1 //===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific DAG Nodes.
21 def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>;
22 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
23 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
25 def PPCfsel : SDNode<"PPCISD::FSEL",
26 // Type constraint for fsel.
27 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
28 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
30 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
31 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
33 //===----------------------------------------------------------------------===//
34 // PowerPC specific transformation functions and pattern fragments.
37 def SHL32 : SDNodeXForm<imm, [{
38 // Transformation function: 31 - imm
39 return getI32Imm(31 - N->getValue());
42 def SHL64 : SDNodeXForm<imm, [{
43 // Transformation function: 63 - imm
44 return getI32Imm(63 - N->getValue());
47 def SRL32 : SDNodeXForm<imm, [{
48 // Transformation function: 32 - imm
49 return N->getValue() ? getI32Imm(32 - N->getValue()) : getI32Imm(0);
52 def SRL64 : SDNodeXForm<imm, [{
53 // Transformation function: 64 - imm
54 return N->getValue() ? getI32Imm(64 - N->getValue()) : getI32Imm(0);
57 def LO16 : SDNodeXForm<imm, [{
58 // Transformation function: get the low 16 bits.
59 return getI32Imm((unsigned short)N->getValue());
62 def HI16 : SDNodeXForm<imm, [{
63 // Transformation function: shift the immediate value down into the low bits.
64 return getI32Imm((unsigned)N->getValue() >> 16);
67 def HA16 : SDNodeXForm<imm, [{
68 // Transformation function: shift the immediate value down into the low bits.
69 signed int Val = N->getValue();
70 return getI32Imm((Val - (signed short)Val) >> 16);
74 def immSExt16 : PatLeaf<(imm), [{
75 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
76 // field. Used by instructions like 'addi'.
77 return (int)N->getValue() == (short)N->getValue();
79 def immZExt16 : PatLeaf<(imm), [{
80 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
81 // field. Used by instructions like 'ori'.
82 return (unsigned)N->getValue() == (unsigned short)N->getValue();
85 def imm16Shifted : PatLeaf<(imm), [{
86 // imm16Shifted predicate - True if only bits in the top 16-bits of the
87 // immediate are set. Used by instructions like 'addis'.
88 return ((unsigned)N->getValue() & 0xFFFF0000U) == (unsigned)N->getValue();
92 // Example of a legalize expander: Only for PPC64.
93 def : Expander<(set i64:$dst, (fp_to_sint f64:$src)),
94 [(set f64:$tmp , (FCTIDZ f64:$src)),
95 (set i32:$tmpFI, (CreateNewFrameIndex 8, 8)),
96 (store f64:$tmp, i32:$tmpFI),
97 (set i64:$dst, (load i32:$tmpFI))],
101 //===----------------------------------------------------------------------===//
102 // PowerPC Flag Definitions.
104 class isPPC64 { bit PPC64 = 1; }
105 class isVMX { bit VMX = 1; }
107 list<Register> Defs = [CR0];
113 //===----------------------------------------------------------------------===//
114 // PowerPC Operand Definitions.
116 def u5imm : Operand<i32> {
117 let PrintMethod = "printU5ImmOperand";
119 def u6imm : Operand<i32> {
120 let PrintMethod = "printU6ImmOperand";
122 def s16imm : Operand<i32> {
123 let PrintMethod = "printS16ImmOperand";
125 def u16imm : Operand<i32> {
126 let PrintMethod = "printU16ImmOperand";
128 def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing.
129 let PrintMethod = "printS16X4ImmOperand";
131 def target : Operand<i32> {
132 let PrintMethod = "printBranchOperand";
134 def aaddr : Operand<i32> {
135 let PrintMethod = "printAbsAddrOperand";
137 def piclabel: Operand<i32> {
138 let PrintMethod = "printPICLabel";
140 def symbolHi: Operand<i32> {
141 let PrintMethod = "printSymbolHi";
143 def symbolLo: Operand<i32> {
144 let PrintMethod = "printSymbolLo";
146 def crbitm: Operand<i8> {
147 let PrintMethod = "printcrbitm";
152 //===----------------------------------------------------------------------===//
153 // PowerPC Instruction Definitions.
155 // Pseudo-instructions:
156 def PHI : Pseudo<(ops variable_ops), "; PHI", []>;
159 def ADJCALLSTACKDOWN : Pseudo<(ops u16imm:$amt), "; ADJCALLSTACKDOWN", []>;
160 def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt), "; ADJCALLSTACKUP", []>;
162 def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC",
163 [(set GPRC:$rD, (undef))]>;
164 def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "; %rD = IMPLICIT_DEF_F8",
165 [(set F8RC:$rD, (undef))]>;
166 def IMPLICIT_DEF_F4 : Pseudo<(ops F4RC:$rD), "; %rD = IMPLICIT_DEF_F4",
167 [(set F4RC:$rD, (undef))]>;
169 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
170 // scheduler into a branch sequence.
171 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
172 def SELECT_CC_Int : Pseudo<(ops GPRC:$dst, CRRC:$cond, GPRC:$T, GPRC:$F,
173 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
174 def SELECT_CC_F4 : Pseudo<(ops F4RC:$dst, CRRC:$cond, F4RC:$T, F4RC:$F,
175 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
176 def SELECT_CC_F8 : Pseudo<(ops F8RC:$dst, CRRC:$cond, F8RC:$T, F8RC:$F,
177 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
181 let isTerminator = 1 in {
183 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr", BrB>;
184 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr", BrB>;
188 def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label", []>;
190 let isBranch = 1, isTerminator = 1 in {
191 def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm:$opc,
192 target:$true, target:$false),
193 "; COND_BRANCH", []>;
194 def B : IForm<18, 0, 0, (ops target:$func), "b $func", BrB>;
196 // FIXME: 4*CR# needs to be added to the BI field!
197 // This will only work for CR0 as it stands now
198 def BLT : BForm<16, 0, 0, 12, 0, (ops CRRC:$crS, target:$block),
199 "blt $crS, $block", BrB>;
200 def BLE : BForm<16, 0, 0, 4, 1, (ops CRRC:$crS, target:$block),
201 "ble $crS, $block", BrB>;
202 def BEQ : BForm<16, 0, 0, 12, 2, (ops CRRC:$crS, target:$block),
203 "beq $crS, $block", BrB>;
204 def BGE : BForm<16, 0, 0, 4, 0, (ops CRRC:$crS, target:$block),
205 "bge $crS, $block", BrB>;
206 def BGT : BForm<16, 0, 0, 12, 1, (ops CRRC:$crS, target:$block),
207 "bgt $crS, $block", BrB>;
208 def BNE : BForm<16, 0, 0, 4, 2, (ops CRRC:$crS, target:$block),
209 "bne $crS, $block", BrB>;
210 def BUN : BForm<16, 0, 0, 12, 3, (ops CRRC:$crS, target:$block),
211 "bun $crS, $block", BrB>;
212 def BNU : BForm<16, 0, 0, 4, 3, (ops CRRC:$crS, target:$block),
213 "bnu $crS, $block", BrB>;
217 // All calls clobber the non-callee saved registers...
218 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
219 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
221 CR0,CR1,CR5,CR6,CR7] in {
222 // Convenient aliases for call instructions
223 def BL : IForm<18, 0, 1, (ops target:$func, variable_ops), "bl $func", BrB>;
224 def BLA : IForm<18, 1, 1, (ops aaddr:$func, variable_ops), "bla $func", BrB>;
225 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (ops variable_ops), "bctrl", BrB>;
228 // D-Form instructions. Most instructions that perform an operation on a
229 // register and an immediate are of this type.
232 def LBZ : DForm_1<34, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
233 "lbz $rD, $disp($rA)", LdStGeneral>;
234 def LHA : DForm_1<42, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
235 "lha $rD, $disp($rA)", LdStLHA>;
236 def LHZ : DForm_1<40, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
237 "lhz $rD, $disp($rA)", LdStGeneral>;
238 def LMW : DForm_1<46, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
239 "lmw $rD, $disp($rA)", LdStLMW>;
240 def LWZ : DForm_1<32, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
241 "lwz $rD, $disp($rA)", LdStGeneral>;
242 def LWZU : DForm_1<35, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
243 "lwzu $rD, $disp($rA)", LdStGeneral>;
245 def ADDI : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
246 "addi $rD, $rA, $imm", IntGeneral,
247 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
248 def ADDIC : DForm_2<12, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
249 "addic $rD, $rA, $imm", IntGeneral,
251 def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
252 "addic. $rD, $rA, $imm", IntGeneral,
254 def ADDIS : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$imm),
255 "addis $rD, $rA, $imm", IntGeneral,
256 [(set GPRC:$rD, (add GPRC:$rA, imm16Shifted:$imm))]>;
257 def LA : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym),
258 "la $rD, $sym($rA)", IntGeneral,
260 def MULLI : DForm_2< 7, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
261 "mulli $rD, $rA, $imm", IntMulLI,
262 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
263 def SUBFIC : DForm_2< 8, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
264 "subfic $rD, $rA, $imm", IntGeneral,
265 [(set GPRC:$rD, (sub immSExt16:$imm, GPRC:$rA))]>;
266 def LI : DForm_2_r0<14, (ops GPRC:$rD, symbolLo:$imm),
267 "li $rD, $imm", IntGeneral,
268 [(set GPRC:$rD, immSExt16:$imm)]>;
269 def LIS : DForm_2_r0<15, (ops GPRC:$rD, symbolHi:$imm),
270 "lis $rD, $imm", IntGeneral,
271 [(set GPRC:$rD, imm16Shifted:$imm)]>;
273 def STMW : DForm_3<47, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
274 "stmw $rS, $disp($rA)", LdStLMW>;
275 def STB : DForm_3<38, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
276 "stb $rS, $disp($rA)", LdStGeneral>;
277 def STH : DForm_3<44, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
278 "sth $rS, $disp($rA)", LdStGeneral>;
279 def STW : DForm_3<36, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
280 "stw $rS, $disp($rA)", LdStGeneral>;
281 def STWU : DForm_3<37, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
282 "stwu $rS, $disp($rA)", LdStGeneral>;
284 def ANDIo : DForm_4<28, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
285 "andi. $dst, $src1, $src2", IntGeneral,
287 def ANDISo : DForm_4<29, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
288 "andis. $dst, $src1, $src2", IntGeneral,
290 def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
291 "ori $dst, $src1, $src2", IntGeneral,
292 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
293 def ORIS : DForm_4<25, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
294 "oris $dst, $src1, $src2", IntGeneral,
295 [(set GPRC:$dst, (or GPRC:$src1, imm16Shifted:$src2))]>;
296 def XORI : DForm_4<26, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
297 "xori $dst, $src1, $src2", IntGeneral,
298 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
299 def XORIS : DForm_4<27, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
300 "xoris $dst, $src1, $src2", IntGeneral,
301 [(set GPRC:$dst, (xor GPRC:$src1, imm16Shifted:$src2))]>;
302 def NOP : DForm_4_zero<24, (ops), "nop", IntGeneral>;
303 def CMPI : DForm_5<11, (ops CRRC:$crD, i1imm:$L, GPRC:$rA, s16imm:$imm),
304 "cmpi $crD, $L, $rA, $imm", IntCompare>;
305 def CMPWI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
306 "cmpwi $crD, $rA, $imm", IntCompare>;
307 def CMPDI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
308 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64;
309 def CMPLI : DForm_6<10, (ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2),
310 "cmpli $dst, $size, $src1, $src2", IntCompare>;
311 def CMPLWI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
312 "cmplwi $dst, $src1, $src2", IntCompare>;
313 def CMPLDI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
314 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64;
316 def LFS : DForm_8<48, (ops F4RC:$rD, symbolLo:$disp, GPRC:$rA),
317 "lfs $rD, $disp($rA)", LdStLFDU>;
318 def LFD : DForm_8<50, (ops F8RC:$rD, symbolLo:$disp, GPRC:$rA),
319 "lfd $rD, $disp($rA)", LdStLFD>;
322 def STFS : DForm_9<52, (ops F4RC:$rS, symbolLo:$disp, GPRC:$rA),
323 "stfs $rS, $disp($rA)", LdStUX>;
324 def STFD : DForm_9<54, (ops F8RC:$rS, symbolLo:$disp, GPRC:$rA),
325 "stfd $rS, $disp($rA)", LdStUX>;
328 // DS-Form instructions. Load/Store instructions available in PPC-64
331 def LWA : DSForm_1<58, 2, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
332 "lwa $rT, $DS($rA)", LdStLWA>, isPPC64;
333 def LD : DSForm_2<58, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
334 "ld $rT, $DS($rA)", LdStLD>, isPPC64;
337 def STD : DSForm_2<62, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
338 "std $rT, $DS($rA)", LdStSTD>, isPPC64;
339 def STDU : DSForm_2<62, 1, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
340 "stdu $rT, $DS($rA)", LdStSTD>, isPPC64;
343 // X-Form instructions. Most instructions that perform an operation on a
344 // register and another register are of this type.
347 def LBZX : XForm_1<31, 87, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
348 "lbzx $dst, $base, $index", LdStGeneral>;
349 def LHAX : XForm_1<31, 343, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
350 "lhax $dst, $base, $index", LdStLHA>;
351 def LHZX : XForm_1<31, 279, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
352 "lhzx $dst, $base, $index", LdStGeneral>;
353 def LWAX : XForm_1<31, 341, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
354 "lwax $dst, $base, $index", LdStLHA>, isPPC64;
355 def LWZX : XForm_1<31, 23, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
356 "lwzx $dst, $base, $index", LdStGeneral>;
357 def LDX : XForm_1<31, 21, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
358 "ldx $dst, $base, $index", LdStLD>, isPPC64;
360 def NAND : XForm_6<31, 476, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
361 "nand $rA, $rS, $rB", IntGeneral,
362 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
363 def AND : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
364 "and $rA, $rS, $rB", IntGeneral,
365 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
366 def ANDo : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
367 "and. $rA, $rS, $rB", IntGeneral,
369 def ANDC : XForm_6<31, 60, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
370 "andc $rA, $rS, $rB", IntGeneral,
371 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
372 def OR4 : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
373 "or $rA, $rS, $rB", IntGeneral,
374 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
375 def OR8 : XForm_6<31, 444, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
376 "or $rA, $rS, $rB", IntGeneral,
377 [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>;
378 def OR4To8 : XForm_6<31, 444, (ops G8RC:$rA, GPRC:$rS, GPRC:$rB),
379 "or $rA, $rS, $rB", IntGeneral,
381 def OR8To4 : XForm_6<31, 444, (ops GPRC:$rA, G8RC:$rS, G8RC:$rB),
382 "or $rA, $rS, $rB", IntGeneral,
384 def NOR : XForm_6<31, 124, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
385 "nor $rA, $rS, $rB", IntGeneral,
386 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
387 def ORo : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
388 "or. $rA, $rS, $rB", IntGeneral,
390 def ORC : XForm_6<31, 412, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
391 "orc $rA, $rS, $rB", IntGeneral,
392 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
393 def EQV : XForm_6<31, 284, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
394 "eqv $rA, $rS, $rB", IntGeneral,
395 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
396 def XOR : XForm_6<31, 316, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
397 "xor $rA, $rS, $rB", IntGeneral,
398 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
399 def SLD : XForm_6<31, 27, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
400 "sld $rA, $rS, $rB", IntRotateD,
401 [(set G8RC:$rA, (shl G8RC:$rS, G8RC:$rB))]>, isPPC64;
402 def SLW : XForm_6<31, 24, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
403 "slw $rA, $rS, $rB", IntGeneral,
404 [(set GPRC:$rA, (shl GPRC:$rS, GPRC:$rB))]>;
405 def SRD : XForm_6<31, 539, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
406 "srd $rA, $rS, $rB", IntRotateD,
407 [(set G8RC:$rA, (srl G8RC:$rS, G8RC:$rB))]>, isPPC64;
408 def SRW : XForm_6<31, 536, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
409 "srw $rA, $rS, $rB", IntGeneral,
410 [(set GPRC:$rA, (srl GPRC:$rS, GPRC:$rB))]>;
411 def SRAD : XForm_6<31, 794, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
412 "srad $rA, $rS, $rB", IntRotateD,
413 [(set G8RC:$rA, (sra G8RC:$rS, G8RC:$rB))]>, isPPC64;
414 def SRAW : XForm_6<31, 792, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
415 "sraw $rA, $rS, $rB", IntShift,
416 [(set GPRC:$rA, (sra GPRC:$rS, GPRC:$rB))]>;
418 def STBX : XForm_8<31, 215, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
419 "stbx $rS, $rA, $rB", LdStGeneral>;
420 def STHX : XForm_8<31, 407, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
421 "sthx $rS, $rA, $rB", LdStGeneral>;
422 def STWX : XForm_8<31, 151, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
423 "stwx $rS, $rA, $rB", LdStGeneral>;
424 def STWUX : XForm_8<31, 183, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
425 "stwux $rS, $rA, $rB", LdStGeneral>;
426 def STDX : XForm_8<31, 149, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
427 "stdx $rS, $rA, $rB", LdStSTD>, isPPC64;
428 def STDUX : XForm_8<31, 181, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
429 "stdux $rS, $rA, $rB", LdStSTD>, isPPC64;
431 def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
432 "srawi $rA, $rS, $SH", IntShift,
433 [(set GPRC:$rA, (sra GPRC:$rS, imm:$SH))]>;
434 def CNTLZW : XForm_11<31, 26, (ops GPRC:$rA, GPRC:$rS),
435 "cntlzw $rA, $rS", IntGeneral,
436 [(set GPRC:$rA, (ctlz GPRC:$rS))]>;
437 def EXTSB : XForm_11<31, 954, (ops GPRC:$rA, GPRC:$rS),
438 "extsb $rA, $rS", IntGeneral,
439 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
440 def EXTSH : XForm_11<31, 922, (ops GPRC:$rA, GPRC:$rS),
441 "extsh $rA, $rS", IntGeneral,
442 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
443 def EXTSW : XForm_11<31, 986, (ops GPRC:$rA, GPRC:$rS),
444 "extsw $rA, $rS", IntRotateD,
446 def CMP : XForm_16<31, 0, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
447 "cmp $crD, $long, $rA, $rB", IntCompare>;
448 def CMPL : XForm_16<31, 32, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
449 "cmpl $crD, $long, $rA, $rB", IntCompare>;
450 def CMPW : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
451 "cmpw $crD, $rA, $rB", IntCompare>;
452 def CMPD : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
453 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64;
454 def CMPLW : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
455 "cmplw $crD, $rA, $rB", IntCompare>;
456 def CMPLD : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
457 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64;
458 //def FCMPO : XForm_17<63, 32, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
459 // "fcmpo $crD, $fA, $fB", FPCompare>;
460 def FCMPUS : XForm_17<63, 0, (ops CRRC:$crD, F4RC:$fA, F4RC:$fB),
461 "fcmpu $crD, $fA, $fB", FPCompare>;
462 def FCMPUD : XForm_17<63, 0, (ops CRRC:$crD, F8RC:$fA, F8RC:$fB),
463 "fcmpu $crD, $fA, $fB", FPCompare>;
466 def LFSX : XForm_25<31, 535, (ops F4RC:$dst, GPRC:$base, GPRC:$index),
467 "lfsx $dst, $base, $index", LdStLFDU>;
468 def LFDX : XForm_25<31, 599, (ops F8RC:$dst, GPRC:$base, GPRC:$index),
469 "lfdx $dst, $base, $index", LdStLFDU>;
471 def FCFID : XForm_26<63, 846, (ops F8RC:$frD, F8RC:$frB),
472 "fcfid $frD, $frB", FPGeneral,
473 [(set F8RC:$frD, (PPCfcfid F8RC:$frB))]>, isPPC64;
474 def FCTIDZ : XForm_26<63, 815, (ops F8RC:$frD, F8RC:$frB),
475 "fctidz $frD, $frB", FPGeneral,
476 [(set F8RC:$frD, (PPCfctidz F8RC:$frB))]>, isPPC64;
477 def FCTIWZ : XForm_26<63, 15, (ops F8RC:$frD, F8RC:$frB),
478 "fctiwz $frD, $frB", FPGeneral,
479 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>;
480 def FRSP : XForm_26<63, 12, (ops F4RC:$frD, F8RC:$frB),
481 "frsp $frD, $frB", FPGeneral,
482 [(set F4RC:$frD, (fround F8RC:$frB))]>;
483 def FSQRT : XForm_26<63, 22, (ops F8RC:$frD, F8RC:$frB),
484 "fsqrt $frD, $frB", FPSqrt,
485 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>;
486 def FSQRTS : XForm_26<59, 22, (ops F4RC:$frD, F4RC:$frB),
487 "fsqrts $frD, $frB", FPSqrt,
488 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>;
490 /// FMR is split into 3 versions, one for 4/8 byte FP, and one for extending.
491 def FMRS : XForm_26<63, 72, (ops F4RC:$frD, F4RC:$frB),
492 "fmr $frD, $frB", FPGeneral,
493 []>; // (set F4RC:$frD, F4RC:$frB)
494 def FMRD : XForm_26<63, 72, (ops F8RC:$frD, F8RC:$frB),
495 "fmr $frD, $frB", FPGeneral,
496 []>; // (set F8RC:$frD, F8RC:$frB)
497 def FMRSD : XForm_26<63, 72, (ops F8RC:$frD, F4RC:$frB),
498 "fmr $frD, $frB", FPGeneral,
499 [(set F8RC:$frD, (fextend F4RC:$frB))]>;
501 // These are artificially split into two different forms, for 4/8 byte FP.
502 def FABSS : XForm_26<63, 264, (ops F4RC:$frD, F4RC:$frB),
503 "fabs $frD, $frB", FPGeneral,
504 [(set F4RC:$frD, (fabs F4RC:$frB))]>;
505 def FABSD : XForm_26<63, 264, (ops F8RC:$frD, F8RC:$frB),
506 "fabs $frD, $frB", FPGeneral,
507 [(set F8RC:$frD, (fabs F8RC:$frB))]>;
508 def FNABSS : XForm_26<63, 136, (ops F4RC:$frD, F4RC:$frB),
509 "fnabs $frD, $frB", FPGeneral,
510 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>;
511 def FNABSD : XForm_26<63, 136, (ops F8RC:$frD, F8RC:$frB),
512 "fnabs $frD, $frB", FPGeneral,
513 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>;
514 def FNEGS : XForm_26<63, 40, (ops F4RC:$frD, F4RC:$frB),
515 "fneg $frD, $frB", FPGeneral,
516 [(set F4RC:$frD, (fneg F4RC:$frB))]>;
517 def FNEGD : XForm_26<63, 40, (ops F8RC:$frD, F8RC:$frB),
518 "fneg $frD, $frB", FPGeneral,
519 [(set F8RC:$frD, (fneg F8RC:$frB))]>;
523 def STFSX : XForm_28<31, 663, (ops F4RC:$frS, GPRC:$rA, GPRC:$rB),
524 "stfsx $frS, $rA, $rB", LdStUX>;
525 def STFDX : XForm_28<31, 727, (ops F8RC:$frS, GPRC:$rA, GPRC:$rB),
526 "stfdx $frS, $rA, $rB", LdStUX>;
529 // XL-Form instructions. condition register logical ops.
531 def MCRF : XLForm_3<19, 0, (ops CRRC:$BF, CRRC:$BFA),
532 "mcrf $BF, $BFA", BrMCR>;
534 // XFX-Form instructions. Instructions that deal with SPRs
536 // Note that although LR should be listed as `8' and CTR as `9' in the SPR
537 // field, the manual lists the groups of bits as [5-9] = 0, [0-4] = 8 or 9
538 // which means the SPR value needs to be multiplied by a factor of 32.
539 def MFCTR : XFXForm_1_ext<31, 339, 288, (ops GPRC:$rT), "mfctr $rT", SprMFSPR>;
540 def MFLR : XFXForm_1_ext<31, 339, 256, (ops GPRC:$rT), "mflr $rT", SprMFSPR>;
541 def MFCR : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT", SprMFCR>;
542 def MTCRF : XFXForm_5<31, 144, (ops crbitm:$FXM, GPRC:$rS),
543 "mtcrf $FXM, $rS", BrMCRX>;
544 def MFOCRF : XFXForm_5a<31, 19, (ops GPRC:$rT, crbitm:$FXM),
545 "mfcr $rT, $FXM", SprMFCR>;
546 def MTCTR : XFXForm_7_ext<31, 467, 288, (ops GPRC:$rS), "mtctr $rS", SprMTSPR>;
547 def MTLR : XFXForm_7_ext<31, 467, 256, (ops GPRC:$rS), "mtlr $rS", SprMTSPR>;
549 // XS-Form instructions. Just 'sradi'
551 def SRADI : XSForm_1<31, 413, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH),
552 "sradi $rA, $rS, $SH", IntRotateD>, isPPC64;
554 // XO-Form instructions. Arithmetic instructions that can set overflow bit
556 def ADD4 : XOForm_1<31, 266, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
557 "add $rT, $rA, $rB", IntGeneral,
558 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
559 def ADD8 : XOForm_1<31, 266, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
560 "add $rT, $rA, $rB", IntGeneral,
561 [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>;
562 def ADDC : XOForm_1<31, 10, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
563 "addc $rT, $rA, $rB", IntGeneral,
565 def ADDE : XOForm_1<31, 138, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
566 "adde $rT, $rA, $rB", IntGeneral,
568 def DIVD : XOForm_1<31, 489, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
569 "divd $rT, $rA, $rB", IntDivD,
570 [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64;
571 def DIVDU : XOForm_1<31, 457, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
572 "divdu $rT, $rA, $rB", IntDivD,
573 [(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64;
574 def DIVW : XOForm_1<31, 491, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
575 "divw $rT, $rA, $rB", IntDivW,
576 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>;
577 def DIVWU : XOForm_1<31, 459, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
578 "divwu $rT, $rA, $rB", IntDivW,
579 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>;
580 def MULHD : XOForm_1<31, 73, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
581 "mulhd $rT, $rA, $rB", IntMulHW,
582 [(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>;
583 def MULHDU : XOForm_1<31, 9, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
584 "mulhdu $rT, $rA, $rB", IntMulHWU,
585 [(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))]>;
586 def MULHW : XOForm_1<31, 75, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
587 "mulhw $rT, $rA, $rB", IntMulHW,
588 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
589 def MULHWU : XOForm_1<31, 11, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
590 "mulhwu $rT, $rA, $rB", IntMulHWU,
591 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
592 def MULLD : XOForm_1<31, 233, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
593 "mulld $rT, $rA, $rB", IntMulHD,
594 [(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64;
595 def MULLW : XOForm_1<31, 235, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
596 "mullw $rT, $rA, $rB", IntMulHW,
597 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
598 def SUBF : XOForm_1<31, 40, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
599 "subf $rT, $rA, $rB", IntGeneral,
600 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
601 def SUBFC : XOForm_1<31, 8, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
602 "subfc $rT, $rA, $rB", IntGeneral,
604 def SUBFE : XOForm_1<31, 136, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
605 "subfe $rT, $rA, $rB", IntGeneral,
607 def ADDME : XOForm_3<31, 234, 0, (ops GPRC:$rT, GPRC:$rA),
608 "addme $rT, $rA", IntGeneral,
610 def ADDZE : XOForm_3<31, 202, 0, (ops GPRC:$rT, GPRC:$rA),
611 "addze $rT, $rA", IntGeneral,
613 def NEG : XOForm_3<31, 104, 0, (ops GPRC:$rT, GPRC:$rA),
614 "neg $rT, $rA", IntGeneral,
615 [(set GPRC:$rT, (ineg GPRC:$rA))]>;
616 def SUBFZE : XOForm_3<31, 200, 0, (ops GPRC:$rT, GPRC:$rA),
617 "subfze $rT, $rA", IntGeneral,
620 // A-Form instructions. Most of the instructions executed in the FPU are of
623 def FMADD : AForm_1<63, 29,
624 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
625 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused,
626 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC),
628 def FMADDS : AForm_1<59, 29,
629 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
630 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
631 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
633 def FMSUB : AForm_1<63, 28,
634 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
635 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused,
636 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC),
638 def FMSUBS : AForm_1<59, 28,
639 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
640 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
641 [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC),
643 def FNMADD : AForm_1<63, 31,
644 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
645 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused,
646 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC),
648 def FNMADDS : AForm_1<59, 31,
649 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
650 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
651 [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC),
653 def FNMSUB : AForm_1<63, 30,
654 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
655 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused,
656 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC),
658 def FNMSUBS : AForm_1<59, 30,
659 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
660 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
661 [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC),
663 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
664 // having 4 of these, force the comparison to always be an 8-byte double (code
665 // should use an FMRSD if the input comparison value really wants to be a float)
666 // and 4/8 byte forms for the result and operand type..
667 def FSELD : AForm_1<63, 23,
668 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
669 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
670 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>;
671 def FSELS : AForm_1<63, 23,
672 (ops F4RC:$FRT, F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
673 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
674 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>;
675 def FADD : AForm_2<63, 21,
676 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
677 "fadd $FRT, $FRA, $FRB", FPGeneral,
678 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>;
679 def FADDS : AForm_2<59, 21,
680 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
681 "fadds $FRT, $FRA, $FRB", FPGeneral,
682 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>;
683 def FDIV : AForm_2<63, 18,
684 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
685 "fdiv $FRT, $FRA, $FRB", FPDivD,
686 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>;
687 def FDIVS : AForm_2<59, 18,
688 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
689 "fdivs $FRT, $FRA, $FRB", FPDivS,
690 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>;
691 def FMUL : AForm_3<63, 25,
692 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
693 "fmul $FRT, $FRA, $FRB", FPFused,
694 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>;
695 def FMULS : AForm_3<59, 25,
696 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
697 "fmuls $FRT, $FRA, $FRB", FPGeneral,
698 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>;
699 def FSUB : AForm_2<63, 20,
700 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
701 "fsub $FRT, $FRA, $FRB", FPGeneral,
702 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>;
703 def FSUBS : AForm_2<59, 20,
704 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
705 "fsubs $FRT, $FRA, $FRB", FPGeneral,
706 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>;
708 // M-Form instructions. rotate and mask instructions.
710 let isTwoAddress = 1, isCommutable = 1 in {
711 // RLWIMI can be commuted if the rotate amount is zero.
712 def RLWIMI : MForm_2<20,
713 (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
714 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate,
716 def RLDIMI : MDForm_1<30, 3,
717 (ops G8RC:$rA, G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB),
718 "rldimi $rA, $rS, $SH, $MB", IntRotateD,
721 def RLWINM : MForm_2<21,
722 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
723 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
725 def RLWINMo : MForm_2<21,
726 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
727 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
729 def RLWNM : MForm_2<23,
730 (ops GPRC:$rA, GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
731 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral,
734 // MD-Form instructions. 64 bit rotate instructions.
736 def RLDICL : MDForm_1<30, 0,
737 (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$MB),
738 "rldicl $rA, $rS, $SH, $MB", IntRotateD,
740 def RLDICR : MDForm_1<30, 1,
741 (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$ME),
742 "rldicr $rA, $rS, $SH, $ME", IntRotateD,
745 //===----------------------------------------------------------------------===//
746 // PowerPC Instruction Patterns
749 // Arbitrary immediate support. Implement in terms of LIS/ORI.
750 def : Pat<(i32 imm:$imm),
751 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
753 // Implement the 'not' operation with the NOR instruction.
754 def NOT : Pat<(not GPRC:$in),
755 (NOR GPRC:$in, GPRC:$in)>;
757 // ADD an arbitrary immediate.
758 def : Pat<(add GPRC:$in, imm:$imm),
759 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
760 // OR an arbitrary immediate.
761 def : Pat<(or GPRC:$in, imm:$imm),
762 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
763 // XOR an arbitrary immediate.
764 def : Pat<(xor GPRC:$in, imm:$imm),
765 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
766 def : Pat<(or (shl GPRC:$rS, GPRC:$rB),
767 (srl GPRC:$rS, (sub 32, GPRC:$rB))),
768 (RLWNM GPRC:$rS, GPRC:$rB, 0, 31)>;
770 def : Pat<(zext GPRC:$in),
771 (RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>;
772 def : Pat<(anyext GPRC:$in),
773 (OR4To8 GPRC:$in, GPRC:$in)>;
774 def : Pat<(trunc G8RC:$in),
775 (OR8To4 G8RC:$in, G8RC:$in)>;
778 def : Pat<(shl GPRC:$in, imm:$imm),
779 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>;
780 def : Pat<(shl G8RC:$in, imm:$imm),
781 (RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>;
783 def : Pat<(srl GPRC:$in, imm:$imm),
784 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>;
785 def : Pat<(srl G8RC:$in, imm:$imm),
786 (RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>;
788 // Hi and Lo for Darwin Global Addresses.
789 def : Pat<(PPChi tglobaladdr:$in, (i32 0)), (LIS node:$in)>;
790 def : Pat<(PPClo tglobaladdr:$in, (i32 0)), (LI node:$in)>;
793 // Same as above, but using a temporary. FIXME: implement temporaries :)
795 def : Pattern<(xor GPRC:$in, imm:$imm),
796 [(set GPRC:$tmp, (XORI GPRC:$in, (LO16 imm:$imm))),
797 (XORIS GPRC:$tmp, (HI16 imm:$imm))]>;
800 //===----------------------------------------------------------------------===//
801 // PowerPCInstrInfo Definition
803 def PowerPCInstrInfo : InstrInfo {
806 let TSFlagsFields = [ "VMX", "PPC64" ];
807 let TSFlagsShifts = [ 0, 1 ];
809 let isLittleEndianEncoding = 1;