1 //===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
24 def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
26 def SDT_PPCvperm : SDTypeProfile<1, 3, [
27 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
30 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
31 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
34 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
35 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
38 def SDT_PPClbrx : SDTypeProfile<1, 2, [
39 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
41 def SDT_PPCstbrx : SDTypeProfile<0, 3, [
42 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
45 def SDT_PPClarx : SDTypeProfile<1, 1, [
46 SDTCisInt<0>, SDTCisPtrTy<1>
48 def SDT_PPCstcx : SDTypeProfile<0, 2, [
49 SDTCisInt<0>, SDTCisPtrTy<1>
52 def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
53 SDTCisPtrTy<0>, SDTCisVT<1, i32>
56 def SDT_PPCnop : SDTypeProfile<0, 0, []>;
58 //===----------------------------------------------------------------------===//
59 // PowerPC specific DAG Nodes.
62 def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>;
63 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
64 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
65 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
66 [SDNPHasChain, SDNPMayStore]>;
68 // This sequence is used for long double->int conversions. It changes the
69 // bits in the FPSCR which is not modelled.
70 def PPCmffs : SDNode<"PPCISD::MFFS", SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>,
72 def PPCmtfsb0 : SDNode<"PPCISD::MTFSB0", SDTypeProfile<0, 1, [SDTCisInt<0>]>,
73 [SDNPInGlue, SDNPOutGlue]>;
74 def PPCmtfsb1 : SDNode<"PPCISD::MTFSB1", SDTypeProfile<0, 1, [SDTCisInt<0>]>,
75 [SDNPInGlue, SDNPOutGlue]>;
76 def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp,
77 [SDNPInGlue, SDNPOutGlue]>;
78 def PPCmtfsf : SDNode<"PPCISD::MTFSF", SDTypeProfile<1, 3,
79 [SDTCisVT<0, f64>, SDTCisInt<1>, SDTCisVT<2, f64>,
83 def PPCfsel : SDNode<"PPCISD::FSEL",
84 // Type constraint for fsel.
85 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
86 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
88 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
89 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
90 def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, [SDNPMayLoad]>;
91 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
92 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
94 def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>;
95 def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp,
97 def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>;
98 def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>;
99 def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>;
100 def PPCgetTlsAddr : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>;
101 def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>;
102 def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>;
103 def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>;
104 def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp,
106 def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>;
108 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
110 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
111 // amounts. These nodes are generated by the multi-precision shift code.
112 def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>;
113 def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>;
114 def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>;
116 def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>;
117 def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore,
118 [SDNPHasChain, SDNPMayStore]>;
120 // These are target-independent nodes, but have target-specific formats.
121 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
122 [SDNPHasChain, SDNPOutGlue]>;
123 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd,
124 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
126 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
127 def PPCcall_Darwin : SDNode<"PPCISD::CALL_Darwin", SDT_PPCCall,
128 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
130 def PPCcall_SVR4 : SDNode<"PPCISD::CALL_SVR4", SDT_PPCCall,
131 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
133 def PPCcall_nop_SVR4 : SDNode<"PPCISD::CALL_NOP_SVR4", SDT_PPCCall,
134 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
136 def PPCnop : SDNode<"PPCISD::NOP", SDT_PPCnop, [SDNPInGlue, SDNPOutGlue]>;
137 def PPCload : SDNode<"PPCISD::LOAD", SDTypeProfile<1, 1, []>,
138 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
139 def PPCload_toc : SDNode<"PPCISD::LOAD_TOC", SDTypeProfile<0, 1, []>,
140 [SDNPHasChain, SDNPSideEffect,
141 SDNPInGlue, SDNPOutGlue]>;
142 def PPCtoc_restore : SDNode<"PPCISD::TOC_RESTORE", SDTypeProfile<0, 0, []>,
143 [SDNPHasChain, SDNPSideEffect,
144 SDNPInGlue, SDNPOutGlue]>;
145 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
146 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
147 def PPCbctrl_Darwin : SDNode<"PPCISD::BCTRL_Darwin", SDTNone,
148 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
151 def PPCbctrl_SVR4 : SDNode<"PPCISD::BCTRL_SVR4", SDTNone,
152 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
155 def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone,
156 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
158 def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
159 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
161 def PPCeh_sjlj_setjmp : SDNode<"PPCISD::EH_SJLJ_SETJMP",
162 SDTypeProfile<1, 1, [SDTCisInt<0>,
164 [SDNPHasChain, SDNPSideEffect]>;
165 def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP",
166 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
167 [SDNPHasChain, SDNPSideEffect]>;
169 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
170 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>;
172 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
173 [SDNPHasChain, SDNPOptInGlue]>;
175 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
176 [SDNPHasChain, SDNPMayLoad]>;
177 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
178 [SDNPHasChain, SDNPMayStore]>;
180 // Instructions to set/unset CR bit 6 for SVR4 vararg calls
181 def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone,
182 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
183 def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone,
184 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
186 // Instructions to support atomic operations
187 def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx,
188 [SDNPHasChain, SDNPMayLoad]>;
189 def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx,
190 [SDNPHasChain, SDNPMayStore]>;
192 // Instructions to support medium and large code model
193 def PPCaddisTocHA : SDNode<"PPCISD::ADDIS_TOC_HA", SDTIntBinOp, []>;
194 def PPCldTocL : SDNode<"PPCISD::LD_TOC_L", SDTIntBinOp, [SDNPMayLoad]>;
195 def PPCaddiTocL : SDNode<"PPCISD::ADDI_TOC_L", SDTIntBinOp, []>;
198 // Instructions to support dynamic alloca.
199 def SDTDynOp : SDTypeProfile<1, 2, []>;
200 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
202 //===----------------------------------------------------------------------===//
203 // PowerPC specific transformation functions and pattern fragments.
206 def SHL32 : SDNodeXForm<imm, [{
207 // Transformation function: 31 - imm
208 return getI32Imm(31 - N->getZExtValue());
211 def SRL32 : SDNodeXForm<imm, [{
212 // Transformation function: 32 - imm
213 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0);
216 def LO16 : SDNodeXForm<imm, [{
217 // Transformation function: get the low 16 bits.
218 return getI32Imm((unsigned short)N->getZExtValue());
221 def HI16 : SDNodeXForm<imm, [{
222 // Transformation function: shift the immediate value down into the low bits.
223 return getI32Imm((unsigned)N->getZExtValue() >> 16);
226 def HA16 : SDNodeXForm<imm, [{
227 // Transformation function: shift the immediate value down into the low bits.
228 signed int Val = N->getZExtValue();
229 return getI32Imm((Val - (signed short)Val) >> 16);
231 def MB : SDNodeXForm<imm, [{
232 // Transformation function: get the start bit of a mask
234 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
235 return getI32Imm(mb);
238 def ME : SDNodeXForm<imm, [{
239 // Transformation function: get the end bit of a mask
241 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
242 return getI32Imm(me);
244 def maskimm32 : PatLeaf<(imm), [{
245 // maskImm predicate - True if immediate is a run of ones.
247 if (N->getValueType(0) == MVT::i32)
248 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
253 def immSExt16 : PatLeaf<(imm), [{
254 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
255 // field. Used by instructions like 'addi'.
256 if (N->getValueType(0) == MVT::i32)
257 return (int32_t)N->getZExtValue() == (short)N->getZExtValue();
259 return (int64_t)N->getZExtValue() == (short)N->getZExtValue();
261 def immZExt16 : PatLeaf<(imm), [{
262 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
263 // field. Used by instructions like 'ori'.
264 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
267 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
268 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
269 // identical in 32-bit mode, but in 64-bit mode, they return true if the
270 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
272 def imm16ShiftedZExt : PatLeaf<(imm), [{
273 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
274 // immediate are set. Used by instructions like 'xoris'.
275 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
278 def imm16ShiftedSExt : PatLeaf<(imm), [{
279 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
280 // immediate are set. Used by instructions like 'addis'. Identical to
281 // imm16ShiftedZExt in 32-bit mode.
282 if (N->getZExtValue() & 0xFFFF) return false;
283 if (N->getValueType(0) == MVT::i32)
285 // For 64-bit, make sure it is sext right.
286 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
289 // Some r+i load/store instructions (such as LD, STD, LDU, etc.) that require
290 // restricted memrix (offset/4) constants are alignment sensitive. If these
291 // offsets are hidden behind TOC entries than the values of the lower-order
292 // bits cannot be checked directly. As a result, we need to also incorporate
293 // an alignment check into the relevant patterns.
295 def aligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
296 return cast<LoadSDNode>(N)->getAlignment() >= 4;
298 def aligned4store : PatFrag<(ops node:$val, node:$ptr),
299 (store node:$val, node:$ptr), [{
300 return cast<StoreSDNode>(N)->getAlignment() >= 4;
302 def aligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
303 return cast<LoadSDNode>(N)->getAlignment() >= 4;
305 def aligned4pre_store : PatFrag<
306 (ops node:$val, node:$base, node:$offset),
307 (pre_store node:$val, node:$base, node:$offset), [{
308 return cast<StoreSDNode>(N)->getAlignment() >= 4;
311 def unaligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
312 return cast<LoadSDNode>(N)->getAlignment() < 4;
314 def unaligned4store : PatFrag<(ops node:$val, node:$ptr),
315 (store node:$val, node:$ptr), [{
316 return cast<StoreSDNode>(N)->getAlignment() < 4;
318 def unaligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
319 return cast<LoadSDNode>(N)->getAlignment() < 4;
322 //===----------------------------------------------------------------------===//
323 // PowerPC Flag Definitions.
325 class isPPC64 { bit PPC64 = 1; }
327 list<Register> Defs = [CR0];
331 class RegConstraint<string C> {
332 string Constraints = C;
334 class NoEncode<string E> {
335 string DisableEncoding = E;
339 //===----------------------------------------------------------------------===//
340 // PowerPC Operand Definitions.
342 def s5imm : Operand<i32> {
343 let PrintMethod = "printS5ImmOperand";
345 def u5imm : Operand<i32> {
346 let PrintMethod = "printU5ImmOperand";
348 def u6imm : Operand<i32> {
349 let PrintMethod = "printU6ImmOperand";
351 def s16imm : Operand<i32> {
352 let PrintMethod = "printS16ImmOperand";
354 def u16imm : Operand<i32> {
355 let PrintMethod = "printU16ImmOperand";
357 def directbrtarget : Operand<OtherVT> {
358 let PrintMethod = "printBranchOperand";
359 let EncoderMethod = "getDirectBrEncoding";
361 def condbrtarget : Operand<OtherVT> {
362 let PrintMethod = "printBranchOperand";
363 let EncoderMethod = "getCondBrEncoding";
365 def calltarget : Operand<iPTR> {
366 let EncoderMethod = "getDirectBrEncoding";
368 def aaddr : Operand<iPTR> {
369 let PrintMethod = "printAbsAddrOperand";
371 def symbolHi: Operand<i32> {
372 let PrintMethod = "printSymbolHi";
373 let EncoderMethod = "getHA16Encoding";
375 def symbolLo: Operand<i32> {
376 let PrintMethod = "printSymbolLo";
377 let EncoderMethod = "getLO16Encoding";
379 def crbitm: Operand<i8> {
380 let PrintMethod = "printcrbitm";
381 let EncoderMethod = "get_crbitm_encoding";
384 // A version of ptr_rc which excludes R0 (or X0 in 64-bit mode).
385 def ptr_rc_nor0 : PointerLikeRegClass<1>;
387 def memri : Operand<iPTR> {
388 let PrintMethod = "printMemRegImm";
389 let MIOperandInfo = (ops symbolLo:$imm, ptr_rc_nor0:$reg);
390 let EncoderMethod = "getMemRIEncoding";
392 def memrr : Operand<iPTR> {
393 let PrintMethod = "printMemRegReg";
394 let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc:$offreg);
396 def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits.
397 let PrintMethod = "printMemRegImmShifted";
398 let MIOperandInfo = (ops symbolLo:$imm, ptr_rc_nor0:$reg);
399 let EncoderMethod = "getMemRIXEncoding";
402 // A single-register address. This is used with the SjLj
403 // pseudo-instructions.
404 def memr : Operand<iPTR> {
405 let MIOperandInfo = (ops ptr_rc:$ptrreg);
408 // PowerPC Predicate operand. 20 = (0<<5)|20 = always, CR0 is a dummy reg
409 // that doesn't matter.
410 def pred : PredicateOperand<OtherVT, (ops imm, CRRC),
411 (ops (i32 20), (i32 zero_reg))> {
412 let PrintMethod = "printPredicateOperand";
415 // Define PowerPC specific addressing mode.
416 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
417 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
418 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
419 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std"
421 // The address in a single register. This is used with the SjLj
422 // pseudo-instructions.
423 def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>;
425 /// This is just the offset part of iaddr, used for preinc.
426 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
428 //===----------------------------------------------------------------------===//
429 // PowerPC Instruction Predicate Definitions.
430 def In32BitMode : Predicate<"!PPCSubTarget.isPPC64()">;
431 def In64BitMode : Predicate<"PPCSubTarget.isPPC64()">;
432 def IsBookE : Predicate<"PPCSubTarget.isBookE()">;
434 //===----------------------------------------------------------------------===//
435 // PowerPC Instruction Definitions.
437 // Pseudo-instructions:
439 let hasCtrlDep = 1 in {
440 let Defs = [R1], Uses = [R1] in {
441 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt",
442 [(callseq_start timm:$amt)]>;
443 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt2",
444 [(callseq_end timm:$amt1, timm:$amt2)]>;
447 def UPDATE_VRSAVE : Pseudo<(outs GPRC:$rD), (ins GPRC:$rS),
448 "UPDATE_VRSAVE $rD, $rS", []>;
451 let Defs = [R1], Uses = [R1] in
452 def DYNALLOC : Pseudo<(outs GPRC:$result), (ins GPRC:$negsize, memri:$fpsi), "#DYNALLOC",
454 (PPCdynalloc GPRC:$negsize, iaddr:$fpsi))]>;
456 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
457 // instruction selection into a branch sequence.
458 let usesCustomInserter = 1, // Expanded after instruction selection.
459 PPC970_Single = 1 in {
460 def SELECT_CC_I4 : Pseudo<(outs GPRC:$dst), (ins CRRC:$cond, GPRC:$T, GPRC:$F,
461 i32imm:$BROPC), "#SELECT_CC_I4",
463 def SELECT_CC_I8 : Pseudo<(outs G8RC:$dst), (ins CRRC:$cond, G8RC:$T, G8RC:$F,
464 i32imm:$BROPC), "#SELECT_CC_I8",
466 def SELECT_CC_F4 : Pseudo<(outs F4RC:$dst), (ins CRRC:$cond, F4RC:$T, F4RC:$F,
467 i32imm:$BROPC), "#SELECT_CC_F4",
469 def SELECT_CC_F8 : Pseudo<(outs F8RC:$dst), (ins CRRC:$cond, F8RC:$T, F8RC:$F,
470 i32imm:$BROPC), "#SELECT_CC_F8",
472 def SELECT_CC_VRRC: Pseudo<(outs VRRC:$dst), (ins CRRC:$cond, VRRC:$T, VRRC:$F,
473 i32imm:$BROPC), "#SELECT_CC_VRRC",
477 // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
478 // scavenge a register for it.
480 def SPILL_CR : Pseudo<(outs), (ins CRRC:$cond, memri:$F),
483 // RESTORE_CR - Indicate that we're restoring the CR register (previously
484 // spilled), so we'll need to scavenge a register for it.
486 def RESTORE_CR : Pseudo<(outs CRRC:$cond), (ins memri:$F),
489 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
490 let isCodeGenOnly = 1, isReturn = 1, Uses = [LR, RM] in
491 def BLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$p),
492 "b${p:cc}lr ${p:reg}", BrB,
494 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in
495 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>;
499 def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>,
502 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
503 let isBarrier = 1 in {
504 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst),
509 // BCC represents an arbitrary conditional branch on a predicate.
510 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
511 // a two-value operand where a dag node expects two operands. :(
512 let isCodeGenOnly = 1 in
513 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst),
514 "b${cond:cc} ${cond:reg}, $dst"
515 /*[(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]*/>;
517 let Defs = [CTR], Uses = [CTR] in {
518 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
520 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
525 // The direct BCL used by the SjLj setjmp code.
526 let isCall = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
527 let Defs = [LR], Uses = [RM] in {
528 def BCL : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst),
534 let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
535 // Convenient aliases for call instructions
537 def BL_Darwin : IForm<18, 0, 1,
538 (outs), (ins calltarget:$func),
539 "bl $func", BrB, []>; // See Pat patterns below.
540 def BLA_Darwin : IForm<18, 1, 1,
541 (outs), (ins aaddr:$func),
542 "bla $func", BrB, [(PPCcall_Darwin (i32 imm:$func))]>;
544 let Uses = [CTR, RM] in {
545 def BCTRL_Darwin : XLForm_2_ext<19, 528, 20, 0, 1,
548 [(PPCbctrl_Darwin)]>, Requires<[In32BitMode]>;
553 let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
554 // Convenient aliases for call instructions
556 def BL_SVR4 : IForm<18, 0, 1,
557 (outs), (ins calltarget:$func),
558 "bl $func", BrB, []>; // See Pat patterns below.
559 def BLA_SVR4 : IForm<18, 1, 1,
560 (outs), (ins aaddr:$func),
562 [(PPCcall_SVR4 (i32 imm:$func))]>;
564 let Uses = [CTR, RM] in {
565 def BCTRL_SVR4 : XLForm_2_ext<19, 528, 20, 0, 1,
568 [(PPCbctrl_SVR4)]>, Requires<[In32BitMode]>;
573 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
574 def TCRETURNdi :Pseudo< (outs),
575 (ins calltarget:$dst, i32imm:$offset),
576 "#TC_RETURNd $dst $offset",
580 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
581 def TCRETURNai :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset),
582 "#TC_RETURNa $func $offset",
583 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
585 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
586 def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset),
587 "#TC_RETURNr $dst $offset",
591 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
592 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in
593 def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
594 Requires<[In32BitMode]>;
598 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
599 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
600 def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
605 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
606 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
607 def TAILBA : IForm<18, 0, 0, (outs), (ins aaddr:$dst),
611 let hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
612 usesCustomInserter = 1 in {
613 def EH_SjLj_SetJmp32 : Pseudo<(outs GPRC:$dst), (ins memr:$buf),
615 [(set GPRC:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
616 Requires<[In32BitMode]>;
617 let isTerminator = 1 in
618 def EH_SjLj_LongJmp32 : Pseudo<(outs), (ins memr:$buf),
619 "#EH_SJLJ_LONGJMP32",
620 [(PPCeh_sjlj_longjmp addr:$buf)]>,
621 Requires<[In32BitMode]>;
624 let isBranch = 1, isTerminator = 1, isCodeGenOnly = 1 in {
625 def EH_SjLj_Setup : Pseudo<(outs), (ins directbrtarget:$dst),
626 "#EH_SjLj_Setup\t$dst", []>;
629 // DCB* instructions.
630 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst),
631 "dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
632 PPC970_DGroup_Single;
633 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst),
634 "dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
635 PPC970_DGroup_Single;
636 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst),
637 "dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
638 PPC970_DGroup_Single;
639 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst),
640 "dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
641 PPC970_DGroup_Single;
642 def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst),
643 "dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
644 PPC970_DGroup_Single;
645 def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst),
646 "dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
647 PPC970_DGroup_Single;
648 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst),
649 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
650 PPC970_DGroup_Single;
651 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst),
652 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
653 PPC970_DGroup_Single;
655 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
659 let usesCustomInserter = 1 in {
660 let Defs = [CR0] in {
661 def ATOMIC_LOAD_ADD_I8 : Pseudo<
662 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_ADD_I8",
663 [(set GPRC:$dst, (atomic_load_add_8 xoaddr:$ptr, GPRC:$incr))]>;
664 def ATOMIC_LOAD_SUB_I8 : Pseudo<
665 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_SUB_I8",
666 [(set GPRC:$dst, (atomic_load_sub_8 xoaddr:$ptr, GPRC:$incr))]>;
667 def ATOMIC_LOAD_AND_I8 : Pseudo<
668 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_AND_I8",
669 [(set GPRC:$dst, (atomic_load_and_8 xoaddr:$ptr, GPRC:$incr))]>;
670 def ATOMIC_LOAD_OR_I8 : Pseudo<
671 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_OR_I8",
672 [(set GPRC:$dst, (atomic_load_or_8 xoaddr:$ptr, GPRC:$incr))]>;
673 def ATOMIC_LOAD_XOR_I8 : Pseudo<
674 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "ATOMIC_LOAD_XOR_I8",
675 [(set GPRC:$dst, (atomic_load_xor_8 xoaddr:$ptr, GPRC:$incr))]>;
676 def ATOMIC_LOAD_NAND_I8 : Pseudo<
677 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_NAND_I8",
678 [(set GPRC:$dst, (atomic_load_nand_8 xoaddr:$ptr, GPRC:$incr))]>;
679 def ATOMIC_LOAD_ADD_I16 : Pseudo<
680 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_ADD_I16",
681 [(set GPRC:$dst, (atomic_load_add_16 xoaddr:$ptr, GPRC:$incr))]>;
682 def ATOMIC_LOAD_SUB_I16 : Pseudo<
683 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_SUB_I16",
684 [(set GPRC:$dst, (atomic_load_sub_16 xoaddr:$ptr, GPRC:$incr))]>;
685 def ATOMIC_LOAD_AND_I16 : Pseudo<
686 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_AND_I16",
687 [(set GPRC:$dst, (atomic_load_and_16 xoaddr:$ptr, GPRC:$incr))]>;
688 def ATOMIC_LOAD_OR_I16 : Pseudo<
689 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_OR_I16",
690 [(set GPRC:$dst, (atomic_load_or_16 xoaddr:$ptr, GPRC:$incr))]>;
691 def ATOMIC_LOAD_XOR_I16 : Pseudo<
692 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_XOR_I16",
693 [(set GPRC:$dst, (atomic_load_xor_16 xoaddr:$ptr, GPRC:$incr))]>;
694 def ATOMIC_LOAD_NAND_I16 : Pseudo<
695 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_NAND_I16",
696 [(set GPRC:$dst, (atomic_load_nand_16 xoaddr:$ptr, GPRC:$incr))]>;
697 def ATOMIC_LOAD_ADD_I32 : Pseudo<
698 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_ADD_I32",
699 [(set GPRC:$dst, (atomic_load_add_32 xoaddr:$ptr, GPRC:$incr))]>;
700 def ATOMIC_LOAD_SUB_I32 : Pseudo<
701 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_SUB_I32",
702 [(set GPRC:$dst, (atomic_load_sub_32 xoaddr:$ptr, GPRC:$incr))]>;
703 def ATOMIC_LOAD_AND_I32 : Pseudo<
704 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_AND_I32",
705 [(set GPRC:$dst, (atomic_load_and_32 xoaddr:$ptr, GPRC:$incr))]>;
706 def ATOMIC_LOAD_OR_I32 : Pseudo<
707 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_OR_I32",
708 [(set GPRC:$dst, (atomic_load_or_32 xoaddr:$ptr, GPRC:$incr))]>;
709 def ATOMIC_LOAD_XOR_I32 : Pseudo<
710 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_XOR_I32",
711 [(set GPRC:$dst, (atomic_load_xor_32 xoaddr:$ptr, GPRC:$incr))]>;
712 def ATOMIC_LOAD_NAND_I32 : Pseudo<
713 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_NAND_I32",
714 [(set GPRC:$dst, (atomic_load_nand_32 xoaddr:$ptr, GPRC:$incr))]>;
716 def ATOMIC_CMP_SWAP_I8 : Pseudo<
717 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "#ATOMIC_CMP_SWAP_I8",
719 (atomic_cmp_swap_8 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
720 def ATOMIC_CMP_SWAP_I16 : Pseudo<
721 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new",
723 (atomic_cmp_swap_16 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
724 def ATOMIC_CMP_SWAP_I32 : Pseudo<
725 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new",
727 (atomic_cmp_swap_32 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
729 def ATOMIC_SWAP_I8 : Pseudo<
730 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "#ATOMIC_SWAP_i8",
731 [(set GPRC:$dst, (atomic_swap_8 xoaddr:$ptr, GPRC:$new))]>;
732 def ATOMIC_SWAP_I16 : Pseudo<
733 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "#ATOMIC_SWAP_I16",
734 [(set GPRC:$dst, (atomic_swap_16 xoaddr:$ptr, GPRC:$new))]>;
735 def ATOMIC_SWAP_I32 : Pseudo<
736 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "#ATOMIC_SWAP_I32",
737 [(set GPRC:$dst, (atomic_swap_32 xoaddr:$ptr, GPRC:$new))]>;
741 // Instructions to support atomic operations
742 def LWARX : XForm_1<31, 20, (outs GPRC:$rD), (ins memrr:$src),
743 "lwarx $rD, $src", LdStLWARX,
744 [(set GPRC:$rD, (PPClarx xoaddr:$src))]>;
747 def STWCX : XForm_1<31, 150, (outs), (ins GPRC:$rS, memrr:$dst),
748 "stwcx. $rS, $dst", LdStSTWCX,
749 [(PPCstcx GPRC:$rS, xoaddr:$dst)]>,
752 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
753 def TRAP : XForm_24<31, 4, (outs), (ins), "trap", LdStLoad, [(trap)]>;
755 //===----------------------------------------------------------------------===//
756 // PPC32 Load Instructions.
759 // Unindexed (r+i) Loads.
760 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
761 def LBZ : DForm_1<34, (outs GPRC:$rD), (ins memri:$src),
762 "lbz $rD, $src", LdStLoad,
763 [(set GPRC:$rD, (zextloadi8 iaddr:$src))]>;
764 def LHA : DForm_1<42, (outs GPRC:$rD), (ins memri:$src),
765 "lha $rD, $src", LdStLHA,
766 [(set GPRC:$rD, (sextloadi16 iaddr:$src))]>,
767 PPC970_DGroup_Cracked;
768 def LHZ : DForm_1<40, (outs GPRC:$rD), (ins memri:$src),
769 "lhz $rD, $src", LdStLoad,
770 [(set GPRC:$rD, (zextloadi16 iaddr:$src))]>;
771 def LWZ : DForm_1<32, (outs GPRC:$rD), (ins memri:$src),
772 "lwz $rD, $src", LdStLoad,
773 [(set GPRC:$rD, (load iaddr:$src))]>;
775 def LFS : DForm_1<48, (outs F4RC:$rD), (ins memri:$src),
776 "lfs $rD, $src", LdStLFD,
777 [(set F4RC:$rD, (load iaddr:$src))]>;
778 def LFD : DForm_1<50, (outs F8RC:$rD), (ins memri:$src),
779 "lfd $rD, $src", LdStLFD,
780 [(set F8RC:$rD, (load iaddr:$src))]>;
783 // Unindexed (r+i) Loads with Update (preinc).
785 def LBZU : DForm_1<35, (outs GPRC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
786 "lbzu $rD, $addr", LdStLoadUpd,
787 []>, RegConstraint<"$addr.reg = $ea_result">,
788 NoEncode<"$ea_result">;
790 def LHAU : DForm_1<43, (outs GPRC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
791 "lhau $rD, $addr", LdStLHAU,
792 []>, RegConstraint<"$addr.reg = $ea_result">,
793 NoEncode<"$ea_result">;
795 def LHZU : DForm_1<41, (outs GPRC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
796 "lhzu $rD, $addr", LdStLoadUpd,
797 []>, RegConstraint<"$addr.reg = $ea_result">,
798 NoEncode<"$ea_result">;
800 def LWZU : DForm_1<33, (outs GPRC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
801 "lwzu $rD, $addr", LdStLoadUpd,
802 []>, RegConstraint<"$addr.reg = $ea_result">,
803 NoEncode<"$ea_result">;
805 def LFSU : DForm_1<49, (outs F4RC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
806 "lfsu $rD, $addr", LdStLFDU,
807 []>, RegConstraint<"$addr.reg = $ea_result">,
808 NoEncode<"$ea_result">;
810 def LFDU : DForm_1<51, (outs F8RC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
811 "lfdu $rD, $addr", LdStLFDU,
812 []>, RegConstraint<"$addr.reg = $ea_result">,
813 NoEncode<"$ea_result">;
816 // Indexed (r+r) Loads with Update (preinc).
817 def LBZUX : XForm_1<31, 119, (outs GPRC:$rD, ptr_rc_nor0:$ea_result),
819 "lbzux $rD, $addr", LdStLoadUpd,
820 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
821 NoEncode<"$ea_result">;
823 def LHAUX : XForm_1<31, 375, (outs GPRC:$rD, ptr_rc_nor0:$ea_result),
825 "lhaux $rD, $addr", LdStLHAU,
826 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
827 NoEncode<"$ea_result">;
829 def LHZUX : XForm_1<31, 311, (outs GPRC:$rD, ptr_rc_nor0:$ea_result),
831 "lhzux $rD, $addr", LdStLoadUpd,
832 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
833 NoEncode<"$ea_result">;
835 def LWZUX : XForm_1<31, 55, (outs GPRC:$rD, ptr_rc_nor0:$ea_result),
837 "lwzux $rD, $addr", LdStLoadUpd,
838 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
839 NoEncode<"$ea_result">;
841 def LFSUX : XForm_1<31, 567, (outs F4RC:$rD, ptr_rc_nor0:$ea_result),
843 "lfsux $rD, $addr", LdStLFDU,
844 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
845 NoEncode<"$ea_result">;
847 def LFDUX : XForm_1<31, 631, (outs F8RC:$rD, ptr_rc_nor0:$ea_result),
849 "lfdux $rD, $addr", LdStLFDU,
850 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
851 NoEncode<"$ea_result">;
855 // Indexed (r+r) Loads.
857 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
858 def LBZX : XForm_1<31, 87, (outs GPRC:$rD), (ins memrr:$src),
859 "lbzx $rD, $src", LdStLoad,
860 [(set GPRC:$rD, (zextloadi8 xaddr:$src))]>;
861 def LHAX : XForm_1<31, 343, (outs GPRC:$rD), (ins memrr:$src),
862 "lhax $rD, $src", LdStLHA,
863 [(set GPRC:$rD, (sextloadi16 xaddr:$src))]>,
864 PPC970_DGroup_Cracked;
865 def LHZX : XForm_1<31, 279, (outs GPRC:$rD), (ins memrr:$src),
866 "lhzx $rD, $src", LdStLoad,
867 [(set GPRC:$rD, (zextloadi16 xaddr:$src))]>;
868 def LWZX : XForm_1<31, 23, (outs GPRC:$rD), (ins memrr:$src),
869 "lwzx $rD, $src", LdStLoad,
870 [(set GPRC:$rD, (load xaddr:$src))]>;
873 def LHBRX : XForm_1<31, 790, (outs GPRC:$rD), (ins memrr:$src),
874 "lhbrx $rD, $src", LdStLoad,
875 [(set GPRC:$rD, (PPClbrx xoaddr:$src, i16))]>;
876 def LWBRX : XForm_1<31, 534, (outs GPRC:$rD), (ins memrr:$src),
877 "lwbrx $rD, $src", LdStLoad,
878 [(set GPRC:$rD, (PPClbrx xoaddr:$src, i32))]>;
880 def LFSX : XForm_25<31, 535, (outs F4RC:$frD), (ins memrr:$src),
881 "lfsx $frD, $src", LdStLFD,
882 [(set F4RC:$frD, (load xaddr:$src))]>;
883 def LFDX : XForm_25<31, 599, (outs F8RC:$frD), (ins memrr:$src),
884 "lfdx $frD, $src", LdStLFD,
885 [(set F8RC:$frD, (load xaddr:$src))]>;
888 //===----------------------------------------------------------------------===//
889 // PPC32 Store Instructions.
892 // Unindexed (r+i) Stores.
893 let PPC970_Unit = 2 in {
894 def STB : DForm_1<38, (outs), (ins GPRC:$rS, memri:$src),
895 "stb $rS, $src", LdStStore,
896 [(truncstorei8 GPRC:$rS, iaddr:$src)]>;
897 def STH : DForm_1<44, (outs), (ins GPRC:$rS, memri:$src),
898 "sth $rS, $src", LdStStore,
899 [(truncstorei16 GPRC:$rS, iaddr:$src)]>;
900 def STW : DForm_1<36, (outs), (ins GPRC:$rS, memri:$src),
901 "stw $rS, $src", LdStStore,
902 [(store GPRC:$rS, iaddr:$src)]>;
903 def STFS : DForm_1<52, (outs), (ins F4RC:$rS, memri:$dst),
904 "stfs $rS, $dst", LdStSTFD,
905 [(store F4RC:$rS, iaddr:$dst)]>;
906 def STFD : DForm_1<54, (outs), (ins F8RC:$rS, memri:$dst),
907 "stfd $rS, $dst", LdStSTFD,
908 [(store F8RC:$rS, iaddr:$dst)]>;
911 // Unindexed (r+i) Stores with Update (preinc).
912 let PPC970_Unit = 2, mayStore = 1 in {
913 def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memri:$dst),
914 "stbu $rS, $dst", LdStStoreUpd, []>,
915 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
916 def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memri:$dst),
917 "sthu $rS, $dst", LdStStoreUpd, []>,
918 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
919 def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memri:$dst),
920 "stwu $rS, $dst", LdStStoreUpd, []>,
921 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
922 def STFSU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins F4RC:$rS, memri:$dst),
923 "stfsu $rS, $dst", LdStSTFDU, []>,
924 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
925 def STFDU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins F8RC:$rS, memri:$dst),
926 "stfdu $rS, $dst", LdStSTFDU, []>,
927 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
930 // Patterns to match the pre-inc stores. We can't put the patterns on
931 // the instruction definitions directly as ISel wants the address base
932 // and offset to be separate operands, not a single complex operand.
933 def : Pat<(pre_truncsti8 GPRC:$rS, ptr_rc_nor0:$ptrreg, iaddroff:$ptroff),
934 (STBU GPRC:$rS, iaddroff:$ptroff, ptr_rc_nor0:$ptrreg)>;
935 def : Pat<(pre_truncsti16 GPRC:$rS, ptr_rc_nor0:$ptrreg, iaddroff:$ptroff),
936 (STHU GPRC:$rS, iaddroff:$ptroff, ptr_rc_nor0:$ptrreg)>;
937 def : Pat<(pre_store GPRC:$rS, ptr_rc_nor0:$ptrreg, iaddroff:$ptroff),
938 (STWU GPRC:$rS, iaddroff:$ptroff, ptr_rc_nor0:$ptrreg)>;
939 def : Pat<(pre_store F4RC:$rS, ptr_rc_nor0:$ptrreg, iaddroff:$ptroff),
940 (STFSU F4RC:$rS, iaddroff:$ptroff, ptr_rc_nor0:$ptrreg)>;
941 def : Pat<(pre_store F8RC:$rS, ptr_rc_nor0:$ptrreg, iaddroff:$ptroff),
942 (STFDU F8RC:$rS, iaddroff:$ptroff, ptr_rc_nor0:$ptrreg)>;
944 // Indexed (r+r) Stores.
945 let PPC970_Unit = 2 in {
946 def STBX : XForm_8<31, 215, (outs), (ins GPRC:$rS, memrr:$dst),
947 "stbx $rS, $dst", LdStStore,
948 [(truncstorei8 GPRC:$rS, xaddr:$dst)]>,
949 PPC970_DGroup_Cracked;
950 def STHX : XForm_8<31, 407, (outs), (ins GPRC:$rS, memrr:$dst),
951 "sthx $rS, $dst", LdStStore,
952 [(truncstorei16 GPRC:$rS, xaddr:$dst)]>,
953 PPC970_DGroup_Cracked;
954 def STWX : XForm_8<31, 151, (outs), (ins GPRC:$rS, memrr:$dst),
955 "stwx $rS, $dst", LdStStore,
956 [(store GPRC:$rS, xaddr:$dst)]>,
957 PPC970_DGroup_Cracked;
959 def STHBRX: XForm_8<31, 918, (outs), (ins GPRC:$rS, memrr:$dst),
960 "sthbrx $rS, $dst", LdStStore,
961 [(PPCstbrx GPRC:$rS, xoaddr:$dst, i16)]>,
962 PPC970_DGroup_Cracked;
963 def STWBRX: XForm_8<31, 662, (outs), (ins GPRC:$rS, memrr:$dst),
964 "stwbrx $rS, $dst", LdStStore,
965 [(PPCstbrx GPRC:$rS, xoaddr:$dst, i32)]>,
966 PPC970_DGroup_Cracked;
968 def STFIWX: XForm_28<31, 983, (outs), (ins F8RC:$frS, memrr:$dst),
969 "stfiwx $frS, $dst", LdStSTFD,
970 [(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>;
972 def STFSX : XForm_28<31, 663, (outs), (ins F4RC:$frS, memrr:$dst),
973 "stfsx $frS, $dst", LdStSTFD,
974 [(store F4RC:$frS, xaddr:$dst)]>;
975 def STFDX : XForm_28<31, 727, (outs), (ins F8RC:$frS, memrr:$dst),
976 "stfdx $frS, $dst", LdStSTFD,
977 [(store F8RC:$frS, xaddr:$dst)]>;
980 // Indexed (r+r) Stores with Update (preinc).
981 let PPC970_Unit = 2, mayStore = 1 in {
982 def STBUX : XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memrr:$dst),
983 "stbux $rS, $dst", LdStStoreUpd, []>,
984 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
985 PPC970_DGroup_Cracked;
986 def STHUX : XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memrr:$dst),
987 "sthux $rS, $dst", LdStStoreUpd, []>,
988 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
989 PPC970_DGroup_Cracked;
990 def STWUX : XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memrr:$dst),
991 "stwux $rS, $dst", LdStStoreUpd, []>,
992 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
993 PPC970_DGroup_Cracked;
994 def STFSUX: XForm_8<31, 695, (outs ptr_rc_nor0:$ea_res), (ins F4RC:$rS, memrr:$dst),
995 "stfsux $rS, $dst", LdStSTFDU, []>,
996 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
997 PPC970_DGroup_Cracked;
998 def STFDUX: XForm_8<31, 759, (outs ptr_rc_nor0:$ea_res), (ins F8RC:$rS, memrr:$dst),
999 "stfdux $rS, $dst", LdStSTFDU, []>,
1000 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1001 PPC970_DGroup_Cracked;
1004 // Patterns to match the pre-inc stores. We can't put the patterns on
1005 // the instruction definitions directly as ISel wants the address base
1006 // and offset to be separate operands, not a single complex operand.
1007 def : Pat<(pre_truncsti8 GPRC:$rS, ptr_rc_nor0:$ptrreg, ptr_rc:$ptroff),
1008 (STBUX GPRC:$rS, ptr_rc_nor0:$ptrreg, ptr_rc:$ptroff)>;
1009 def : Pat<(pre_truncsti16 GPRC:$rS, ptr_rc_nor0:$ptrreg, ptr_rc:$ptroff),
1010 (STHUX GPRC:$rS, ptr_rc_nor0:$ptrreg, ptr_rc:$ptroff)>;
1011 def : Pat<(pre_store GPRC:$rS, ptr_rc_nor0:$ptrreg, ptr_rc:$ptroff),
1012 (STWUX GPRC:$rS, ptr_rc_nor0:$ptrreg, ptr_rc:$ptroff)>;
1013 def : Pat<(pre_store F4RC:$rS, ptr_rc_nor0:$ptrreg, ptr_rc:$ptroff),
1014 (STFSUX F4RC:$rS, ptr_rc_nor0:$ptrreg, ptr_rc:$ptroff)>;
1015 def : Pat<(pre_store F8RC:$rS, ptr_rc_nor0:$ptrreg, ptr_rc:$ptroff),
1016 (STFDUX F8RC:$rS, ptr_rc_nor0:$ptrreg, ptr_rc:$ptroff)>;
1018 def SYNC : XForm_24_sync<31, 598, (outs), (ins),
1022 //===----------------------------------------------------------------------===//
1023 // PPC32 Arithmetic Instructions.
1026 let PPC970_Unit = 1 in { // FXU Operations.
1027 def ADDI : DForm_2<14, (outs GPRC:$rD), (ins GPRC_NOR0:$rA, s16imm:$imm),
1028 "addi $rD, $rA, $imm", IntSimple,
1029 [(set GPRC:$rD, (add GPRC_NOR0:$rA, immSExt16:$imm))]>;
1030 def ADDIL : DForm_2<14, (outs GPRC:$rD), (ins GPRC_NOR0:$rA, symbolLo:$imm),
1031 "addi $rD, $rA, $imm", IntSimple,
1032 [(set GPRC:$rD, (add GPRC_NOR0:$rA, immSExt16:$imm))]>;
1033 let Defs = [CARRY] in {
1034 def ADDIC : DForm_2<12, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
1035 "addic $rD, $rA, $imm", IntGeneral,
1036 [(set GPRC:$rD, (addc GPRC:$rA, immSExt16:$imm))]>,
1037 PPC970_DGroup_Cracked;
1038 def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
1039 "addic. $rD, $rA, $imm", IntGeneral,
1042 def ADDIS : DForm_2<15, (outs GPRC:$rD), (ins GPRC_NOR0:$rA, symbolHi:$imm),
1043 "addis $rD, $rA, $imm", IntSimple,
1044 [(set GPRC:$rD, (add GPRC_NOR0:$rA,
1045 imm16ShiftedSExt:$imm))]>;
1046 def LA : DForm_2<14, (outs GPRC:$rD), (ins GPRC_NOR0:$rA, symbolLo:$sym),
1047 "la $rD, $sym($rA)", IntGeneral,
1048 [(set GPRC:$rD, (add GPRC_NOR0:$rA,
1049 (PPClo tglobaladdr:$sym, 0)))]>;
1050 def MULLI : DForm_2< 7, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
1051 "mulli $rD, $rA, $imm", IntMulLI,
1052 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
1053 let Defs = [CARRY] in {
1054 def SUBFIC : DForm_2< 8, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
1055 "subfic $rD, $rA, $imm", IntGeneral,
1056 [(set GPRC:$rD, (subc immSExt16:$imm, GPRC:$rA))]>;
1059 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
1060 def LI : DForm_2_r0<14, (outs GPRC:$rD), (ins symbolLo:$imm),
1061 "li $rD, $imm", IntSimple,
1062 [(set GPRC:$rD, immSExt16:$imm)]>;
1063 def LIS : DForm_2_r0<15, (outs GPRC:$rD), (ins symbolHi:$imm),
1064 "lis $rD, $imm", IntSimple,
1065 [(set GPRC:$rD, imm16ShiftedSExt:$imm)]>;
1069 let PPC970_Unit = 1 in { // FXU Operations.
1070 def ANDIo : DForm_4<28, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1071 "andi. $dst, $src1, $src2", IntGeneral,
1072 [(set GPRC:$dst, (and GPRC:$src1, immZExt16:$src2))]>,
1074 def ANDISo : DForm_4<29, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1075 "andis. $dst, $src1, $src2", IntGeneral,
1076 [(set GPRC:$dst, (and GPRC:$src1,imm16ShiftedZExt:$src2))]>,
1078 def ORI : DForm_4<24, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1079 "ori $dst, $src1, $src2", IntSimple,
1080 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
1081 def ORIS : DForm_4<25, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1082 "oris $dst, $src1, $src2", IntSimple,
1083 [(set GPRC:$dst, (or GPRC:$src1, imm16ShiftedZExt:$src2))]>;
1084 def XORI : DForm_4<26, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1085 "xori $dst, $src1, $src2", IntSimple,
1086 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
1087 def XORIS : DForm_4<27, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1088 "xoris $dst, $src1, $src2", IntSimple,
1089 [(set GPRC:$dst, (xor GPRC:$src1,imm16ShiftedZExt:$src2))]>;
1090 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IntSimple,
1092 def CMPWI : DForm_5_ext<11, (outs CRRC:$crD), (ins GPRC:$rA, s16imm:$imm),
1093 "cmpwi $crD, $rA, $imm", IntCompare>;
1094 def CMPLWI : DForm_6_ext<10, (outs CRRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1095 "cmplwi $dst, $src1, $src2", IntCompare>;
1099 let PPC970_Unit = 1 in { // FXU Operations.
1100 def NAND : XForm_6<31, 476, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1101 "nand $rA, $rS, $rB", IntSimple,
1102 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
1103 def AND : XForm_6<31, 28, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1104 "and $rA, $rS, $rB", IntSimple,
1105 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
1106 def ANDC : XForm_6<31, 60, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1107 "andc $rA, $rS, $rB", IntSimple,
1108 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
1109 def OR : XForm_6<31, 444, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1110 "or $rA, $rS, $rB", IntSimple,
1111 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
1112 def NOR : XForm_6<31, 124, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1113 "nor $rA, $rS, $rB", IntSimple,
1114 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
1115 def ORC : XForm_6<31, 412, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1116 "orc $rA, $rS, $rB", IntSimple,
1117 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
1118 def EQV : XForm_6<31, 284, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1119 "eqv $rA, $rS, $rB", IntSimple,
1120 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
1121 def XOR : XForm_6<31, 316, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1122 "xor $rA, $rS, $rB", IntSimple,
1123 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
1124 def SLW : XForm_6<31, 24, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1125 "slw $rA, $rS, $rB", IntGeneral,
1126 [(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>;
1127 def SRW : XForm_6<31, 536, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1128 "srw $rA, $rS, $rB", IntGeneral,
1129 [(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>;
1130 let Defs = [CARRY] in {
1131 def SRAW : XForm_6<31, 792, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1132 "sraw $rA, $rS, $rB", IntShift,
1133 [(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>;
1137 let PPC970_Unit = 1 in { // FXU Operations.
1138 let Defs = [CARRY] in {
1139 def SRAWI : XForm_10<31, 824, (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH),
1140 "srawi $rA, $rS, $SH", IntShift,
1141 [(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>;
1143 def CNTLZW : XForm_11<31, 26, (outs GPRC:$rA), (ins GPRC:$rS),
1144 "cntlzw $rA, $rS", IntGeneral,
1145 [(set GPRC:$rA, (ctlz GPRC:$rS))]>;
1146 def EXTSB : XForm_11<31, 954, (outs GPRC:$rA), (ins GPRC:$rS),
1147 "extsb $rA, $rS", IntSimple,
1148 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
1149 def EXTSH : XForm_11<31, 922, (outs GPRC:$rA), (ins GPRC:$rS),
1150 "extsh $rA, $rS", IntSimple,
1151 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
1153 def CMPW : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
1154 "cmpw $crD, $rA, $rB", IntCompare>;
1155 def CMPLW : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
1156 "cmplw $crD, $rA, $rB", IntCompare>;
1158 let PPC970_Unit = 3 in { // FPU Operations.
1159 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
1160 // "fcmpo $crD, $fA, $fB", FPCompare>;
1161 def FCMPUS : XForm_17<63, 0, (outs CRRC:$crD), (ins F4RC:$fA, F4RC:$fB),
1162 "fcmpu $crD, $fA, $fB", FPCompare>;
1163 def FCMPUD : XForm_17<63, 0, (outs CRRC:$crD), (ins F8RC:$fA, F8RC:$fB),
1164 "fcmpu $crD, $fA, $fB", FPCompare>;
1166 let Uses = [RM] in {
1167 def FCTIWZ : XForm_26<63, 15, (outs F8RC:$frD), (ins F8RC:$frB),
1168 "fctiwz $frD, $frB", FPGeneral,
1169 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>;
1170 def FRSP : XForm_26<63, 12, (outs F4RC:$frD), (ins F8RC:$frB),
1171 "frsp $frD, $frB", FPGeneral,
1172 [(set F4RC:$frD, (fround F8RC:$frB))]>;
1173 def FSQRT : XForm_26<63, 22, (outs F8RC:$frD), (ins F8RC:$frB),
1174 "fsqrt $frD, $frB", FPSqrt,
1175 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>;
1176 def FSQRTS : XForm_26<59, 22, (outs F4RC:$frD), (ins F4RC:$frB),
1177 "fsqrts $frD, $frB", FPSqrt,
1178 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>;
1182 /// Note that FMR is defined as pseudo-ops on the PPC970 because they are
1183 /// often coalesced away and we don't want the dispatch group builder to think
1184 /// that they will fill slots (which could cause the load of a LSU reject to
1185 /// sneak into a d-group with a store).
1186 def FMR : XForm_26<63, 72, (outs F4RC:$frD), (ins F4RC:$frB),
1187 "fmr $frD, $frB", FPGeneral,
1188 []>, // (set F4RC:$frD, F4RC:$frB)
1191 let PPC970_Unit = 3 in { // FPU Operations.
1192 // These are artificially split into two different forms, for 4/8 byte FP.
1193 def FABSS : XForm_26<63, 264, (outs F4RC:$frD), (ins F4RC:$frB),
1194 "fabs $frD, $frB", FPGeneral,
1195 [(set F4RC:$frD, (fabs F4RC:$frB))]>;
1196 def FABSD : XForm_26<63, 264, (outs F8RC:$frD), (ins F8RC:$frB),
1197 "fabs $frD, $frB", FPGeneral,
1198 [(set F8RC:$frD, (fabs F8RC:$frB))]>;
1199 def FNABSS : XForm_26<63, 136, (outs F4RC:$frD), (ins F4RC:$frB),
1200 "fnabs $frD, $frB", FPGeneral,
1201 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>;
1202 def FNABSD : XForm_26<63, 136, (outs F8RC:$frD), (ins F8RC:$frB),
1203 "fnabs $frD, $frB", FPGeneral,
1204 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>;
1205 def FNEGS : XForm_26<63, 40, (outs F4RC:$frD), (ins F4RC:$frB),
1206 "fneg $frD, $frB", FPGeneral,
1207 [(set F4RC:$frD, (fneg F4RC:$frB))]>;
1208 def FNEGD : XForm_26<63, 40, (outs F8RC:$frD), (ins F8RC:$frB),
1209 "fneg $frD, $frB", FPGeneral,
1210 [(set F8RC:$frD, (fneg F8RC:$frB))]>;
1214 // XL-Form instructions. condition register logical ops.
1216 def MCRF : XLForm_3<19, 0, (outs CRRC:$BF), (ins CRRC:$BFA),
1217 "mcrf $BF, $BFA", BrMCR>,
1218 PPC970_DGroup_First, PPC970_Unit_CRU;
1220 def CREQV : XLForm_1<19, 289, (outs CRBITRC:$CRD),
1221 (ins CRBITRC:$CRA, CRBITRC:$CRB),
1222 "creqv $CRD, $CRA, $CRB", BrCR,
1225 def CROR : XLForm_1<19, 449, (outs CRBITRC:$CRD),
1226 (ins CRBITRC:$CRA, CRBITRC:$CRB),
1227 "cror $CRD, $CRA, $CRB", BrCR,
1230 def CRSET : XLForm_1_ext<19, 289, (outs CRBITRC:$dst), (ins),
1231 "creqv $dst, $dst, $dst", BrCR,
1234 def CRUNSET: XLForm_1_ext<19, 193, (outs CRBITRC:$dst), (ins),
1235 "crxor $dst, $dst, $dst", BrCR,
1238 let Defs = [CR1EQ], CRD = 6 in {
1239 def CR6SET : XLForm_1_ext<19, 289, (outs), (ins),
1240 "creqv 6, 6, 6", BrCR,
1243 def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins),
1244 "crxor 6, 6, 6", BrCR,
1248 // XFX-Form instructions. Instructions that deal with SPRs.
1250 let Uses = [CTR] in {
1251 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs GPRC:$rT), (ins),
1252 "mfctr $rT", SprMFSPR>,
1253 PPC970_DGroup_First, PPC970_Unit_FXU;
1255 let Defs = [CTR], Pattern = [(PPCmtctr GPRC:$rS)] in {
1256 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins GPRC:$rS),
1257 "mtctr $rS", SprMTSPR>,
1258 PPC970_DGroup_First, PPC970_Unit_FXU;
1261 let Defs = [LR] in {
1262 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins GPRC:$rS),
1263 "mtlr $rS", SprMTSPR>,
1264 PPC970_DGroup_First, PPC970_Unit_FXU;
1266 let Uses = [LR] in {
1267 def MFLR : XFXForm_1_ext<31, 339, 8, (outs GPRC:$rT), (ins),
1268 "mflr $rT", SprMFSPR>,
1269 PPC970_DGroup_First, PPC970_Unit_FXU;
1272 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like
1273 // a GPR on the PPC970. As such, copies in and out have the same performance
1274 // characteristics as an OR instruction.
1275 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins GPRC:$rS),
1276 "mtspr 256, $rS", IntGeneral>,
1277 PPC970_DGroup_Single, PPC970_Unit_FXU;
1278 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs GPRC:$rT), (ins),
1279 "mfspr $rT, 256", IntGeneral>,
1280 PPC970_DGroup_First, PPC970_Unit_FXU;
1282 let isCodeGenOnly = 1 in {
1283 def MTVRSAVEv : XFXForm_7_ext<31, 467, 256,
1284 (outs VRSAVERC:$reg), (ins GPRC:$rS),
1285 "mtspr 256, $rS", IntGeneral>,
1286 PPC970_DGroup_Single, PPC970_Unit_FXU;
1287 def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs GPRC:$rT),
1288 (ins VRSAVERC:$reg),
1289 "mfspr $rT, 256", IntGeneral>,
1290 PPC970_DGroup_First, PPC970_Unit_FXU;
1293 // SPILL_VRSAVE - Indicate that we're dumping the VRSAVE register,
1294 // so we'll need to scavenge a register for it.
1296 def SPILL_VRSAVE : Pseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F),
1297 "#SPILL_VRSAVE", []>;
1299 // RESTORE_VRSAVE - Indicate that we're restoring the VRSAVE register (previously
1300 // spilled), so we'll need to scavenge a register for it.
1302 def RESTORE_VRSAVE : Pseudo<(outs VRSAVERC:$vrsave), (ins memri:$F),
1303 "#RESTORE_VRSAVE", []>;
1305 def MTCRF : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins GPRC:$rS),
1306 "mtcrf $FXM, $rS", BrMCRX>,
1307 PPC970_MicroCode, PPC970_Unit_CRU;
1309 // This is a pseudo for MFCR, which implicitly uses all 8 of its subregisters;
1310 // declaring that here gives the local register allocator problems with this:
1312 // MFCR <kill of whatever preg got assigned to vreg>
1313 // while not declaring it breaks DeadMachineInstructionElimination.
1314 // As it turns out, in all cases where we currently use this,
1315 // we're only interested in one subregister of it. Represent this in the
1316 // instruction to keep the register allocator from becoming confused.
1318 // FIXME: Make this a real Pseudo instruction when the JIT switches to MC.
1319 def MFCRpseud: XFXForm_3<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM),
1320 "#MFCRpseud", SprMFCR>,
1321 PPC970_MicroCode, PPC970_Unit_CRU;
1323 def MFCR : XFXForm_3<31, 19, (outs GPRC:$rT), (ins),
1324 "mfcr $rT", SprMFCR>,
1325 PPC970_MicroCode, PPC970_Unit_CRU;
1327 def MFOCRF: XFXForm_5a<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM),
1328 "mfocrf $rT, $FXM", SprMFCR>,
1329 PPC970_DGroup_First, PPC970_Unit_CRU;
1331 // Instructions to manipulate FPSCR. Only long double handling uses these.
1332 // FPSCR is not modelled; we use the SDNode Flag to keep things in order.
1334 let Uses = [RM], Defs = [RM] in {
1335 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
1336 "mtfsb0 $FM", IntMTFSB0,
1337 [(PPCmtfsb0 (i32 imm:$FM))]>,
1338 PPC970_DGroup_Single, PPC970_Unit_FPU;
1339 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
1340 "mtfsb1 $FM", IntMTFSB0,
1341 [(PPCmtfsb1 (i32 imm:$FM))]>,
1342 PPC970_DGroup_Single, PPC970_Unit_FPU;
1343 // MTFSF does not actually produce an FP result. We pretend it copies
1344 // input reg B to the output. If we didn't do this it would look like the
1345 // instruction had no outputs (because we aren't modelling the FPSCR) and
1346 // it would be deleted.
1347 def MTFSF : XFLForm<63, 711, (outs F8RC:$FRA),
1348 (ins i32imm:$FM, F8RC:$rT, F8RC:$FRB),
1349 "mtfsf $FM, $rT", "$FRB = $FRA", IntMTFSB0,
1350 [(set F8RC:$FRA, (PPCmtfsf (i32 imm:$FM),
1351 F8RC:$rT, F8RC:$FRB))]>,
1352 PPC970_DGroup_Single, PPC970_Unit_FPU;
1354 let Uses = [RM] in {
1355 def MFFS : XForm_42<63, 583, (outs F8RC:$rT), (ins),
1356 "mffs $rT", IntMFFS,
1357 [(set F8RC:$rT, (PPCmffs))]>,
1358 PPC970_DGroup_Single, PPC970_Unit_FPU;
1359 def FADDrtz: AForm_2<63, 21,
1360 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1361 "fadd $FRT, $FRA, $FRB", FPAddSub,
1362 [(set F8RC:$FRT, (PPCfaddrtz F8RC:$FRA, F8RC:$FRB))]>,
1363 PPC970_DGroup_Single, PPC970_Unit_FPU;
1367 let PPC970_Unit = 1 in { // FXU Operations.
1369 // XO-Form instructions. Arithmetic instructions that can set overflow bit
1371 def ADD4 : XOForm_1<31, 266, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1372 "add $rT, $rA, $rB", IntSimple,
1373 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
1374 let Defs = [CARRY] in {
1375 def ADDC : XOForm_1<31, 10, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1376 "addc $rT, $rA, $rB", IntGeneral,
1377 [(set GPRC:$rT, (addc GPRC:$rA, GPRC:$rB))]>,
1378 PPC970_DGroup_Cracked;
1380 def DIVW : XOForm_1<31, 491, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1381 "divw $rT, $rA, $rB", IntDivW,
1382 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>,
1383 PPC970_DGroup_First, PPC970_DGroup_Cracked;
1384 def DIVWU : XOForm_1<31, 459, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1385 "divwu $rT, $rA, $rB", IntDivW,
1386 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>,
1387 PPC970_DGroup_First, PPC970_DGroup_Cracked;
1388 def MULHW : XOForm_1<31, 75, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1389 "mulhw $rT, $rA, $rB", IntMulHW,
1390 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
1391 def MULHWU : XOForm_1<31, 11, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1392 "mulhwu $rT, $rA, $rB", IntMulHWU,
1393 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
1394 def MULLW : XOForm_1<31, 235, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1395 "mullw $rT, $rA, $rB", IntMulHW,
1396 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
1397 def SUBF : XOForm_1<31, 40, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1398 "subf $rT, $rA, $rB", IntGeneral,
1399 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
1400 let Defs = [CARRY] in {
1401 def SUBFC : XOForm_1<31, 8, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1402 "subfc $rT, $rA, $rB", IntGeneral,
1403 [(set GPRC:$rT, (subc GPRC:$rB, GPRC:$rA))]>,
1404 PPC970_DGroup_Cracked;
1406 def NEG : XOForm_3<31, 104, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1407 "neg $rT, $rA", IntSimple,
1408 [(set GPRC:$rT, (ineg GPRC:$rA))]>;
1409 let Uses = [CARRY], Defs = [CARRY] in {
1410 def ADDE : XOForm_1<31, 138, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1411 "adde $rT, $rA, $rB", IntGeneral,
1412 [(set GPRC:$rT, (adde GPRC:$rA, GPRC:$rB))]>;
1413 def ADDME : XOForm_3<31, 234, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1414 "addme $rT, $rA", IntGeneral,
1415 [(set GPRC:$rT, (adde GPRC:$rA, -1))]>;
1416 def ADDZE : XOForm_3<31, 202, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1417 "addze $rT, $rA", IntGeneral,
1418 [(set GPRC:$rT, (adde GPRC:$rA, 0))]>;
1419 def SUBFE : XOForm_1<31, 136, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1420 "subfe $rT, $rA, $rB", IntGeneral,
1421 [(set GPRC:$rT, (sube GPRC:$rB, GPRC:$rA))]>;
1422 def SUBFME : XOForm_3<31, 232, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1423 "subfme $rT, $rA", IntGeneral,
1424 [(set GPRC:$rT, (sube -1, GPRC:$rA))]>;
1425 def SUBFZE : XOForm_3<31, 200, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1426 "subfze $rT, $rA", IntGeneral,
1427 [(set GPRC:$rT, (sube 0, GPRC:$rA))]>;
1431 // A-Form instructions. Most of the instructions executed in the FPU are of
1434 let PPC970_Unit = 3 in { // FPU Operations.
1435 let Uses = [RM] in {
1436 def FMADD : AForm_1<63, 29,
1437 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1438 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused,
1440 (fma F8RC:$FRA, F8RC:$FRC, F8RC:$FRB))]>;
1441 def FMADDS : AForm_1<59, 29,
1442 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1443 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
1445 (fma F4RC:$FRA, F4RC:$FRC, F4RC:$FRB))]>;
1446 def FMSUB : AForm_1<63, 28,
1447 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1448 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused,
1450 (fma F8RC:$FRA, F8RC:$FRC, (fneg F8RC:$FRB)))]>;
1451 def FMSUBS : AForm_1<59, 28,
1452 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1453 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
1455 (fma F4RC:$FRA, F4RC:$FRC, (fneg F4RC:$FRB)))]>;
1456 def FNMADD : AForm_1<63, 31,
1457 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1458 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused,
1460 (fneg (fma F8RC:$FRA, F8RC:$FRC, F8RC:$FRB)))]>;
1461 def FNMADDS : AForm_1<59, 31,
1462 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1463 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
1465 (fneg (fma F4RC:$FRA, F4RC:$FRC, F4RC:$FRB)))]>;
1466 def FNMSUB : AForm_1<63, 30,
1467 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1468 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused,
1469 [(set F8RC:$FRT, (fneg (fma F8RC:$FRA, F8RC:$FRC,
1470 (fneg F8RC:$FRB))))]>;
1471 def FNMSUBS : AForm_1<59, 30,
1472 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1473 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
1474 [(set F4RC:$FRT, (fneg (fma F4RC:$FRA, F4RC:$FRC,
1475 (fneg F4RC:$FRB))))]>;
1477 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
1478 // having 4 of these, force the comparison to always be an 8-byte double (code
1479 // should use an FMRSD if the input comparison value really wants to be a float)
1480 // and 4/8 byte forms for the result and operand type..
1481 def FSELD : AForm_1<63, 23,
1482 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1483 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
1484 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>;
1485 def FSELS : AForm_1<63, 23,
1486 (outs F4RC:$FRT), (ins F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1487 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
1488 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>;
1489 let Uses = [RM] in {
1490 def FADD : AForm_2<63, 21,
1491 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1492 "fadd $FRT, $FRA, $FRB", FPAddSub,
1493 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>;
1494 def FADDS : AForm_2<59, 21,
1495 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1496 "fadds $FRT, $FRA, $FRB", FPGeneral,
1497 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>;
1498 def FDIV : AForm_2<63, 18,
1499 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1500 "fdiv $FRT, $FRA, $FRB", FPDivD,
1501 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>;
1502 def FDIVS : AForm_2<59, 18,
1503 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1504 "fdivs $FRT, $FRA, $FRB", FPDivS,
1505 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>;
1506 def FMUL : AForm_3<63, 25,
1507 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC),
1508 "fmul $FRT, $FRA, $FRC", FPFused,
1509 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRC))]>;
1510 def FMULS : AForm_3<59, 25,
1511 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC),
1512 "fmuls $FRT, $FRA, $FRC", FPGeneral,
1513 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRC))]>;
1514 def FSUB : AForm_2<63, 20,
1515 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1516 "fsub $FRT, $FRA, $FRB", FPAddSub,
1517 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>;
1518 def FSUBS : AForm_2<59, 20,
1519 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1520 "fsubs $FRT, $FRA, $FRB", FPGeneral,
1521 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>;
1525 let PPC970_Unit = 1 in { // FXU Operations.
1526 def ISEL : AForm_4<31, 15,
1527 (outs GPRC:$rT), (ins GPRC_NOR0:$rA, GPRC:$rB, pred:$cond),
1528 "isel $rT, $rA, $rB, $cond", IntGeneral,
1532 let PPC970_Unit = 1 in { // FXU Operations.
1533 // M-Form instructions. rotate and mask instructions.
1535 let isCommutable = 1 in {
1536 // RLWIMI can be commuted if the rotate amount is zero.
1537 def RLWIMI : MForm_2<20,
1538 (outs GPRC:$rA), (ins GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
1539 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate,
1540 []>, PPC970_DGroup_Cracked, RegConstraint<"$rSi = $rA">,
1543 def RLWINM : MForm_2<21,
1544 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1545 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
1547 def RLWINMo : MForm_2<21,
1548 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1549 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
1550 []>, isDOT, PPC970_DGroup_Cracked;
1551 def RLWNM : MForm_2<23,
1552 (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
1553 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral,
1558 //===----------------------------------------------------------------------===//
1559 // PowerPC Instruction Patterns
1562 // Arbitrary immediate support. Implement in terms of LIS/ORI.
1563 def : Pat<(i32 imm:$imm),
1564 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
1566 // Implement the 'not' operation with the NOR instruction.
1567 def NOT : Pat<(not GPRC:$in),
1568 (NOR GPRC:$in, GPRC:$in)>;
1570 // ADD an arbitrary immediate.
1571 def : Pat<(add GPRC:$in, imm:$imm),
1572 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
1573 // OR an arbitrary immediate.
1574 def : Pat<(or GPRC:$in, imm:$imm),
1575 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1576 // XOR an arbitrary immediate.
1577 def : Pat<(xor GPRC:$in, imm:$imm),
1578 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1580 def : Pat<(sub immSExt16:$imm, GPRC:$in),
1581 (SUBFIC GPRC:$in, imm:$imm)>;
1584 def : Pat<(shl GPRC:$in, (i32 imm:$imm)),
1585 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>;
1586 def : Pat<(srl GPRC:$in, (i32 imm:$imm)),
1587 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>;
1590 def : Pat<(rotl GPRC:$in, GPRC:$sh),
1591 (RLWNM GPRC:$in, GPRC:$sh, 0, 31)>;
1592 def : Pat<(rotl GPRC:$in, (i32 imm:$imm)),
1593 (RLWINM GPRC:$in, imm:$imm, 0, 31)>;
1596 def : Pat<(and (rotl GPRC:$in, GPRC:$sh), maskimm32:$imm),
1597 (RLWNM GPRC:$in, GPRC:$sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
1600 def : Pat<(PPCcall_Darwin (i32 tglobaladdr:$dst)),
1601 (BL_Darwin tglobaladdr:$dst)>;
1602 def : Pat<(PPCcall_Darwin (i32 texternalsym:$dst)),
1603 (BL_Darwin texternalsym:$dst)>;
1604 def : Pat<(PPCcall_SVR4 (i32 tglobaladdr:$dst)),
1605 (BL_SVR4 tglobaladdr:$dst)>;
1606 def : Pat<(PPCcall_SVR4 (i32 texternalsym:$dst)),
1607 (BL_SVR4 texternalsym:$dst)>;
1610 def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm),
1611 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
1613 def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
1614 (TCRETURNdi texternalsym:$dst, imm:$imm)>;
1616 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
1617 (TCRETURNri CTRRC:$dst, imm:$imm)>;
1621 // Hi and Lo for Darwin Global Addresses.
1622 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
1623 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
1624 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
1625 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
1626 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
1627 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
1628 def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>;
1629 def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>;
1630 def : Pat<(PPChi tglobaltlsaddr:$g, GPRC:$in),
1631 (ADDIS GPRC:$in, tglobaltlsaddr:$g)>;
1632 def : Pat<(PPClo tglobaltlsaddr:$g, GPRC:$in),
1633 (ADDIL GPRC:$in, tglobaltlsaddr:$g)>;
1634 def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)),
1635 (ADDIS GPRC:$in, tglobaladdr:$g)>;
1636 def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)),
1637 (ADDIS GPRC:$in, tconstpool:$g)>;
1638 def : Pat<(add GPRC:$in, (PPChi tjumptable:$g, 0)),
1639 (ADDIS GPRC:$in, tjumptable:$g)>;
1640 def : Pat<(add GPRC:$in, (PPChi tblockaddress:$g, 0)),
1641 (ADDIS GPRC:$in, tblockaddress:$g)>;
1643 // Standard shifts. These are represented separately from the real shifts above
1644 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
1646 def : Pat<(sra GPRC:$rS, GPRC:$rB),
1647 (SRAW GPRC:$rS, GPRC:$rB)>;
1648 def : Pat<(srl GPRC:$rS, GPRC:$rB),
1649 (SRW GPRC:$rS, GPRC:$rB)>;
1650 def : Pat<(shl GPRC:$rS, GPRC:$rB),
1651 (SLW GPRC:$rS, GPRC:$rB)>;
1653 def : Pat<(zextloadi1 iaddr:$src),
1655 def : Pat<(zextloadi1 xaddr:$src),
1657 def : Pat<(extloadi1 iaddr:$src),
1659 def : Pat<(extloadi1 xaddr:$src),
1661 def : Pat<(extloadi8 iaddr:$src),
1663 def : Pat<(extloadi8 xaddr:$src),
1665 def : Pat<(extloadi16 iaddr:$src),
1667 def : Pat<(extloadi16 xaddr:$src),
1669 def : Pat<(f64 (extloadf32 iaddr:$src)),
1670 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
1671 def : Pat<(f64 (extloadf32 xaddr:$src)),
1672 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
1674 def : Pat<(f64 (fextend F4RC:$src)),
1675 (COPY_TO_REGCLASS F4RC:$src, F8RC)>;
1678 def : Pat<(membarrier (i32 imm /*ll*/),
1682 (i32 imm /*device*/)),
1685 def : Pat<(atomic_fence (imm), (imm)), (SYNC)>;
1687 include "PPCInstrAltivec.td"
1688 include "PPCInstr64Bit.td"