1 //===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPCShiftOp : SDTypeProfile<1, 2, [ // PPCshl, PPCsra, PPCsrl
24 SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32>
26 def SDT_PPCCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
28 def SDT_PPCvperm : SDTypeProfile<1, 3, [
29 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
32 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
33 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
36 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
37 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
40 def SDT_PPClbrx : SDTypeProfile<1, 3, [
41 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
43 def SDT_PPCstbrx : SDTypeProfile<0, 4, [
44 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
47 //===----------------------------------------------------------------------===//
48 // PowerPC specific DAG Nodes.
51 def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>;
52 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
53 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
54 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx, [SDNPHasChain]>;
56 def PPCfsel : SDNode<"PPCISD::FSEL",
57 // Type constraint for fsel.
58 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
59 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
61 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
62 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
63 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
64 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
66 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
68 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
69 // amounts. These nodes are generated by the multi-precision shift code.
70 def PPCsrl : SDNode<"PPCISD::SRL" , SDT_PPCShiftOp>;
71 def PPCsra : SDNode<"PPCISD::SRA" , SDT_PPCShiftOp>;
72 def PPCshl : SDNode<"PPCISD::SHL" , SDT_PPCShiftOp>;
74 def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>;
75 def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore, [SDNPHasChain]>;
77 // These are target-independent nodes, but have target-specific formats.
78 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeq,
79 [SDNPHasChain, SDNPOutFlag]>;
80 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeq,
81 [SDNPHasChain, SDNPOutFlag]>;
83 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
84 def PPCcall_Macho : SDNode<"PPCISD::CALL", SDT_PPCCall,
85 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
86 def PPCcall_ELF : SDNode<"PPCISD::CALL", SDT_PPCCall,
87 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
88 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
89 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
90 def PPCbctrl_Macho : SDNode<"PPCISD::BCTRL_Macho", SDTRet,
91 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
93 def PPCbctrl_ELF : SDNode<"PPCISD::BCTRL_ELF", SDTRet,
94 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
96 def retflag : SDNode<"PPCISD::RET_FLAG", SDTRet,
97 [SDNPHasChain, SDNPOptInFlag]>;
99 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
100 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutFlag]>;
102 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
103 [SDNPHasChain, SDNPOptInFlag]>;
105 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx, [SDNPHasChain]>;
106 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx, [SDNPHasChain]>;
108 // Instructions to support dynamic alloca.
109 def SDTDynOp : SDTypeProfile<1, 2, []>;
110 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
112 //===----------------------------------------------------------------------===//
113 // PowerPC specific transformation functions and pattern fragments.
116 def SHL32 : SDNodeXForm<imm, [{
117 // Transformation function: 31 - imm
118 return getI32Imm(31 - N->getValue());
121 def SRL32 : SDNodeXForm<imm, [{
122 // Transformation function: 32 - imm
123 return N->getValue() ? getI32Imm(32 - N->getValue()) : getI32Imm(0);
126 def LO16 : SDNodeXForm<imm, [{
127 // Transformation function: get the low 16 bits.
128 return getI32Imm((unsigned short)N->getValue());
131 def HI16 : SDNodeXForm<imm, [{
132 // Transformation function: shift the immediate value down into the low bits.
133 return getI32Imm((unsigned)N->getValue() >> 16);
136 def HA16 : SDNodeXForm<imm, [{
137 // Transformation function: shift the immediate value down into the low bits.
138 signed int Val = N->getValue();
139 return getI32Imm((Val - (signed short)Val) >> 16);
141 def MB : SDNodeXForm<imm, [{
142 // Transformation function: get the start bit of a mask
144 (void)isRunOfOnes((unsigned)N->getValue(), mb, me);
145 return getI32Imm(mb);
148 def ME : SDNodeXForm<imm, [{
149 // Transformation function: get the end bit of a mask
151 (void)isRunOfOnes((unsigned)N->getValue(), mb, me);
152 return getI32Imm(me);
154 def maskimm32 : PatLeaf<(imm), [{
155 // maskImm predicate - True if immediate is a run of ones.
157 if (N->getValueType(0) == MVT::i32)
158 return isRunOfOnes((unsigned)N->getValue(), mb, me);
163 def immSExt16 : PatLeaf<(imm), [{
164 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
165 // field. Used by instructions like 'addi'.
166 if (N->getValueType(0) == MVT::i32)
167 return (int32_t)N->getValue() == (short)N->getValue();
169 return (int64_t)N->getValue() == (short)N->getValue();
171 def immZExt16 : PatLeaf<(imm), [{
172 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
173 // field. Used by instructions like 'ori'.
174 return (uint64_t)N->getValue() == (unsigned short)N->getValue();
177 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
178 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
179 // identical in 32-bit mode, but in 64-bit mode, they return true if the
180 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
182 def imm16ShiftedZExt : PatLeaf<(imm), [{
183 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
184 // immediate are set. Used by instructions like 'xoris'.
185 return (N->getValue() & ~uint64_t(0xFFFF0000)) == 0;
188 def imm16ShiftedSExt : PatLeaf<(imm), [{
189 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
190 // immediate are set. Used by instructions like 'addis'. Identical to
191 // imm16ShiftedZExt in 32-bit mode.
192 if (N->getValue() & 0xFFFF) return false;
193 if (N->getValueType(0) == MVT::i32)
195 // For 64-bit, make sure it is sext right.
196 return N->getValue() == (uint64_t)(int)N->getValue();
200 //===----------------------------------------------------------------------===//
201 // PowerPC Flag Definitions.
203 class isPPC64 { bit PPC64 = 1; }
205 list<Register> Defs = [CR0];
209 class RegConstraint<string C> {
210 string Constraints = C;
212 class NoEncode<string E> {
213 string DisableEncoding = E;
217 //===----------------------------------------------------------------------===//
218 // PowerPC Operand Definitions.
220 def s5imm : Operand<i32> {
221 let PrintMethod = "printS5ImmOperand";
223 def u5imm : Operand<i32> {
224 let PrintMethod = "printU5ImmOperand";
226 def u6imm : Operand<i32> {
227 let PrintMethod = "printU6ImmOperand";
229 def s16imm : Operand<i32> {
230 let PrintMethod = "printS16ImmOperand";
232 def u16imm : Operand<i32> {
233 let PrintMethod = "printU16ImmOperand";
235 def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing.
236 let PrintMethod = "printS16X4ImmOperand";
238 def target : Operand<OtherVT> {
239 let PrintMethod = "printBranchOperand";
241 def calltarget : Operand<iPTR> {
242 let PrintMethod = "printCallOperand";
244 def aaddr : Operand<iPTR> {
245 let PrintMethod = "printAbsAddrOperand";
247 def piclabel: Operand<iPTR> {
248 let PrintMethod = "printPICLabel";
250 def symbolHi: Operand<i32> {
251 let PrintMethod = "printSymbolHi";
253 def symbolLo: Operand<i32> {
254 let PrintMethod = "printSymbolLo";
256 def crbitm: Operand<i8> {
257 let PrintMethod = "printcrbitm";
260 def memri : Operand<iPTR> {
261 let PrintMethod = "printMemRegImm";
262 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg);
264 def memrr : Operand<iPTR> {
265 let PrintMethod = "printMemRegReg";
266 let MIOperandInfo = (ops ptr_rc, ptr_rc);
268 def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits.
269 let PrintMethod = "printMemRegImmShifted";
270 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg);
273 // PowerPC Predicate operand. 20 = (0<<5)|20 = always, CR0 is a dummy reg
274 // that doesn't matter.
275 def pred : PredicateOperand<(ops imm, CRRC), (ops (i32 20), CR0)> {
276 let PrintMethod = "printPredicateOperand";
279 // Define PowerPC specific addressing mode.
280 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
281 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
282 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
283 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std"
285 /// This is just the offset part of iaddr, used for preinc.
286 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
288 //===----------------------------------------------------------------------===//
289 // PowerPC Instruction Predicate Definitions.
290 def FPContractions : Predicate<"!NoExcessFPPrecision">;
293 //===----------------------------------------------------------------------===//
294 // PowerPC Instruction Definitions.
296 // Pseudo-instructions:
298 let hasCtrlDep = 1 in {
299 def ADJCALLSTACKDOWN : Pseudo<(ops u16imm:$amt),
300 "${:comment} ADJCALLSTACKDOWN",
301 [(callseq_start imm:$amt)]>, Imp<[R1],[R1]>;
302 def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt),
303 "${:comment} ADJCALLSTACKUP",
304 [(callseq_end imm:$amt)]>, Imp<[R1],[R1]>;
306 def UPDATE_VRSAVE : Pseudo<(ops GPRC:$rD, GPRC:$rS),
307 "UPDATE_VRSAVE $rD, $rS", []>;
310 def DYNALLOC : Pseudo<(ops GPRC:$result, GPRC:$negsize, memri:$fpsi),
311 "${:comment} DYNALLOC $result, $negsize, $fpsi",
313 (PPCdynalloc GPRC:$negsize, iaddr:$fpsi))]>,
316 def IMPLICIT_DEF_GPRC: Pseudo<(ops GPRC:$rD),"${:comment}IMPLICIT_DEF_GPRC $rD",
317 [(set GPRC:$rD, (undef))]>;
318 def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "${:comment} IMPLICIT_DEF_F8 $rD",
319 [(set F8RC:$rD, (undef))]>;
320 def IMPLICIT_DEF_F4 : Pseudo<(ops F4RC:$rD), "${:comment} IMPLICIT_DEF_F4 $rD",
321 [(set F4RC:$rD, (undef))]>;
323 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
324 // scheduler into a branch sequence.
325 let usesCustomDAGSchedInserter = 1, // Expanded by the scheduler.
326 PPC970_Single = 1 in {
327 def SELECT_CC_I4 : Pseudo<(ops GPRC:$dst, CRRC:$cond, GPRC:$T, GPRC:$F,
328 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
330 def SELECT_CC_I8 : Pseudo<(ops G8RC:$dst, CRRC:$cond, G8RC:$T, G8RC:$F,
331 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
333 def SELECT_CC_F4 : Pseudo<(ops F4RC:$dst, CRRC:$cond, F4RC:$T, F4RC:$F,
334 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
336 def SELECT_CC_F8 : Pseudo<(ops F8RC:$dst, CRRC:$cond, F8RC:$T, F8RC:$F,
337 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
339 def SELECT_CC_VRRC: Pseudo<(ops VRRC:$dst, CRRC:$cond, VRRC:$T, VRRC:$F,
340 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
344 let isTerminator = 1, isBarrier = 1, noResults = 1, PPC970_Unit = 7 in {
346 def BLR : XLForm_2_br<19, 16, 0, (ops pred:$p),
347 "b${p:cc}lr ${p:reg}", BrB,
349 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr", BrB, []>;
355 def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label", []>,
358 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1,
359 noResults = 1, PPC970_Unit = 7 in {
360 let isBarrier = 1 in {
361 def B : IForm<18, 0, 0, (ops target:$dst),
366 // BCC represents an arbitrary conditional branch on a predicate.
367 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
368 // a two-value operand where a dag node expects two operands. :(
369 def BCC : BForm<16, 0, 0, (ops pred:$cond, target:$dst),
370 "b${cond:cc} ${cond:reg}, $dst"
371 /*[(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]*/>;
375 let isCall = 1, noResults = 1, PPC970_Unit = 7,
376 // All calls clobber the non-callee saved registers...
377 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
378 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
379 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
381 CR0,CR1,CR5,CR6,CR7] in {
382 // Convenient aliases for call instructions
383 def BL_Macho : IForm<18, 0, 1,
384 (ops calltarget:$func, variable_ops),
385 "bl $func", BrB, []>; // See Pat patterns below.
386 def BLA_Macho : IForm<18, 1, 1,
387 (ops aaddr:$func, variable_ops),
388 "bla $func", BrB, [(PPCcall_Macho (i32 imm:$func))]>;
389 def BCTRL_Macho : XLForm_2_ext<19, 528, 20, 0, 1,
396 let isCall = 1, noResults = 1, PPC970_Unit = 7,
397 // All calls clobber the non-callee saved registers...
398 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
399 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,
400 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
402 CR0,CR1,CR5,CR6,CR7] in {
403 // Convenient aliases for call instructions
404 def BL_ELF : IForm<18, 0, 1,
405 (ops calltarget:$func, variable_ops),
406 "bl $func", BrB, []>; // See Pat patterns below.
407 def BLA_ELF : IForm<18, 1, 1,
408 (ops aaddr:$func, variable_ops),
410 [(PPCcall_ELF (i32 imm:$func))]>;
411 def BCTRL_ELF : XLForm_2_ext<19, 528, 20, 0, 1,
417 // DCB* instructions.
418 def DCBA : DCB_Form<758, 0, (ops memrr:$dst),
419 "dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
420 PPC970_DGroup_Single;
421 def DCBF : DCB_Form<86, 0, (ops memrr:$dst),
422 "dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
423 PPC970_DGroup_Single;
424 def DCBI : DCB_Form<470, 0, (ops memrr:$dst),
425 "dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
426 PPC970_DGroup_Single;
427 def DCBST : DCB_Form<54, 0, (ops memrr:$dst),
428 "dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
429 PPC970_DGroup_Single;
430 def DCBT : DCB_Form<278, 0, (ops memrr:$dst),
431 "dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
432 PPC970_DGroup_Single;
433 def DCBTST : DCB_Form<246, 0, (ops memrr:$dst),
434 "dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
435 PPC970_DGroup_Single;
436 def DCBZ : DCB_Form<1014, 0, (ops memrr:$dst),
437 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
438 PPC970_DGroup_Single;
439 def DCBZL : DCB_Form<1014, 1, (ops memrr:$dst),
440 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
441 PPC970_DGroup_Single;
443 //===----------------------------------------------------------------------===//
444 // PPC32 Load Instructions.
447 // Unindexed (r+i) Loads.
448 let isLoad = 1, PPC970_Unit = 2 in {
449 def LBZ : DForm_1<34, (ops GPRC:$rD, memri:$src),
450 "lbz $rD, $src", LdStGeneral,
451 [(set GPRC:$rD, (zextloadi8 iaddr:$src))]>;
452 def LHA : DForm_1<42, (ops GPRC:$rD, memri:$src),
453 "lha $rD, $src", LdStLHA,
454 [(set GPRC:$rD, (sextloadi16 iaddr:$src))]>,
455 PPC970_DGroup_Cracked;
456 def LHZ : DForm_1<40, (ops GPRC:$rD, memri:$src),
457 "lhz $rD, $src", LdStGeneral,
458 [(set GPRC:$rD, (zextloadi16 iaddr:$src))]>;
459 def LWZ : DForm_1<32, (ops GPRC:$rD, memri:$src),
460 "lwz $rD, $src", LdStGeneral,
461 [(set GPRC:$rD, (load iaddr:$src))]>;
463 def LFS : DForm_1<48, (ops F4RC:$rD, memri:$src),
464 "lfs $rD, $src", LdStLFDU,
465 [(set F4RC:$rD, (load iaddr:$src))]>;
466 def LFD : DForm_1<50, (ops F8RC:$rD, memri:$src),
467 "lfd $rD, $src", LdStLFD,
468 [(set F8RC:$rD, (load iaddr:$src))]>;
471 // Unindexed (r+i) Loads with Update (preinc).
472 def LBZU : DForm_1<35, (ops GPRC:$rD, ptr_rc:$ea_result, memri:$addr),
473 "lbzu $rD, $addr", LdStGeneral,
474 []>, RegConstraint<"$addr.reg = $ea_result">,
475 NoEncode<"$ea_result">;
477 def LHAU : DForm_1<43, (ops GPRC:$rD, ptr_rc:$ea_result, memri:$addr),
478 "lhau $rD, $addr", LdStGeneral,
479 []>, RegConstraint<"$addr.reg = $ea_result">,
480 NoEncode<"$ea_result">;
482 def LHZU : DForm_1<41, (ops GPRC:$rD, ptr_rc:$ea_result, memri:$addr),
483 "lhzu $rD, $addr", LdStGeneral,
484 []>, RegConstraint<"$addr.reg = $ea_result">,
485 NoEncode<"$ea_result">;
487 def LWZU : DForm_1<33, (ops GPRC:$rD, ptr_rc:$ea_result, memri:$addr),
488 "lwzu $rD, $addr", LdStGeneral,
489 []>, RegConstraint<"$addr.reg = $ea_result">,
490 NoEncode<"$ea_result">;
492 def LFSU : DForm_1<49, (ops F4RC:$rD, ptr_rc:$ea_result, memri:$addr),
493 "lfs $rD, $addr", LdStLFDU,
494 []>, RegConstraint<"$addr.reg = $ea_result">,
495 NoEncode<"$ea_result">;
497 def LFDU : DForm_1<51, (ops F8RC:$rD, ptr_rc:$ea_result, memri:$addr),
498 "lfd $rD, $addr", LdStLFD,
499 []>, RegConstraint<"$addr.reg = $ea_result">,
500 NoEncode<"$ea_result">;
503 // Indexed (r+r) Loads.
505 let isLoad = 1, PPC970_Unit = 2 in {
506 def LBZX : XForm_1<31, 87, (ops GPRC:$rD, memrr:$src),
507 "lbzx $rD, $src", LdStGeneral,
508 [(set GPRC:$rD, (zextloadi8 xaddr:$src))]>;
509 def LHAX : XForm_1<31, 343, (ops GPRC:$rD, memrr:$src),
510 "lhax $rD, $src", LdStLHA,
511 [(set GPRC:$rD, (sextloadi16 xaddr:$src))]>,
512 PPC970_DGroup_Cracked;
513 def LHZX : XForm_1<31, 279, (ops GPRC:$rD, memrr:$src),
514 "lhzx $rD, $src", LdStGeneral,
515 [(set GPRC:$rD, (zextloadi16 xaddr:$src))]>;
516 def LWZX : XForm_1<31, 23, (ops GPRC:$rD, memrr:$src),
517 "lwzx $rD, $src", LdStGeneral,
518 [(set GPRC:$rD, (load xaddr:$src))]>;
521 def LHBRX : XForm_1<31, 790, (ops GPRC:$rD, memrr:$src),
522 "lhbrx $rD, $src", LdStGeneral,
523 [(set GPRC:$rD, (PPClbrx xoaddr:$src, srcvalue:$sv, i16))]>;
524 def LWBRX : XForm_1<31, 534, (ops GPRC:$rD, memrr:$src),
525 "lwbrx $rD, $src", LdStGeneral,
526 [(set GPRC:$rD, (PPClbrx xoaddr:$src, srcvalue:$sv, i32))]>;
528 def LFSX : XForm_25<31, 535, (ops F4RC:$frD, memrr:$src),
529 "lfsx $frD, $src", LdStLFDU,
530 [(set F4RC:$frD, (load xaddr:$src))]>;
531 def LFDX : XForm_25<31, 599, (ops F8RC:$frD, memrr:$src),
532 "lfdx $frD, $src", LdStLFDU,
533 [(set F8RC:$frD, (load xaddr:$src))]>;
536 //===----------------------------------------------------------------------===//
537 // PPC32 Store Instructions.
540 // Unindexed (r+i) Stores.
541 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
542 def STB : DForm_1<38, (ops GPRC:$rS, memri:$src),
543 "stb $rS, $src", LdStGeneral,
544 [(truncstorei8 GPRC:$rS, iaddr:$src)]>;
545 def STH : DForm_1<44, (ops GPRC:$rS, memri:$src),
546 "sth $rS, $src", LdStGeneral,
547 [(truncstorei16 GPRC:$rS, iaddr:$src)]>;
548 def STW : DForm_1<36, (ops GPRC:$rS, memri:$src),
549 "stw $rS, $src", LdStGeneral,
550 [(store GPRC:$rS, iaddr:$src)]>;
551 def STFS : DForm_1<52, (ops F4RC:$rS, memri:$dst),
552 "stfs $rS, $dst", LdStUX,
553 [(store F4RC:$rS, iaddr:$dst)]>;
554 def STFD : DForm_1<54, (ops F8RC:$rS, memri:$dst),
555 "stfd $rS, $dst", LdStUX,
556 [(store F8RC:$rS, iaddr:$dst)]>;
559 // Unindexed (r+i) Stores with Update (preinc).
560 let isStore = 1, PPC970_Unit = 2 in {
561 def STBU : DForm_1<39, (ops ptr_rc:$ea_res, GPRC:$rS,
562 symbolLo:$ptroff, ptr_rc:$ptrreg),
563 "stbu $rS, $ptroff($ptrreg)", LdStGeneral,
564 [(set ptr_rc:$ea_res,
565 (pre_truncsti8 GPRC:$rS, ptr_rc:$ptrreg,
566 iaddroff:$ptroff))]>,
567 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
568 def STHU : DForm_1<45, (ops ptr_rc:$ea_res, GPRC:$rS,
569 symbolLo:$ptroff, ptr_rc:$ptrreg),
570 "sthu $rS, $ptroff($ptrreg)", LdStGeneral,
571 [(set ptr_rc:$ea_res,
572 (pre_truncsti16 GPRC:$rS, ptr_rc:$ptrreg,
573 iaddroff:$ptroff))]>,
574 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
575 def STWU : DForm_1<37, (ops ptr_rc:$ea_res, GPRC:$rS,
576 symbolLo:$ptroff, ptr_rc:$ptrreg),
577 "stwu $rS, $ptroff($ptrreg)", LdStGeneral,
578 [(set ptr_rc:$ea_res, (pre_store GPRC:$rS, ptr_rc:$ptrreg,
579 iaddroff:$ptroff))]>,
580 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
581 def STFSU : DForm_1<37, (ops ptr_rc:$ea_res, F4RC:$rS,
582 symbolLo:$ptroff, ptr_rc:$ptrreg),
583 "stfsu $rS, $ptroff($ptrreg)", LdStGeneral,
584 [(set ptr_rc:$ea_res, (pre_store F4RC:$rS, ptr_rc:$ptrreg,
585 iaddroff:$ptroff))]>,
586 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
587 def STFDU : DForm_1<37, (ops ptr_rc:$ea_res, F8RC:$rS,
588 symbolLo:$ptroff, ptr_rc:$ptrreg),
589 "stfdu $rS, $ptroff($ptrreg)", LdStGeneral,
590 [(set ptr_rc:$ea_res, (pre_store F8RC:$rS, ptr_rc:$ptrreg,
591 iaddroff:$ptroff))]>,
592 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
596 // Indexed (r+r) Stores.
598 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
599 def STBX : XForm_8<31, 215, (ops GPRC:$rS, memrr:$dst),
600 "stbx $rS, $dst", LdStGeneral,
601 [(truncstorei8 GPRC:$rS, xaddr:$dst)]>,
602 PPC970_DGroup_Cracked;
603 def STHX : XForm_8<31, 407, (ops GPRC:$rS, memrr:$dst),
604 "sthx $rS, $dst", LdStGeneral,
605 [(truncstorei16 GPRC:$rS, xaddr:$dst)]>,
606 PPC970_DGroup_Cracked;
607 def STWX : XForm_8<31, 151, (ops GPRC:$rS, memrr:$dst),
608 "stwx $rS, $dst", LdStGeneral,
609 [(store GPRC:$rS, xaddr:$dst)]>,
610 PPC970_DGroup_Cracked;
611 def STWUX : XForm_8<31, 183, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
612 "stwux $rS, $rA, $rB", LdStGeneral,
614 def STHBRX: XForm_8<31, 918, (ops GPRC:$rS, memrr:$dst),
615 "sthbrx $rS, $dst", LdStGeneral,
616 [(PPCstbrx GPRC:$rS, xoaddr:$dst, srcvalue:$dummy, i16)]>,
617 PPC970_DGroup_Cracked;
618 def STWBRX: XForm_8<31, 662, (ops GPRC:$rS, memrr:$dst),
619 "stwbrx $rS, $dst", LdStGeneral,
620 [(PPCstbrx GPRC:$rS, xoaddr:$dst, srcvalue:$dummy, i32)]>,
621 PPC970_DGroup_Cracked;
623 def STFIWX: XForm_28<31, 983, (ops F8RC:$frS, memrr:$dst),
624 "stfiwx $frS, $dst", LdStUX,
625 [(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>;
626 def STFSX : XForm_28<31, 663, (ops F4RC:$frS, memrr:$dst),
627 "stfsx $frS, $dst", LdStUX,
628 [(store F4RC:$frS, xaddr:$dst)]>;
629 def STFDX : XForm_28<31, 727, (ops F8RC:$frS, memrr:$dst),
630 "stfdx $frS, $dst", LdStUX,
631 [(store F8RC:$frS, xaddr:$dst)]>;
635 //===----------------------------------------------------------------------===//
636 // PPC32 Arithmetic Instructions.
639 let PPC970_Unit = 1 in { // FXU Operations.
640 def ADDI : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
641 "addi $rD, $rA, $imm", IntGeneral,
642 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
643 def ADDIC : DForm_2<12, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
644 "addic $rD, $rA, $imm", IntGeneral,
645 [(set GPRC:$rD, (addc GPRC:$rA, immSExt16:$imm))]>,
646 PPC970_DGroup_Cracked;
647 def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
648 "addic. $rD, $rA, $imm", IntGeneral,
650 def ADDIS : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$imm),
651 "addis $rD, $rA, $imm", IntGeneral,
652 [(set GPRC:$rD, (add GPRC:$rA, imm16ShiftedSExt:$imm))]>;
653 def LA : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym),
654 "la $rD, $sym($rA)", IntGeneral,
655 [(set GPRC:$rD, (add GPRC:$rA,
656 (PPClo tglobaladdr:$sym, 0)))]>;
657 def MULLI : DForm_2< 7, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
658 "mulli $rD, $rA, $imm", IntMulLI,
659 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
660 def SUBFIC : DForm_2< 8, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
661 "subfic $rD, $rA, $imm", IntGeneral,
662 [(set GPRC:$rD, (subc immSExt16:$imm, GPRC:$rA))]>;
663 def LI : DForm_2_r0<14, (ops GPRC:$rD, symbolLo:$imm),
664 "li $rD, $imm", IntGeneral,
665 [(set GPRC:$rD, immSExt16:$imm)]>;
666 def LIS : DForm_2_r0<15, (ops GPRC:$rD, symbolHi:$imm),
667 "lis $rD, $imm", IntGeneral,
668 [(set GPRC:$rD, imm16ShiftedSExt:$imm)]>;
671 let PPC970_Unit = 1 in { // FXU Operations.
672 def ANDIo : DForm_4<28, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
673 "andi. $dst, $src1, $src2", IntGeneral,
674 [(set GPRC:$dst, (and GPRC:$src1, immZExt16:$src2))]>,
676 def ANDISo : DForm_4<29, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
677 "andis. $dst, $src1, $src2", IntGeneral,
678 [(set GPRC:$dst, (and GPRC:$src1,imm16ShiftedZExt:$src2))]>,
680 def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
681 "ori $dst, $src1, $src2", IntGeneral,
682 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
683 def ORIS : DForm_4<25, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
684 "oris $dst, $src1, $src2", IntGeneral,
685 [(set GPRC:$dst, (or GPRC:$src1, imm16ShiftedZExt:$src2))]>;
686 def XORI : DForm_4<26, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
687 "xori $dst, $src1, $src2", IntGeneral,
688 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
689 def XORIS : DForm_4<27, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
690 "xoris $dst, $src1, $src2", IntGeneral,
691 [(set GPRC:$dst, (xor GPRC:$src1,imm16ShiftedZExt:$src2))]>;
692 def NOP : DForm_4_zero<24, (ops), "nop", IntGeneral,
694 def CMPWI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
695 "cmpwi $crD, $rA, $imm", IntCompare>;
696 def CMPLWI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
697 "cmplwi $dst, $src1, $src2", IntCompare>;
701 let PPC970_Unit = 1 in { // FXU Operations.
702 def NAND : XForm_6<31, 476, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
703 "nand $rA, $rS, $rB", IntGeneral,
704 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
705 def AND : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
706 "and $rA, $rS, $rB", IntGeneral,
707 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
708 def ANDC : XForm_6<31, 60, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
709 "andc $rA, $rS, $rB", IntGeneral,
710 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
711 def OR : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
712 "or $rA, $rS, $rB", IntGeneral,
713 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
714 def NOR : XForm_6<31, 124, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
715 "nor $rA, $rS, $rB", IntGeneral,
716 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
717 def ORC : XForm_6<31, 412, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
718 "orc $rA, $rS, $rB", IntGeneral,
719 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
720 def EQV : XForm_6<31, 284, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
721 "eqv $rA, $rS, $rB", IntGeneral,
722 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
723 def XOR : XForm_6<31, 316, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
724 "xor $rA, $rS, $rB", IntGeneral,
725 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
726 def SLW : XForm_6<31, 24, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
727 "slw $rA, $rS, $rB", IntGeneral,
728 [(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>;
729 def SRW : XForm_6<31, 536, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
730 "srw $rA, $rS, $rB", IntGeneral,
731 [(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>;
732 def SRAW : XForm_6<31, 792, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
733 "sraw $rA, $rS, $rB", IntShift,
734 [(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>;
737 let PPC970_Unit = 1 in { // FXU Operations.
738 def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
739 "srawi $rA, $rS, $SH", IntShift,
740 [(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>;
741 def CNTLZW : XForm_11<31, 26, (ops GPRC:$rA, GPRC:$rS),
742 "cntlzw $rA, $rS", IntGeneral,
743 [(set GPRC:$rA, (ctlz GPRC:$rS))]>;
744 def EXTSB : XForm_11<31, 954, (ops GPRC:$rA, GPRC:$rS),
745 "extsb $rA, $rS", IntGeneral,
746 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
747 def EXTSH : XForm_11<31, 922, (ops GPRC:$rA, GPRC:$rS),
748 "extsh $rA, $rS", IntGeneral,
749 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
751 def CMPW : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
752 "cmpw $crD, $rA, $rB", IntCompare>;
753 def CMPLW : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
754 "cmplw $crD, $rA, $rB", IntCompare>;
756 let PPC970_Unit = 3 in { // FPU Operations.
757 //def FCMPO : XForm_17<63, 32, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
758 // "fcmpo $crD, $fA, $fB", FPCompare>;
759 def FCMPUS : XForm_17<63, 0, (ops CRRC:$crD, F4RC:$fA, F4RC:$fB),
760 "fcmpu $crD, $fA, $fB", FPCompare>;
761 def FCMPUD : XForm_17<63, 0, (ops CRRC:$crD, F8RC:$fA, F8RC:$fB),
762 "fcmpu $crD, $fA, $fB", FPCompare>;
764 def FCTIWZ : XForm_26<63, 15, (ops F8RC:$frD, F8RC:$frB),
765 "fctiwz $frD, $frB", FPGeneral,
766 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>;
767 def FRSP : XForm_26<63, 12, (ops F4RC:$frD, F8RC:$frB),
768 "frsp $frD, $frB", FPGeneral,
769 [(set F4RC:$frD, (fround F8RC:$frB))]>;
770 def FSQRT : XForm_26<63, 22, (ops F8RC:$frD, F8RC:$frB),
771 "fsqrt $frD, $frB", FPSqrt,
772 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>;
773 def FSQRTS : XForm_26<59, 22, (ops F4RC:$frD, F4RC:$frB),
774 "fsqrts $frD, $frB", FPSqrt,
775 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>;
778 /// FMR is split into 3 versions, one for 4/8 byte FP, and one for extending.
780 /// Note that these are defined as pseudo-ops on the PPC970 because they are
781 /// often coalesced away and we don't want the dispatch group builder to think
782 /// that they will fill slots (which could cause the load of a LSU reject to
783 /// sneak into a d-group with a store).
784 def FMRS : XForm_26<63, 72, (ops F4RC:$frD, F4RC:$frB),
785 "fmr $frD, $frB", FPGeneral,
786 []>, // (set F4RC:$frD, F4RC:$frB)
788 def FMRD : XForm_26<63, 72, (ops F8RC:$frD, F8RC:$frB),
789 "fmr $frD, $frB", FPGeneral,
790 []>, // (set F8RC:$frD, F8RC:$frB)
792 def FMRSD : XForm_26<63, 72, (ops F8RC:$frD, F4RC:$frB),
793 "fmr $frD, $frB", FPGeneral,
794 [(set F8RC:$frD, (fextend F4RC:$frB))]>,
797 let PPC970_Unit = 3 in { // FPU Operations.
798 // These are artificially split into two different forms, for 4/8 byte FP.
799 def FABSS : XForm_26<63, 264, (ops F4RC:$frD, F4RC:$frB),
800 "fabs $frD, $frB", FPGeneral,
801 [(set F4RC:$frD, (fabs F4RC:$frB))]>;
802 def FABSD : XForm_26<63, 264, (ops F8RC:$frD, F8RC:$frB),
803 "fabs $frD, $frB", FPGeneral,
804 [(set F8RC:$frD, (fabs F8RC:$frB))]>;
805 def FNABSS : XForm_26<63, 136, (ops F4RC:$frD, F4RC:$frB),
806 "fnabs $frD, $frB", FPGeneral,
807 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>;
808 def FNABSD : XForm_26<63, 136, (ops F8RC:$frD, F8RC:$frB),
809 "fnabs $frD, $frB", FPGeneral,
810 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>;
811 def FNEGS : XForm_26<63, 40, (ops F4RC:$frD, F4RC:$frB),
812 "fneg $frD, $frB", FPGeneral,
813 [(set F4RC:$frD, (fneg F4RC:$frB))]>;
814 def FNEGD : XForm_26<63, 40, (ops F8RC:$frD, F8RC:$frB),
815 "fneg $frD, $frB", FPGeneral,
816 [(set F8RC:$frD, (fneg F8RC:$frB))]>;
820 // XL-Form instructions. condition register logical ops.
822 def MCRF : XLForm_3<19, 0, (ops CRRC:$BF, CRRC:$BFA),
823 "mcrf $BF, $BFA", BrMCR>,
824 PPC970_DGroup_First, PPC970_Unit_CRU;
826 def CREQV : XLForm_1<19, 289, (ops CRRC:$CRD, CRRC:$CRA, CRRC:$CRB),
827 "creqv $CRD, $CRA, $CRB", BrCR,
830 def SETCR : XLForm_1_ext<19, 289, (ops CRRC:$dst),
831 "creqv $dst, $dst, $dst", BrCR,
834 // XFX-Form instructions. Instructions that deal with SPRs.
836 def MFCTR : XFXForm_1_ext<31, 339, 9, (ops GPRC:$rT), "mfctr $rT", SprMFSPR>,
837 PPC970_DGroup_First, PPC970_Unit_FXU;
838 let Pattern = [(PPCmtctr GPRC:$rS)] in {
839 def MTCTR : XFXForm_7_ext<31, 467, 9, (ops GPRC:$rS), "mtctr $rS", SprMTSPR>,
840 PPC970_DGroup_First, PPC970_Unit_FXU;
843 def MTLR : XFXForm_7_ext<31, 467, 8, (ops GPRC:$rS), "mtlr $rS", SprMTSPR>,
844 PPC970_DGroup_First, PPC970_Unit_FXU;
845 def MFLR : XFXForm_1_ext<31, 339, 8, (ops GPRC:$rT), "mflr $rT", SprMFSPR>,
846 PPC970_DGroup_First, PPC970_Unit_FXU;
848 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like
849 // a GPR on the PPC970. As such, copies in and out have the same performance
850 // characteristics as an OR instruction.
851 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (ops GPRC:$rS),
852 "mtspr 256, $rS", IntGeneral>,
853 PPC970_DGroup_Single, PPC970_Unit_FXU;
854 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (ops GPRC:$rT),
855 "mfspr $rT, 256", IntGeneral>,
856 PPC970_DGroup_First, PPC970_Unit_FXU;
858 def MTCRF : XFXForm_5<31, 144, (ops crbitm:$FXM, GPRC:$rS),
859 "mtcrf $FXM, $rS", BrMCRX>,
860 PPC970_MicroCode, PPC970_Unit_CRU;
861 def MFCR : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT", SprMFCR>,
862 PPC970_MicroCode, PPC970_Unit_CRU;
863 def MFOCRF: XFXForm_5a<31, 19, (ops GPRC:$rT, crbitm:$FXM),
864 "mfcr $rT, $FXM", SprMFCR>,
865 PPC970_DGroup_First, PPC970_Unit_CRU;
867 let PPC970_Unit = 1 in { // FXU Operations.
869 // XO-Form instructions. Arithmetic instructions that can set overflow bit
871 def ADD4 : XOForm_1<31, 266, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
872 "add $rT, $rA, $rB", IntGeneral,
873 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
874 def ADDC : XOForm_1<31, 10, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
875 "addc $rT, $rA, $rB", IntGeneral,
876 [(set GPRC:$rT, (addc GPRC:$rA, GPRC:$rB))]>,
877 PPC970_DGroup_Cracked;
878 def ADDE : XOForm_1<31, 138, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
879 "adde $rT, $rA, $rB", IntGeneral,
880 [(set GPRC:$rT, (adde GPRC:$rA, GPRC:$rB))]>;
881 def DIVW : XOForm_1<31, 491, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
882 "divw $rT, $rA, $rB", IntDivW,
883 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>,
884 PPC970_DGroup_First, PPC970_DGroup_Cracked;
885 def DIVWU : XOForm_1<31, 459, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
886 "divwu $rT, $rA, $rB", IntDivW,
887 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>,
888 PPC970_DGroup_First, PPC970_DGroup_Cracked;
889 def MULHW : XOForm_1<31, 75, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
890 "mulhw $rT, $rA, $rB", IntMulHW,
891 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
892 def MULHWU : XOForm_1<31, 11, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
893 "mulhwu $rT, $rA, $rB", IntMulHWU,
894 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
895 def MULLW : XOForm_1<31, 235, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
896 "mullw $rT, $rA, $rB", IntMulHW,
897 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
898 def SUBF : XOForm_1<31, 40, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
899 "subf $rT, $rA, $rB", IntGeneral,
900 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
901 def SUBFC : XOForm_1<31, 8, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
902 "subfc $rT, $rA, $rB", IntGeneral,
903 [(set GPRC:$rT, (subc GPRC:$rB, GPRC:$rA))]>,
904 PPC970_DGroup_Cracked;
905 def SUBFE : XOForm_1<31, 136, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
906 "subfe $rT, $rA, $rB", IntGeneral,
907 [(set GPRC:$rT, (sube GPRC:$rB, GPRC:$rA))]>;
908 def ADDME : XOForm_3<31, 234, 0, (ops GPRC:$rT, GPRC:$rA),
909 "addme $rT, $rA", IntGeneral,
910 [(set GPRC:$rT, (adde GPRC:$rA, immAllOnes))]>;
911 def ADDZE : XOForm_3<31, 202, 0, (ops GPRC:$rT, GPRC:$rA),
912 "addze $rT, $rA", IntGeneral,
913 [(set GPRC:$rT, (adde GPRC:$rA, 0))]>;
914 def NEG : XOForm_3<31, 104, 0, (ops GPRC:$rT, GPRC:$rA),
915 "neg $rT, $rA", IntGeneral,
916 [(set GPRC:$rT, (ineg GPRC:$rA))]>;
917 def SUBFME : XOForm_3<31, 232, 0, (ops GPRC:$rT, GPRC:$rA),
918 "subfme $rT, $rA", IntGeneral,
919 [(set GPRC:$rT, (sube immAllOnes, GPRC:$rA))]>;
920 def SUBFZE : XOForm_3<31, 200, 0, (ops GPRC:$rT, GPRC:$rA),
921 "subfze $rT, $rA", IntGeneral,
922 [(set GPRC:$rT, (sube 0, GPRC:$rA))]>;
925 // A-Form instructions. Most of the instructions executed in the FPU are of
928 let PPC970_Unit = 3 in { // FPU Operations.
929 def FMADD : AForm_1<63, 29,
930 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
931 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused,
932 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC),
934 Requires<[FPContractions]>;
935 def FMADDS : AForm_1<59, 29,
936 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
937 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
938 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
940 Requires<[FPContractions]>;
941 def FMSUB : AForm_1<63, 28,
942 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
943 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused,
944 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC),
946 Requires<[FPContractions]>;
947 def FMSUBS : AForm_1<59, 28,
948 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
949 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
950 [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC),
952 Requires<[FPContractions]>;
953 def FNMADD : AForm_1<63, 31,
954 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
955 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused,
956 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC),
958 Requires<[FPContractions]>;
959 def FNMADDS : AForm_1<59, 31,
960 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
961 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
962 [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC),
964 Requires<[FPContractions]>;
965 def FNMSUB : AForm_1<63, 30,
966 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
967 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused,
968 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC),
970 Requires<[FPContractions]>;
971 def FNMSUBS : AForm_1<59, 30,
972 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
973 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
974 [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC),
976 Requires<[FPContractions]>;
977 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
978 // having 4 of these, force the comparison to always be an 8-byte double (code
979 // should use an FMRSD if the input comparison value really wants to be a float)
980 // and 4/8 byte forms for the result and operand type..
981 def FSELD : AForm_1<63, 23,
982 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
983 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
984 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>;
985 def FSELS : AForm_1<63, 23,
986 (ops F4RC:$FRT, F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
987 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
988 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>;
989 def FADD : AForm_2<63, 21,
990 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
991 "fadd $FRT, $FRA, $FRB", FPGeneral,
992 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>;
993 def FADDS : AForm_2<59, 21,
994 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
995 "fadds $FRT, $FRA, $FRB", FPGeneral,
996 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>;
997 def FDIV : AForm_2<63, 18,
998 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
999 "fdiv $FRT, $FRA, $FRB", FPDivD,
1000 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>;
1001 def FDIVS : AForm_2<59, 18,
1002 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
1003 "fdivs $FRT, $FRA, $FRB", FPDivS,
1004 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>;
1005 def FMUL : AForm_3<63, 25,
1006 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
1007 "fmul $FRT, $FRA, $FRB", FPFused,
1008 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>;
1009 def FMULS : AForm_3<59, 25,
1010 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
1011 "fmuls $FRT, $FRA, $FRB", FPGeneral,
1012 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>;
1013 def FSUB : AForm_2<63, 20,
1014 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
1015 "fsub $FRT, $FRA, $FRB", FPGeneral,
1016 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>;
1017 def FSUBS : AForm_2<59, 20,
1018 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
1019 "fsubs $FRT, $FRA, $FRB", FPGeneral,
1020 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>;
1023 let PPC970_Unit = 1 in { // FXU Operations.
1024 // M-Form instructions. rotate and mask instructions.
1026 let isCommutable = 1 in {
1027 // RLWIMI can be commuted if the rotate amount is zero.
1028 def RLWIMI : MForm_2<20,
1029 (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
1030 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate,
1031 []>, PPC970_DGroup_Cracked, RegConstraint<"$rSi = $rA">,
1034 def RLWINM : MForm_2<21,
1035 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1036 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
1038 def RLWINMo : MForm_2<21,
1039 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1040 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
1041 []>, isDOT, PPC970_DGroup_Cracked;
1042 def RLWNM : MForm_2<23,
1043 (ops GPRC:$rA, GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
1044 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral,
1049 //===----------------------------------------------------------------------===//
1050 // DWARF Pseudo Instructions
1053 def DWARF_LOC : Pseudo<(ops i32imm:$line, i32imm:$col, i32imm:$file),
1054 "${:comment} .loc $file, $line, $col",
1055 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
1058 //===----------------------------------------------------------------------===//
1059 // PowerPC Instruction Patterns
1062 // Arbitrary immediate support. Implement in terms of LIS/ORI.
1063 def : Pat<(i32 imm:$imm),
1064 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
1066 // Implement the 'not' operation with the NOR instruction.
1067 def NOT : Pat<(not GPRC:$in),
1068 (NOR GPRC:$in, GPRC:$in)>;
1070 // ADD an arbitrary immediate.
1071 def : Pat<(add GPRC:$in, imm:$imm),
1072 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
1073 // OR an arbitrary immediate.
1074 def : Pat<(or GPRC:$in, imm:$imm),
1075 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1076 // XOR an arbitrary immediate.
1077 def : Pat<(xor GPRC:$in, imm:$imm),
1078 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1080 def : Pat<(sub immSExt16:$imm, GPRC:$in),
1081 (SUBFIC GPRC:$in, imm:$imm)>;
1083 // Return void support.
1084 def : Pat<(ret), (BLR)>;
1087 def : Pat<(shl GPRC:$in, (i32 imm:$imm)),
1088 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>;
1089 def : Pat<(srl GPRC:$in, (i32 imm:$imm)),
1090 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>;
1093 def : Pat<(rotl GPRC:$in, GPRC:$sh),
1094 (RLWNM GPRC:$in, GPRC:$sh, 0, 31)>;
1095 def : Pat<(rotl GPRC:$in, (i32 imm:$imm)),
1096 (RLWINM GPRC:$in, imm:$imm, 0, 31)>;
1099 def : Pat<(and (rotl GPRC:$in, GPRC:$sh), maskimm32:$imm),
1100 (RLWNM GPRC:$in, GPRC:$sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
1103 def : Pat<(PPCcall_Macho (i32 tglobaladdr:$dst)),
1104 (BL_Macho tglobaladdr:$dst)>;
1105 def : Pat<(PPCcall_ELF (i32 texternalsym:$dst)),
1106 (BL_ELF texternalsym:$dst)>;
1108 // Hi and Lo for Darwin Global Addresses.
1109 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
1110 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
1111 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
1112 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
1113 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
1114 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
1115 def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)),
1116 (ADDIS GPRC:$in, tglobaladdr:$g)>;
1117 def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)),
1118 (ADDIS GPRC:$in, tconstpool:$g)>;
1119 def : Pat<(add GPRC:$in, (PPChi tjumptable:$g, 0)),
1120 (ADDIS GPRC:$in, tjumptable:$g)>;
1122 // Fused negative multiply subtract, alternate pattern
1123 def : Pat<(fsub F8RC:$B, (fmul F8RC:$A, F8RC:$C)),
1124 (FNMSUB F8RC:$A, F8RC:$C, F8RC:$B)>,
1125 Requires<[FPContractions]>;
1126 def : Pat<(fsub F4RC:$B, (fmul F4RC:$A, F4RC:$C)),
1127 (FNMSUBS F4RC:$A, F4RC:$C, F4RC:$B)>,
1128 Requires<[FPContractions]>;
1130 // Standard shifts. These are represented separately from the real shifts above
1131 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
1133 def : Pat<(sra GPRC:$rS, GPRC:$rB),
1134 (SRAW GPRC:$rS, GPRC:$rB)>;
1135 def : Pat<(srl GPRC:$rS, GPRC:$rB),
1136 (SRW GPRC:$rS, GPRC:$rB)>;
1137 def : Pat<(shl GPRC:$rS, GPRC:$rB),
1138 (SLW GPRC:$rS, GPRC:$rB)>;
1140 def : Pat<(zextloadi1 iaddr:$src),
1142 def : Pat<(zextloadi1 xaddr:$src),
1144 def : Pat<(extloadi1 iaddr:$src),
1146 def : Pat<(extloadi1 xaddr:$src),
1148 def : Pat<(extloadi8 iaddr:$src),
1150 def : Pat<(extloadi8 xaddr:$src),
1152 def : Pat<(extloadi16 iaddr:$src),
1154 def : Pat<(extloadi16 xaddr:$src),
1156 def : Pat<(extloadf32 iaddr:$src),
1157 (FMRSD (LFS iaddr:$src))>;
1158 def : Pat<(extloadf32 xaddr:$src),
1159 (FMRSD (LFSX xaddr:$src))>;
1161 include "PPCInstrAltivec.td"
1162 include "PPCInstr64Bit.td"