1 //===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x
24 SDTCisVT<0, f64>, SDTCisPtrTy<1>
27 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
28 def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
30 def SDT_PPCvperm : SDTypeProfile<1, 3, [
31 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
34 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
35 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
38 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
39 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
42 def SDT_PPClbrx : SDTypeProfile<1, 2, [
43 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
45 def SDT_PPCstbrx : SDTypeProfile<0, 3, [
46 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
49 def SDT_PPClarx : SDTypeProfile<1, 1, [
50 SDTCisInt<0>, SDTCisPtrTy<1>
52 def SDT_PPCstcx : SDTypeProfile<0, 2, [
53 SDTCisInt<0>, SDTCisPtrTy<1>
56 def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
57 SDTCisPtrTy<0>, SDTCisVT<1, i32>
60 def tocentry32 : Operand<iPTR> {
61 let MIOperandInfo = (ops i32imm:$imm);
64 //===----------------------------------------------------------------------===//
65 // PowerPC specific DAG Nodes.
68 def PPCfre : SDNode<"PPCISD::FRE", SDTFPUnaryOp, []>;
69 def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>;
71 def PPCfcfid : SDNode<"PPCISD::FCFID", SDTFPUnaryOp, []>;
72 def PPCfcfidu : SDNode<"PPCISD::FCFIDU", SDTFPUnaryOp, []>;
73 def PPCfcfids : SDNode<"PPCISD::FCFIDS", SDTFPRoundOp, []>;
74 def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>;
75 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
76 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
77 def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>;
78 def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>;
79 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
80 [SDNPHasChain, SDNPMayStore]>;
81 def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx,
82 [SDNPHasChain, SDNPMayLoad]>;
83 def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx,
84 [SDNPHasChain, SDNPMayLoad]>;
86 // Extract FPSCR (not modeled at the DAG level).
87 def PPCmffs : SDNode<"PPCISD::MFFS",
88 SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, []>;
90 // Perform FADD in round-to-zero mode.
91 def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>;
94 def PPCfsel : SDNode<"PPCISD::FSEL",
95 // Type constraint for fsel.
96 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
97 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
99 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
100 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
101 def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, [SDNPMayLoad]>;
102 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
103 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
105 def PPCppc32GOT : SDNode<"PPCISD::PPC32_GOT", SDTIntLeaf, []>;
107 def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>;
108 def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp,
110 def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>;
111 def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>;
112 def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>;
113 def PPCgetTlsAddr : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>;
114 def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>;
115 def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>;
116 def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>;
117 def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp,
119 def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>;
121 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
123 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
124 // amounts. These nodes are generated by the multi-precision shift code.
125 def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>;
126 def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>;
127 def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>;
129 // These are target-independent nodes, but have target-specific formats.
130 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
131 [SDNPHasChain, SDNPOutGlue]>;
132 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd,
133 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
135 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
136 def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall,
137 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
139 def PPCcall_nop : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall,
140 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
142 def PPCload : SDNode<"PPCISD::LOAD", SDTypeProfile<1, 1, []>,
143 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
144 def PPCload_toc : SDNode<"PPCISD::LOAD_TOC", SDTypeProfile<0, 1, []>,
145 [SDNPHasChain, SDNPSideEffect,
146 SDNPInGlue, SDNPOutGlue]>;
147 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
148 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
149 def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone,
150 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
153 def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone,
154 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
156 def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
157 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
159 def PPCeh_sjlj_setjmp : SDNode<"PPCISD::EH_SJLJ_SETJMP",
160 SDTypeProfile<1, 1, [SDTCisInt<0>,
162 [SDNPHasChain, SDNPSideEffect]>;
163 def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP",
164 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
165 [SDNPHasChain, SDNPSideEffect]>;
167 def SDT_PPCsc : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
168 def PPCsc : SDNode<"PPCISD::SC", SDT_PPCsc,
169 [SDNPHasChain, SDNPSideEffect]>;
171 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
172 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>;
174 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
175 [SDNPHasChain, SDNPOptInGlue]>;
177 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
178 [SDNPHasChain, SDNPMayLoad]>;
179 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
180 [SDNPHasChain, SDNPMayStore]>;
182 // Instructions to set/unset CR bit 6 for SVR4 vararg calls
183 def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone,
184 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
185 def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone,
186 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
188 // Instructions to support atomic operations
189 def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx,
190 [SDNPHasChain, SDNPMayLoad]>;
191 def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx,
192 [SDNPHasChain, SDNPMayStore]>;
194 // Instructions to support medium and large code model
195 def PPCaddisTocHA : SDNode<"PPCISD::ADDIS_TOC_HA", SDTIntBinOp, []>;
196 def PPCldTocL : SDNode<"PPCISD::LD_TOC_L", SDTIntBinOp, [SDNPMayLoad]>;
197 def PPCaddiTocL : SDNode<"PPCISD::ADDI_TOC_L", SDTIntBinOp, []>;
200 // Instructions to support dynamic alloca.
201 def SDTDynOp : SDTypeProfile<1, 2, []>;
202 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
204 //===----------------------------------------------------------------------===//
205 // PowerPC specific transformation functions and pattern fragments.
208 def SHL32 : SDNodeXForm<imm, [{
209 // Transformation function: 31 - imm
210 return getI32Imm(31 - N->getZExtValue());
213 def SRL32 : SDNodeXForm<imm, [{
214 // Transformation function: 32 - imm
215 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0);
218 def LO16 : SDNodeXForm<imm, [{
219 // Transformation function: get the low 16 bits.
220 return getI32Imm((unsigned short)N->getZExtValue());
223 def HI16 : SDNodeXForm<imm, [{
224 // Transformation function: shift the immediate value down into the low bits.
225 return getI32Imm((unsigned)N->getZExtValue() >> 16);
228 def HA16 : SDNodeXForm<imm, [{
229 // Transformation function: shift the immediate value down into the low bits.
230 signed int Val = N->getZExtValue();
231 return getI32Imm((Val - (signed short)Val) >> 16);
233 def MB : SDNodeXForm<imm, [{
234 // Transformation function: get the start bit of a mask
236 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
237 return getI32Imm(mb);
240 def ME : SDNodeXForm<imm, [{
241 // Transformation function: get the end bit of a mask
243 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
244 return getI32Imm(me);
246 def maskimm32 : PatLeaf<(imm), [{
247 // maskImm predicate - True if immediate is a run of ones.
249 if (N->getValueType(0) == MVT::i32)
250 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
255 def imm32SExt16 : Operand<i32>, ImmLeaf<i32, [{
256 // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit
257 // sign extended field. Used by instructions like 'addi'.
258 return (int32_t)Imm == (short)Imm;
260 def imm64SExt16 : Operand<i64>, ImmLeaf<i64, [{
261 // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit
262 // sign extended field. Used by instructions like 'addi'.
263 return (int64_t)Imm == (short)Imm;
265 def immZExt16 : PatLeaf<(imm), [{
266 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
267 // field. Used by instructions like 'ori'.
268 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
271 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
272 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
273 // identical in 32-bit mode, but in 64-bit mode, they return true if the
274 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
276 def imm16ShiftedZExt : PatLeaf<(imm), [{
277 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
278 // immediate are set. Used by instructions like 'xoris'.
279 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
282 def imm16ShiftedSExt : PatLeaf<(imm), [{
283 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
284 // immediate are set. Used by instructions like 'addis'. Identical to
285 // imm16ShiftedZExt in 32-bit mode.
286 if (N->getZExtValue() & 0xFFFF) return false;
287 if (N->getValueType(0) == MVT::i32)
289 // For 64-bit, make sure it is sext right.
290 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
293 def imm64ZExt32 : Operand<i64>, ImmLeaf<i64, [{
294 // imm64ZExt32 predicate - True if the i64 immediate fits in a 32-bit
295 // zero extended field.
296 return isUInt<32>(Imm);
299 // Some r+i load/store instructions (such as LD, STD, LDU, etc.) that require
300 // restricted memrix (4-aligned) constants are alignment sensitive. If these
301 // offsets are hidden behind TOC entries than the values of the lower-order
302 // bits cannot be checked directly. As a result, we need to also incorporate
303 // an alignment check into the relevant patterns.
305 def aligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
306 return cast<LoadSDNode>(N)->getAlignment() >= 4;
308 def aligned4store : PatFrag<(ops node:$val, node:$ptr),
309 (store node:$val, node:$ptr), [{
310 return cast<StoreSDNode>(N)->getAlignment() >= 4;
312 def aligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
313 return cast<LoadSDNode>(N)->getAlignment() >= 4;
315 def aligned4pre_store : PatFrag<
316 (ops node:$val, node:$base, node:$offset),
317 (pre_store node:$val, node:$base, node:$offset), [{
318 return cast<StoreSDNode>(N)->getAlignment() >= 4;
321 def unaligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
322 return cast<LoadSDNode>(N)->getAlignment() < 4;
324 def unaligned4store : PatFrag<(ops node:$val, node:$ptr),
325 (store node:$val, node:$ptr), [{
326 return cast<StoreSDNode>(N)->getAlignment() < 4;
328 def unaligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
329 return cast<LoadSDNode>(N)->getAlignment() < 4;
332 //===----------------------------------------------------------------------===//
333 // PowerPC Flag Definitions.
335 class isPPC64 { bit PPC64 = 1; }
336 class isDOT { bit RC = 1; }
338 class RegConstraint<string C> {
339 string Constraints = C;
341 class NoEncode<string E> {
342 string DisableEncoding = E;
346 //===----------------------------------------------------------------------===//
347 // PowerPC Operand Definitions.
349 // In the default PowerPC assembler syntax, registers are specified simply
350 // by number, so they cannot be distinguished from immediate values (without
351 // looking at the opcode). This means that the default operand matching logic
352 // for the asm parser does not work, and we need to specify custom matchers.
353 // Since those can only be specified with RegisterOperand classes and not
354 // directly on the RegisterClass, all instructions patterns used by the asm
355 // parser need to use a RegisterOperand (instead of a RegisterClass) for
356 // all their register operands.
357 // For this purpose, we define one RegisterOperand for each RegisterClass,
358 // using the same name as the class, just in lower case.
360 def PPCRegGPRCAsmOperand : AsmOperandClass {
361 let Name = "RegGPRC"; let PredicateMethod = "isRegNumber";
363 def gprc : RegisterOperand<GPRC> {
364 let ParserMatchClass = PPCRegGPRCAsmOperand;
366 def PPCRegG8RCAsmOperand : AsmOperandClass {
367 let Name = "RegG8RC"; let PredicateMethod = "isRegNumber";
369 def g8rc : RegisterOperand<G8RC> {
370 let ParserMatchClass = PPCRegG8RCAsmOperand;
372 def PPCRegGPRCNoR0AsmOperand : AsmOperandClass {
373 let Name = "RegGPRCNoR0"; let PredicateMethod = "isRegNumber";
375 def gprc_nor0 : RegisterOperand<GPRC_NOR0> {
376 let ParserMatchClass = PPCRegGPRCNoR0AsmOperand;
378 def PPCRegG8RCNoX0AsmOperand : AsmOperandClass {
379 let Name = "RegG8RCNoX0"; let PredicateMethod = "isRegNumber";
381 def g8rc_nox0 : RegisterOperand<G8RC_NOX0> {
382 let ParserMatchClass = PPCRegG8RCNoX0AsmOperand;
384 def PPCRegF8RCAsmOperand : AsmOperandClass {
385 let Name = "RegF8RC"; let PredicateMethod = "isRegNumber";
387 def f8rc : RegisterOperand<F8RC> {
388 let ParserMatchClass = PPCRegF8RCAsmOperand;
390 def PPCRegF4RCAsmOperand : AsmOperandClass {
391 let Name = "RegF4RC"; let PredicateMethod = "isRegNumber";
393 def f4rc : RegisterOperand<F4RC> {
394 let ParserMatchClass = PPCRegF4RCAsmOperand;
396 def PPCRegVRRCAsmOperand : AsmOperandClass {
397 let Name = "RegVRRC"; let PredicateMethod = "isRegNumber";
399 def vrrc : RegisterOperand<VRRC> {
400 let ParserMatchClass = PPCRegVRRCAsmOperand;
402 def PPCRegCRBITRCAsmOperand : AsmOperandClass {
403 let Name = "RegCRBITRC"; let PredicateMethod = "isCRBitNumber";
405 def crbitrc : RegisterOperand<CRBITRC> {
406 let ParserMatchClass = PPCRegCRBITRCAsmOperand;
408 def PPCRegCRRCAsmOperand : AsmOperandClass {
409 let Name = "RegCRRC"; let PredicateMethod = "isCCRegNumber";
411 def crrc : RegisterOperand<CRRC> {
412 let ParserMatchClass = PPCRegCRRCAsmOperand;
415 def PPCU2ImmAsmOperand : AsmOperandClass {
416 let Name = "U2Imm"; let PredicateMethod = "isU2Imm";
417 let RenderMethod = "addImmOperands";
419 def u2imm : Operand<i32> {
420 let PrintMethod = "printU2ImmOperand";
421 let ParserMatchClass = PPCU2ImmAsmOperand;
424 def PPCU4ImmAsmOperand : AsmOperandClass {
425 let Name = "U4Imm"; let PredicateMethod = "isU4Imm";
426 let RenderMethod = "addImmOperands";
428 def u4imm : Operand<i32> {
429 let PrintMethod = "printU4ImmOperand";
430 let ParserMatchClass = PPCU4ImmAsmOperand;
432 def PPCS5ImmAsmOperand : AsmOperandClass {
433 let Name = "S5Imm"; let PredicateMethod = "isS5Imm";
434 let RenderMethod = "addImmOperands";
436 def s5imm : Operand<i32> {
437 let PrintMethod = "printS5ImmOperand";
438 let ParserMatchClass = PPCS5ImmAsmOperand;
439 let DecoderMethod = "decodeSImmOperand<5>";
441 def PPCU5ImmAsmOperand : AsmOperandClass {
442 let Name = "U5Imm"; let PredicateMethod = "isU5Imm";
443 let RenderMethod = "addImmOperands";
445 def u5imm : Operand<i32> {
446 let PrintMethod = "printU5ImmOperand";
447 let ParserMatchClass = PPCU5ImmAsmOperand;
448 let DecoderMethod = "decodeUImmOperand<5>";
450 def PPCU6ImmAsmOperand : AsmOperandClass {
451 let Name = "U6Imm"; let PredicateMethod = "isU6Imm";
452 let RenderMethod = "addImmOperands";
454 def u6imm : Operand<i32> {
455 let PrintMethod = "printU6ImmOperand";
456 let ParserMatchClass = PPCU6ImmAsmOperand;
457 let DecoderMethod = "decodeUImmOperand<6>";
459 def PPCS16ImmAsmOperand : AsmOperandClass {
460 let Name = "S16Imm"; let PredicateMethod = "isS16Imm";
461 let RenderMethod = "addImmOperands";
463 def s16imm : Operand<i32> {
464 let PrintMethod = "printS16ImmOperand";
465 let EncoderMethod = "getImm16Encoding";
466 let ParserMatchClass = PPCS16ImmAsmOperand;
467 let DecoderMethod = "decodeSImmOperand<16>";
469 def PPCU16ImmAsmOperand : AsmOperandClass {
470 let Name = "U16Imm"; let PredicateMethod = "isU16Imm";
471 let RenderMethod = "addImmOperands";
473 def u16imm : Operand<i32> {
474 let PrintMethod = "printU16ImmOperand";
475 let EncoderMethod = "getImm16Encoding";
476 let ParserMatchClass = PPCU16ImmAsmOperand;
477 let DecoderMethod = "decodeUImmOperand<16>";
479 def PPCS17ImmAsmOperand : AsmOperandClass {
480 let Name = "S17Imm"; let PredicateMethod = "isS17Imm";
481 let RenderMethod = "addImmOperands";
483 def s17imm : Operand<i32> {
484 // This operand type is used for addis/lis to allow the assembler parser
485 // to accept immediates in the range -65536..65535 for compatibility with
486 // the GNU assembler. The operand is treated as 16-bit otherwise.
487 let PrintMethod = "printS16ImmOperand";
488 let EncoderMethod = "getImm16Encoding";
489 let ParserMatchClass = PPCS17ImmAsmOperand;
490 let DecoderMethod = "decodeSImmOperand<16>";
492 def PPCDirectBrAsmOperand : AsmOperandClass {
493 let Name = "DirectBr"; let PredicateMethod = "isDirectBr";
494 let RenderMethod = "addBranchTargetOperands";
496 def directbrtarget : Operand<OtherVT> {
497 let PrintMethod = "printBranchOperand";
498 let EncoderMethod = "getDirectBrEncoding";
499 let ParserMatchClass = PPCDirectBrAsmOperand;
501 def absdirectbrtarget : Operand<OtherVT> {
502 let PrintMethod = "printAbsBranchOperand";
503 let EncoderMethod = "getAbsDirectBrEncoding";
504 let ParserMatchClass = PPCDirectBrAsmOperand;
506 def PPCCondBrAsmOperand : AsmOperandClass {
507 let Name = "CondBr"; let PredicateMethod = "isCondBr";
508 let RenderMethod = "addBranchTargetOperands";
510 def condbrtarget : Operand<OtherVT> {
511 let PrintMethod = "printBranchOperand";
512 let EncoderMethod = "getCondBrEncoding";
513 let ParserMatchClass = PPCCondBrAsmOperand;
515 def abscondbrtarget : Operand<OtherVT> {
516 let PrintMethod = "printAbsBranchOperand";
517 let EncoderMethod = "getAbsCondBrEncoding";
518 let ParserMatchClass = PPCCondBrAsmOperand;
520 def calltarget : Operand<iPTR> {
521 let PrintMethod = "printBranchOperand";
522 let EncoderMethod = "getDirectBrEncoding";
523 let ParserMatchClass = PPCDirectBrAsmOperand;
525 def abscalltarget : Operand<iPTR> {
526 let PrintMethod = "printAbsBranchOperand";
527 let EncoderMethod = "getAbsDirectBrEncoding";
528 let ParserMatchClass = PPCDirectBrAsmOperand;
530 def PPCCRBitMaskOperand : AsmOperandClass {
531 let Name = "CRBitMask"; let PredicateMethod = "isCRBitMask";
533 def crbitm: Operand<i8> {
534 let PrintMethod = "printcrbitm";
535 let EncoderMethod = "get_crbitm_encoding";
536 let DecoderMethod = "decodeCRBitMOperand";
537 let ParserMatchClass = PPCCRBitMaskOperand;
540 // A version of ptr_rc which excludes R0 (or X0 in 64-bit mode).
541 def PPCRegGxRCNoR0Operand : AsmOperandClass {
542 let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber";
544 def ptr_rc_nor0 : Operand<iPTR>, PointerLikeRegClass<1> {
545 let ParserMatchClass = PPCRegGxRCNoR0Operand;
547 // A version of ptr_rc usable with the asm parser.
548 def PPCRegGxRCOperand : AsmOperandClass {
549 let Name = "RegGxRC"; let PredicateMethod = "isRegNumber";
551 def ptr_rc_idx : Operand<iPTR>, PointerLikeRegClass<0> {
552 let ParserMatchClass = PPCRegGxRCOperand;
555 def PPCDispRIOperand : AsmOperandClass {
556 let Name = "DispRI"; let PredicateMethod = "isS16Imm";
557 let RenderMethod = "addImmOperands";
559 def dispRI : Operand<iPTR> {
560 let ParserMatchClass = PPCDispRIOperand;
562 def PPCDispRIXOperand : AsmOperandClass {
563 let Name = "DispRIX"; let PredicateMethod = "isS16ImmX4";
564 let RenderMethod = "addImmOperands";
566 def dispRIX : Operand<iPTR> {
567 let ParserMatchClass = PPCDispRIXOperand;
570 def memri : Operand<iPTR> {
571 let PrintMethod = "printMemRegImm";
572 let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg);
573 let EncoderMethod = "getMemRIEncoding";
574 let DecoderMethod = "decodeMemRIOperands";
576 def memrr : Operand<iPTR> {
577 let PrintMethod = "printMemRegReg";
578 let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc_idx:$offreg);
580 def memrix : Operand<iPTR> { // memri where the imm is 4-aligned.
581 let PrintMethod = "printMemRegImm";
582 let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg);
583 let EncoderMethod = "getMemRIXEncoding";
584 let DecoderMethod = "decodeMemRIXOperands";
587 // A single-register address. This is used with the SjLj
588 // pseudo-instructions.
589 def memr : Operand<iPTR> {
590 let MIOperandInfo = (ops ptr_rc:$ptrreg);
592 def PPCTLSRegOperand : AsmOperandClass {
593 let Name = "TLSReg"; let PredicateMethod = "isTLSReg";
594 let RenderMethod = "addTLSRegOperands";
596 def tlsreg32 : Operand<i32> {
597 let EncoderMethod = "getTLSRegEncoding";
598 let ParserMatchClass = PPCTLSRegOperand;
600 def tlsgd32 : Operand<i32> {}
601 def tlscall32 : Operand<i32> {
602 let PrintMethod = "printTLSCall";
603 let MIOperandInfo = (ops calltarget:$func, tlsgd32:$sym);
604 let EncoderMethod = "getTLSCallEncoding";
607 // PowerPC Predicate operand.
608 def pred : Operand<OtherVT> {
609 let PrintMethod = "printPredicateOperand";
610 let MIOperandInfo = (ops i32imm:$bibo, crrc:$reg);
613 // Define PowerPC specific addressing mode.
614 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
615 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
616 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
617 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmX4", [], []>; // "std"
619 // The address in a single register. This is used with the SjLj
620 // pseudo-instructions.
621 def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>;
623 /// This is just the offset part of iaddr, used for preinc.
624 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
626 //===----------------------------------------------------------------------===//
627 // PowerPC Instruction Predicate Definitions.
628 def In32BitMode : Predicate<"!PPCSubTarget->isPPC64()">;
629 def In64BitMode : Predicate<"PPCSubTarget->isPPC64()">;
630 def IsBookE : Predicate<"PPCSubTarget->isBookE()">;
631 def IsNotBookE : Predicate<"!PPCSubTarget->isBookE()">;
633 //===----------------------------------------------------------------------===//
634 // PowerPC Multiclass Definitions.
636 multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
637 string asmbase, string asmstr, InstrItinClass itin,
639 let BaseName = asmbase in {
640 def NAME : XForm_6<opcode, xo, OOL, IOL,
641 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
642 pattern>, RecFormRel;
644 def o : XForm_6<opcode, xo, OOL, IOL,
645 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
646 []>, isDOT, RecFormRel;
650 multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
651 string asmbase, string asmstr, InstrItinClass itin,
653 let BaseName = asmbase in {
654 let Defs = [CARRY] in
655 def NAME : XForm_6<opcode, xo, OOL, IOL,
656 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
657 pattern>, RecFormRel;
658 let Defs = [CARRY, CR0] in
659 def o : XForm_6<opcode, xo, OOL, IOL,
660 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
661 []>, isDOT, RecFormRel;
665 multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
666 string asmbase, string asmstr, InstrItinClass itin,
668 let BaseName = asmbase in {
669 let Defs = [CARRY] in
670 def NAME : XForm_10<opcode, xo, OOL, IOL,
671 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
672 pattern>, RecFormRel;
673 let Defs = [CARRY, CR0] in
674 def o : XForm_10<opcode, xo, OOL, IOL,
675 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
676 []>, isDOT, RecFormRel;
680 multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
681 string asmbase, string asmstr, InstrItinClass itin,
683 let BaseName = asmbase in {
684 def NAME : XForm_11<opcode, xo, OOL, IOL,
685 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
686 pattern>, RecFormRel;
688 def o : XForm_11<opcode, xo, OOL, IOL,
689 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
690 []>, isDOT, RecFormRel;
694 multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
695 string asmbase, string asmstr, InstrItinClass itin,
697 let BaseName = asmbase in {
698 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
699 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
700 pattern>, RecFormRel;
702 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
703 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
704 []>, isDOT, RecFormRel;
708 multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
709 string asmbase, string asmstr, InstrItinClass itin,
711 let BaseName = asmbase in {
712 let Defs = [CARRY] in
713 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
714 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
715 pattern>, RecFormRel;
716 let Defs = [CARRY, CR0] in
717 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
718 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
719 []>, isDOT, RecFormRel;
723 multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
724 string asmbase, string asmstr, InstrItinClass itin,
726 let BaseName = asmbase in {
727 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
728 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
729 pattern>, RecFormRel;
731 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
732 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
733 []>, isDOT, RecFormRel;
737 multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
738 string asmbase, string asmstr, InstrItinClass itin,
740 let BaseName = asmbase in {
741 let Defs = [CARRY] in
742 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
743 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
744 pattern>, RecFormRel;
745 let Defs = [CARRY, CR0] in
746 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
747 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
748 []>, isDOT, RecFormRel;
752 multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL,
753 string asmbase, string asmstr, InstrItinClass itin,
755 let BaseName = asmbase in {
756 def NAME : MForm_2<opcode, OOL, IOL,
757 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
758 pattern>, RecFormRel;
760 def o : MForm_2<opcode, OOL, IOL,
761 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
762 []>, isDOT, RecFormRel;
766 multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
767 string asmbase, string asmstr, InstrItinClass itin,
769 let BaseName = asmbase in {
770 def NAME : MDForm_1<opcode, xo, OOL, IOL,
771 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
772 pattern>, RecFormRel;
774 def o : MDForm_1<opcode, xo, OOL, IOL,
775 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
776 []>, isDOT, RecFormRel;
780 multiclass MDSForm_1r<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
781 string asmbase, string asmstr, InstrItinClass itin,
783 let BaseName = asmbase in {
784 def NAME : MDSForm_1<opcode, xo, OOL, IOL,
785 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
786 pattern>, RecFormRel;
788 def o : MDSForm_1<opcode, xo, OOL, IOL,
789 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
790 []>, isDOT, RecFormRel;
794 multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
795 string asmbase, string asmstr, InstrItinClass itin,
797 let BaseName = asmbase in {
798 let Defs = [CARRY] in
799 def NAME : XSForm_1<opcode, xo, OOL, IOL,
800 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
801 pattern>, RecFormRel;
802 let Defs = [CARRY, CR0] in
803 def o : XSForm_1<opcode, xo, OOL, IOL,
804 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
805 []>, isDOT, RecFormRel;
809 multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
810 string asmbase, string asmstr, InstrItinClass itin,
812 let BaseName = asmbase in {
813 def NAME : XForm_26<opcode, xo, OOL, IOL,
814 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
815 pattern>, RecFormRel;
817 def o : XForm_26<opcode, xo, OOL, IOL,
818 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
819 []>, isDOT, RecFormRel;
823 multiclass XForm_28r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
824 string asmbase, string asmstr, InstrItinClass itin,
826 let BaseName = asmbase in {
827 def NAME : XForm_28<opcode, xo, OOL, IOL,
828 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
829 pattern>, RecFormRel;
831 def o : XForm_28<opcode, xo, OOL, IOL,
832 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
833 []>, isDOT, RecFormRel;
837 multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
838 string asmbase, string asmstr, InstrItinClass itin,
840 let BaseName = asmbase in {
841 def NAME : AForm_1<opcode, xo, OOL, IOL,
842 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
843 pattern>, RecFormRel;
845 def o : AForm_1<opcode, xo, OOL, IOL,
846 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
847 []>, isDOT, RecFormRel;
851 multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
852 string asmbase, string asmstr, InstrItinClass itin,
854 let BaseName = asmbase in {
855 def NAME : AForm_2<opcode, xo, OOL, IOL,
856 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
857 pattern>, RecFormRel;
859 def o : AForm_2<opcode, xo, OOL, IOL,
860 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
861 []>, isDOT, RecFormRel;
865 multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
866 string asmbase, string asmstr, InstrItinClass itin,
868 let BaseName = asmbase in {
869 def NAME : AForm_3<opcode, xo, OOL, IOL,
870 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
871 pattern>, RecFormRel;
873 def o : AForm_3<opcode, xo, OOL, IOL,
874 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
875 []>, isDOT, RecFormRel;
879 //===----------------------------------------------------------------------===//
880 // PowerPC Instruction Definitions.
882 // Pseudo-instructions:
884 let hasCtrlDep = 1 in {
885 let Defs = [R1], Uses = [R1] in {
886 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt",
887 [(callseq_start timm:$amt)]>;
888 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt2",
889 [(callseq_end timm:$amt1, timm:$amt2)]>;
892 def UPDATE_VRSAVE : Pseudo<(outs gprc:$rD), (ins gprc:$rS),
893 "UPDATE_VRSAVE $rD, $rS", []>;
896 let Defs = [R1], Uses = [R1] in
897 def DYNALLOC : Pseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC",
899 (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>;
901 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
902 // instruction selection into a branch sequence.
903 let usesCustomInserter = 1, // Expanded after instruction selection.
904 PPC970_Single = 1 in {
905 // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes
906 // because either operand might become the first operand in an isel, and
907 // that operand cannot be r0.
908 def SELECT_CC_I4 : Pseudo<(outs gprc:$dst), (ins crrc:$cond,
909 gprc_nor0:$T, gprc_nor0:$F,
910 i32imm:$BROPC), "#SELECT_CC_I4",
912 def SELECT_CC_I8 : Pseudo<(outs g8rc:$dst), (ins crrc:$cond,
913 g8rc_nox0:$T, g8rc_nox0:$F,
914 i32imm:$BROPC), "#SELECT_CC_I8",
916 def SELECT_CC_F4 : Pseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F,
917 i32imm:$BROPC), "#SELECT_CC_F4",
919 def SELECT_CC_F8 : Pseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F,
920 i32imm:$BROPC), "#SELECT_CC_F8",
922 def SELECT_CC_VRRC: Pseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F,
923 i32imm:$BROPC), "#SELECT_CC_VRRC",
926 // SELECT_* pseudo instructions, like SELECT_CC_* but taking condition
927 // register bit directly.
928 def SELECT_I4 : Pseudo<(outs gprc:$dst), (ins crbitrc:$cond,
929 gprc_nor0:$T, gprc_nor0:$F), "#SELECT_I4",
930 [(set i32:$dst, (select i1:$cond, i32:$T, i32:$F))]>;
931 def SELECT_I8 : Pseudo<(outs g8rc:$dst), (ins crbitrc:$cond,
932 g8rc_nox0:$T, g8rc_nox0:$F), "#SELECT_I8",
933 [(set i64:$dst, (select i1:$cond, i64:$T, i64:$F))]>;
934 def SELECT_F4 : Pseudo<(outs f4rc:$dst), (ins crbitrc:$cond,
935 f4rc:$T, f4rc:$F), "#SELECT_F4",
936 [(set f32:$dst, (select i1:$cond, f32:$T, f32:$F))]>;
937 def SELECT_F8 : Pseudo<(outs f8rc:$dst), (ins crbitrc:$cond,
938 f8rc:$T, f8rc:$F), "#SELECT_F8",
939 [(set f64:$dst, (select i1:$cond, f64:$T, f64:$F))]>;
940 def SELECT_VRRC: Pseudo<(outs vrrc:$dst), (ins crbitrc:$cond,
941 vrrc:$T, vrrc:$F), "#SELECT_VRRC",
943 (select i1:$cond, v4i32:$T, v4i32:$F))]>;
946 // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
947 // scavenge a register for it.
948 let mayStore = 1 in {
949 def SPILL_CR : Pseudo<(outs), (ins crrc:$cond, memri:$F),
951 def SPILL_CRBIT : Pseudo<(outs), (ins crbitrc:$cond, memri:$F),
955 // RESTORE_CR - Indicate that we're restoring the CR register (previously
956 // spilled), so we'll need to scavenge a register for it.
958 def RESTORE_CR : Pseudo<(outs crrc:$cond), (ins memri:$F),
960 def RESTORE_CRBIT : Pseudo<(outs crbitrc:$cond), (ins memri:$F),
961 "#RESTORE_CRBIT", []>;
964 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
965 let isReturn = 1, Uses = [LR, RM] in
966 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB,
968 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in {
969 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
972 let isCodeGenOnly = 1 in {
973 def BCCCTR : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
974 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB,
977 def BCCTR : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi),
978 "bcctr 12, $bi, 0", IIC_BrB, []>;
979 def BCCTRn : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi),
980 "bcctr 4, $bi, 0", IIC_BrB, []>;
986 def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>,
989 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
990 let isBarrier = 1 in {
991 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst),
994 def BA : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$dst),
995 "ba $dst", IIC_BrB, []>;
998 // BCC represents an arbitrary conditional branch on a predicate.
999 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
1000 // a two-value operand where a dag node expects two operands. :(
1001 let isCodeGenOnly = 1 in {
1002 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst),
1003 "b${cond:cc}${cond:pm} ${cond:reg}, $dst"
1004 /*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$dst)]*/>;
1005 def BCCA : BForm<16, 1, 0, (outs), (ins pred:$cond, abscondbrtarget:$dst),
1006 "b${cond:cc}a${cond:pm} ${cond:reg}, $dst">;
1008 let isReturn = 1, Uses = [LR, RM] in
1009 def BCCLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$cond),
1010 "b${cond:cc}lr${cond:pm} ${cond:reg}", IIC_BrB, []>;
1013 let isCodeGenOnly = 1 in {
1014 let Pattern = [(brcond i1:$bi, bb:$dst)] in
1015 def BC : BForm_4<16, 12, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
1016 "bc 12, $bi, $dst">;
1018 let Pattern = [(brcond (not i1:$bi), bb:$dst)] in
1019 def BCn : BForm_4<16, 4, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
1022 let isReturn = 1, Uses = [LR, RM] in
1023 def BCLR : XLForm_2_br2<19, 16, 12, 0, (outs), (ins crbitrc:$bi),
1024 "bclr 12, $bi, 0", IIC_BrB, []>;
1025 def BCLRn : XLForm_2_br2<19, 16, 4, 0, (outs), (ins crbitrc:$bi),
1026 "bclr 4, $bi, 0", IIC_BrB, []>;
1029 let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in {
1030 def BDZLR : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
1031 "bdzlr", IIC_BrB, []>;
1032 def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
1033 "bdnzlr", IIC_BrB, []>;
1034 def BDZLRp : XLForm_2_ext<19, 16, 27, 0, 0, (outs), (ins),
1035 "bdzlr+", IIC_BrB, []>;
1036 def BDNZLRp: XLForm_2_ext<19, 16, 25, 0, 0, (outs), (ins),
1037 "bdnzlr+", IIC_BrB, []>;
1038 def BDZLRm : XLForm_2_ext<19, 16, 26, 0, 0, (outs), (ins),
1039 "bdzlr-", IIC_BrB, []>;
1040 def BDNZLRm: XLForm_2_ext<19, 16, 24, 0, 0, (outs), (ins),
1041 "bdnzlr-", IIC_BrB, []>;
1044 let Defs = [CTR], Uses = [CTR] in {
1045 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
1047 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
1049 def BDZA : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$dst),
1051 def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$dst),
1053 def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$dst),
1055 def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$dst),
1057 def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$dst),
1059 def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$dst),
1061 def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$dst),
1063 def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$dst),
1065 def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$dst),
1067 def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$dst),
1072 // The unconditional BCL used by the SjLj setjmp code.
1073 let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7 in {
1074 let Defs = [LR], Uses = [RM] in {
1075 def BCLalways : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst),
1076 "bcl 20, 31, $dst">;
1080 let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
1081 // Convenient aliases for call instructions
1082 let Uses = [RM] in {
1083 def BL : IForm<18, 0, 1, (outs), (ins calltarget:$func),
1084 "bl $func", IIC_BrB, []>; // See Pat patterns below.
1085 def BLA : IForm<18, 1, 1, (outs), (ins abscalltarget:$func),
1086 "bla $func", IIC_BrB, [(PPCcall (i32 imm:$func))]>;
1088 let isCodeGenOnly = 1 in {
1089 def BL_TLS : IForm<18, 0, 1, (outs), (ins tlscall32:$func),
1090 "bl $func", IIC_BrB, []>;
1091 def BCCL : BForm<16, 0, 1, (outs), (ins pred:$cond, condbrtarget:$dst),
1092 "b${cond:cc}l${cond:pm} ${cond:reg}, $dst">;
1093 def BCCLA : BForm<16, 1, 1, (outs), (ins pred:$cond, abscondbrtarget:$dst),
1094 "b${cond:cc}la${cond:pm} ${cond:reg}, $dst">;
1096 def BCL : BForm_4<16, 12, 0, 1, (outs),
1097 (ins crbitrc:$bi, condbrtarget:$dst),
1098 "bcl 12, $bi, $dst">;
1099 def BCLn : BForm_4<16, 4, 0, 1, (outs),
1100 (ins crbitrc:$bi, condbrtarget:$dst),
1101 "bcl 4, $bi, $dst">;
1104 let Uses = [CTR, RM] in {
1105 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
1106 "bctrl", IIC_BrB, [(PPCbctrl)]>,
1107 Requires<[In32BitMode]>;
1109 let isCodeGenOnly = 1 in {
1110 def BCCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
1111 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB,
1114 def BCCTRL : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi),
1115 "bcctrl 12, $bi, 0", IIC_BrB, []>;
1116 def BCCTRLn : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi),
1117 "bcctrl 4, $bi, 0", IIC_BrB, []>;
1120 let Uses = [LR, RM] in {
1121 def BLRL : XLForm_2_ext<19, 16, 20, 0, 1, (outs), (ins),
1122 "blrl", IIC_BrB, []>;
1124 let isCodeGenOnly = 1 in {
1125 def BCCLRL : XLForm_2_br<19, 16, 1, (outs), (ins pred:$cond),
1126 "b${cond:cc}lrl${cond:pm} ${cond:reg}", IIC_BrB,
1129 def BCLRL : XLForm_2_br2<19, 16, 12, 1, (outs), (ins crbitrc:$bi),
1130 "bclrl 12, $bi, 0", IIC_BrB, []>;
1131 def BCLRLn : XLForm_2_br2<19, 16, 4, 1, (outs), (ins crbitrc:$bi),
1132 "bclrl 4, $bi, 0", IIC_BrB, []>;
1135 let Defs = [CTR], Uses = [CTR, RM] in {
1136 def BDZL : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$dst),
1138 def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$dst),
1140 def BDZLA : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$dst),
1142 def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$dst),
1144 def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$dst),
1146 def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$dst),
1148 def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$dst),
1150 def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$dst),
1152 def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$dst),
1154 def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$dst),
1156 def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$dst),
1158 def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$dst),
1161 let Defs = [CTR], Uses = [CTR, LR, RM] in {
1162 def BDZLRL : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins),
1163 "bdzlrl", IIC_BrB, []>;
1164 def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins),
1165 "bdnzlrl", IIC_BrB, []>;
1166 def BDZLRLp : XLForm_2_ext<19, 16, 27, 0, 1, (outs), (ins),
1167 "bdzlrl+", IIC_BrB, []>;
1168 def BDNZLRLp: XLForm_2_ext<19, 16, 25, 0, 1, (outs), (ins),
1169 "bdnzlrl+", IIC_BrB, []>;
1170 def BDZLRLm : XLForm_2_ext<19, 16, 26, 0, 1, (outs), (ins),
1171 "bdzlrl-", IIC_BrB, []>;
1172 def BDNZLRLm: XLForm_2_ext<19, 16, 24, 0, 1, (outs), (ins),
1173 "bdnzlrl-", IIC_BrB, []>;
1177 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1178 def TCRETURNdi :Pseudo< (outs),
1179 (ins calltarget:$dst, i32imm:$offset),
1180 "#TC_RETURNd $dst $offset",
1184 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1185 def TCRETURNai :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
1186 "#TC_RETURNa $func $offset",
1187 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
1189 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1190 def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset),
1191 "#TC_RETURNr $dst $offset",
1195 let isCodeGenOnly = 1 in {
1197 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
1198 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in
1199 def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
1200 []>, Requires<[In32BitMode]>;
1202 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1203 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1204 def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
1208 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1209 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1210 def TAILBA : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst),
1216 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
1218 def EH_SjLj_SetJmp32 : Pseudo<(outs gprc:$dst), (ins memr:$buf),
1219 "#EH_SJLJ_SETJMP32",
1220 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
1221 Requires<[In32BitMode]>;
1222 let isTerminator = 1 in
1223 def EH_SjLj_LongJmp32 : Pseudo<(outs), (ins memr:$buf),
1224 "#EH_SJLJ_LONGJMP32",
1225 [(PPCeh_sjlj_longjmp addr:$buf)]>,
1226 Requires<[In32BitMode]>;
1229 let isBranch = 1, isTerminator = 1 in {
1230 def EH_SjLj_Setup : Pseudo<(outs), (ins directbrtarget:$dst),
1231 "#EH_SjLj_Setup\t$dst", []>;
1235 let PPC970_Unit = 7 in {
1236 def SC : SCForm<17, 1, (outs), (ins i32imm:$lev),
1237 "sc $lev", IIC_BrB, [(PPCsc (i32 imm:$lev))]>;
1240 // DCB* instructions.
1241 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst), "dcba $dst",
1242 IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
1243 PPC970_DGroup_Single;
1244 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst), "dcbf $dst",
1245 IIC_LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
1246 PPC970_DGroup_Single;
1247 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst), "dcbi $dst",
1248 IIC_LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
1249 PPC970_DGroup_Single;
1250 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst), "dcbst $dst",
1251 IIC_LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
1252 PPC970_DGroup_Single;
1253 def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst), "dcbt $dst",
1254 IIC_LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
1255 PPC970_DGroup_Single;
1256 def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst), "dcbtst $dst",
1257 IIC_LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
1258 PPC970_DGroup_Single;
1259 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst), "dcbz $dst",
1260 IIC_LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
1261 PPC970_DGroup_Single;
1262 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), "dcbzl $dst",
1263 IIC_LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
1264 PPC970_DGroup_Single;
1266 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
1267 (DCBT xoaddr:$dst)>;
1269 // Atomic operations
1270 let usesCustomInserter = 1 in {
1271 let Defs = [CR0] in {
1272 def ATOMIC_LOAD_ADD_I8 : Pseudo<
1273 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I8",
1274 [(set i32:$dst, (atomic_load_add_8 xoaddr:$ptr, i32:$incr))]>;
1275 def ATOMIC_LOAD_SUB_I8 : Pseudo<
1276 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I8",
1277 [(set i32:$dst, (atomic_load_sub_8 xoaddr:$ptr, i32:$incr))]>;
1278 def ATOMIC_LOAD_AND_I8 : Pseudo<
1279 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I8",
1280 [(set i32:$dst, (atomic_load_and_8 xoaddr:$ptr, i32:$incr))]>;
1281 def ATOMIC_LOAD_OR_I8 : Pseudo<
1282 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I8",
1283 [(set i32:$dst, (atomic_load_or_8 xoaddr:$ptr, i32:$incr))]>;
1284 def ATOMIC_LOAD_XOR_I8 : Pseudo<
1285 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "ATOMIC_LOAD_XOR_I8",
1286 [(set i32:$dst, (atomic_load_xor_8 xoaddr:$ptr, i32:$incr))]>;
1287 def ATOMIC_LOAD_NAND_I8 : Pseudo<
1288 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8",
1289 [(set i32:$dst, (atomic_load_nand_8 xoaddr:$ptr, i32:$incr))]>;
1290 def ATOMIC_LOAD_ADD_I16 : Pseudo<
1291 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16",
1292 [(set i32:$dst, (atomic_load_add_16 xoaddr:$ptr, i32:$incr))]>;
1293 def ATOMIC_LOAD_SUB_I16 : Pseudo<
1294 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I16",
1295 [(set i32:$dst, (atomic_load_sub_16 xoaddr:$ptr, i32:$incr))]>;
1296 def ATOMIC_LOAD_AND_I16 : Pseudo<
1297 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I16",
1298 [(set i32:$dst, (atomic_load_and_16 xoaddr:$ptr, i32:$incr))]>;
1299 def ATOMIC_LOAD_OR_I16 : Pseudo<
1300 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I16",
1301 [(set i32:$dst, (atomic_load_or_16 xoaddr:$ptr, i32:$incr))]>;
1302 def ATOMIC_LOAD_XOR_I16 : Pseudo<
1303 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I16",
1304 [(set i32:$dst, (atomic_load_xor_16 xoaddr:$ptr, i32:$incr))]>;
1305 def ATOMIC_LOAD_NAND_I16 : Pseudo<
1306 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I16",
1307 [(set i32:$dst, (atomic_load_nand_16 xoaddr:$ptr, i32:$incr))]>;
1308 def ATOMIC_LOAD_ADD_I32 : Pseudo<
1309 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I32",
1310 [(set i32:$dst, (atomic_load_add_32 xoaddr:$ptr, i32:$incr))]>;
1311 def ATOMIC_LOAD_SUB_I32 : Pseudo<
1312 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I32",
1313 [(set i32:$dst, (atomic_load_sub_32 xoaddr:$ptr, i32:$incr))]>;
1314 def ATOMIC_LOAD_AND_I32 : Pseudo<
1315 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I32",
1316 [(set i32:$dst, (atomic_load_and_32 xoaddr:$ptr, i32:$incr))]>;
1317 def ATOMIC_LOAD_OR_I32 : Pseudo<
1318 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I32",
1319 [(set i32:$dst, (atomic_load_or_32 xoaddr:$ptr, i32:$incr))]>;
1320 def ATOMIC_LOAD_XOR_I32 : Pseudo<
1321 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I32",
1322 [(set i32:$dst, (atomic_load_xor_32 xoaddr:$ptr, i32:$incr))]>;
1323 def ATOMIC_LOAD_NAND_I32 : Pseudo<
1324 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I32",
1325 [(set i32:$dst, (atomic_load_nand_32 xoaddr:$ptr, i32:$incr))]>;
1327 def ATOMIC_CMP_SWAP_I8 : Pseudo<
1328 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I8",
1329 [(set i32:$dst, (atomic_cmp_swap_8 xoaddr:$ptr, i32:$old, i32:$new))]>;
1330 def ATOMIC_CMP_SWAP_I16 : Pseudo<
1331 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new",
1332 [(set i32:$dst, (atomic_cmp_swap_16 xoaddr:$ptr, i32:$old, i32:$new))]>;
1333 def ATOMIC_CMP_SWAP_I32 : Pseudo<
1334 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new",
1335 [(set i32:$dst, (atomic_cmp_swap_32 xoaddr:$ptr, i32:$old, i32:$new))]>;
1337 def ATOMIC_SWAP_I8 : Pseudo<
1338 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_i8",
1339 [(set i32:$dst, (atomic_swap_8 xoaddr:$ptr, i32:$new))]>;
1340 def ATOMIC_SWAP_I16 : Pseudo<
1341 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I16",
1342 [(set i32:$dst, (atomic_swap_16 xoaddr:$ptr, i32:$new))]>;
1343 def ATOMIC_SWAP_I32 : Pseudo<
1344 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I32",
1345 [(set i32:$dst, (atomic_swap_32 xoaddr:$ptr, i32:$new))]>;
1349 // Instructions to support atomic operations
1350 def LWARX : XForm_1<31, 20, (outs gprc:$rD), (ins memrr:$src),
1351 "lwarx $rD, $src", IIC_LdStLWARX,
1352 [(set i32:$rD, (PPClarx xoaddr:$src))]>;
1355 def STWCX : XForm_1<31, 150, (outs), (ins gprc:$rS, memrr:$dst),
1356 "stwcx. $rS, $dst", IIC_LdStSTWCX,
1357 [(PPCstcx i32:$rS, xoaddr:$dst)]>,
1360 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
1361 def TRAP : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>;
1363 def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm),
1364 "twi $to, $rA, $imm", IIC_IntTrapW, []>;
1365 def TW : XForm_1<31, 4, (outs), (ins u5imm:$to, gprc:$rA, gprc:$rB),
1366 "tw $to, $rA, $rB", IIC_IntTrapW, []>;
1367 def TDI : DForm_base<2, (outs), (ins u5imm:$to, g8rc:$rA, s16imm:$imm),
1368 "tdi $to, $rA, $imm", IIC_IntTrapD, []>;
1369 def TD : XForm_1<31, 68, (outs), (ins u5imm:$to, g8rc:$rA, g8rc:$rB),
1370 "td $to, $rA, $rB", IIC_IntTrapD, []>;
1372 //===----------------------------------------------------------------------===//
1373 // PPC32 Load Instructions.
1376 // Unindexed (r+i) Loads.
1377 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
1378 def LBZ : DForm_1<34, (outs gprc:$rD), (ins memri:$src),
1379 "lbz $rD, $src", IIC_LdStLoad,
1380 [(set i32:$rD, (zextloadi8 iaddr:$src))]>;
1381 def LHA : DForm_1<42, (outs gprc:$rD), (ins memri:$src),
1382 "lha $rD, $src", IIC_LdStLHA,
1383 [(set i32:$rD, (sextloadi16 iaddr:$src))]>,
1384 PPC970_DGroup_Cracked;
1385 def LHZ : DForm_1<40, (outs gprc:$rD), (ins memri:$src),
1386 "lhz $rD, $src", IIC_LdStLoad,
1387 [(set i32:$rD, (zextloadi16 iaddr:$src))]>;
1388 def LWZ : DForm_1<32, (outs gprc:$rD), (ins memri:$src),
1389 "lwz $rD, $src", IIC_LdStLoad,
1390 [(set i32:$rD, (load iaddr:$src))]>;
1392 def LFS : DForm_1<48, (outs f4rc:$rD), (ins memri:$src),
1393 "lfs $rD, $src", IIC_LdStLFD,
1394 [(set f32:$rD, (load iaddr:$src))]>;
1395 def LFD : DForm_1<50, (outs f8rc:$rD), (ins memri:$src),
1396 "lfd $rD, $src", IIC_LdStLFD,
1397 [(set f64:$rD, (load iaddr:$src))]>;
1400 // Unindexed (r+i) Loads with Update (preinc).
1401 let mayLoad = 1, neverHasSideEffects = 1 in {
1402 def LBZU : DForm_1<35, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1403 "lbzu $rD, $addr", IIC_LdStLoadUpd,
1404 []>, RegConstraint<"$addr.reg = $ea_result">,
1405 NoEncode<"$ea_result">;
1407 def LHAU : DForm_1<43, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1408 "lhau $rD, $addr", IIC_LdStLHAU,
1409 []>, RegConstraint<"$addr.reg = $ea_result">,
1410 NoEncode<"$ea_result">;
1412 def LHZU : DForm_1<41, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1413 "lhzu $rD, $addr", IIC_LdStLoadUpd,
1414 []>, RegConstraint<"$addr.reg = $ea_result">,
1415 NoEncode<"$ea_result">;
1417 def LWZU : DForm_1<33, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1418 "lwzu $rD, $addr", IIC_LdStLoadUpd,
1419 []>, RegConstraint<"$addr.reg = $ea_result">,
1420 NoEncode<"$ea_result">;
1422 def LFSU : DForm_1<49, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1423 "lfsu $rD, $addr", IIC_LdStLFDU,
1424 []>, RegConstraint<"$addr.reg = $ea_result">,
1425 NoEncode<"$ea_result">;
1427 def LFDU : DForm_1<51, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1428 "lfdu $rD, $addr", IIC_LdStLFDU,
1429 []>, RegConstraint<"$addr.reg = $ea_result">,
1430 NoEncode<"$ea_result">;
1433 // Indexed (r+r) Loads with Update (preinc).
1434 def LBZUX : XForm_1<31, 119, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1436 "lbzux $rD, $addr", IIC_LdStLoadUpdX,
1437 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1438 NoEncode<"$ea_result">;
1440 def LHAUX : XForm_1<31, 375, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1442 "lhaux $rD, $addr", IIC_LdStLHAUX,
1443 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1444 NoEncode<"$ea_result">;
1446 def LHZUX : XForm_1<31, 311, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1448 "lhzux $rD, $addr", IIC_LdStLoadUpdX,
1449 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1450 NoEncode<"$ea_result">;
1452 def LWZUX : XForm_1<31, 55, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1454 "lwzux $rD, $addr", IIC_LdStLoadUpdX,
1455 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1456 NoEncode<"$ea_result">;
1458 def LFSUX : XForm_1<31, 567, (outs f4rc:$rD, ptr_rc_nor0:$ea_result),
1460 "lfsux $rD, $addr", IIC_LdStLFDUX,
1461 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1462 NoEncode<"$ea_result">;
1464 def LFDUX : XForm_1<31, 631, (outs f8rc:$rD, ptr_rc_nor0:$ea_result),
1466 "lfdux $rD, $addr", IIC_LdStLFDUX,
1467 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1468 NoEncode<"$ea_result">;
1472 // Indexed (r+r) Loads.
1474 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
1475 def LBZX : XForm_1<31, 87, (outs gprc:$rD), (ins memrr:$src),
1476 "lbzx $rD, $src", IIC_LdStLoad,
1477 [(set i32:$rD, (zextloadi8 xaddr:$src))]>;
1478 def LHAX : XForm_1<31, 343, (outs gprc:$rD), (ins memrr:$src),
1479 "lhax $rD, $src", IIC_LdStLHA,
1480 [(set i32:$rD, (sextloadi16 xaddr:$src))]>,
1481 PPC970_DGroup_Cracked;
1482 def LHZX : XForm_1<31, 279, (outs gprc:$rD), (ins memrr:$src),
1483 "lhzx $rD, $src", IIC_LdStLoad,
1484 [(set i32:$rD, (zextloadi16 xaddr:$src))]>;
1485 def LWZX : XForm_1<31, 23, (outs gprc:$rD), (ins memrr:$src),
1486 "lwzx $rD, $src", IIC_LdStLoad,
1487 [(set i32:$rD, (load xaddr:$src))]>;
1490 def LHBRX : XForm_1<31, 790, (outs gprc:$rD), (ins memrr:$src),
1491 "lhbrx $rD, $src", IIC_LdStLoad,
1492 [(set i32:$rD, (PPClbrx xoaddr:$src, i16))]>;
1493 def LWBRX : XForm_1<31, 534, (outs gprc:$rD), (ins memrr:$src),
1494 "lwbrx $rD, $src", IIC_LdStLoad,
1495 [(set i32:$rD, (PPClbrx xoaddr:$src, i32))]>;
1497 def LFSX : XForm_25<31, 535, (outs f4rc:$frD), (ins memrr:$src),
1498 "lfsx $frD, $src", IIC_LdStLFD,
1499 [(set f32:$frD, (load xaddr:$src))]>;
1500 def LFDX : XForm_25<31, 599, (outs f8rc:$frD), (ins memrr:$src),
1501 "lfdx $frD, $src", IIC_LdStLFD,
1502 [(set f64:$frD, (load xaddr:$src))]>;
1504 def LFIWAX : XForm_25<31, 855, (outs f8rc:$frD), (ins memrr:$src),
1505 "lfiwax $frD, $src", IIC_LdStLFD,
1506 [(set f64:$frD, (PPClfiwax xoaddr:$src))]>;
1507 def LFIWZX : XForm_25<31, 887, (outs f8rc:$frD), (ins memrr:$src),
1508 "lfiwzx $frD, $src", IIC_LdStLFD,
1509 [(set f64:$frD, (PPClfiwzx xoaddr:$src))]>;
1513 def LMW : DForm_1<46, (outs gprc:$rD), (ins memri:$src),
1514 "lmw $rD, $src", IIC_LdStLMW, []>;
1516 //===----------------------------------------------------------------------===//
1517 // PPC32 Store Instructions.
1520 // Unindexed (r+i) Stores.
1521 let PPC970_Unit = 2 in {
1522 def STB : DForm_1<38, (outs), (ins gprc:$rS, memri:$src),
1523 "stb $rS, $src", IIC_LdStStore,
1524 [(truncstorei8 i32:$rS, iaddr:$src)]>;
1525 def STH : DForm_1<44, (outs), (ins gprc:$rS, memri:$src),
1526 "sth $rS, $src", IIC_LdStStore,
1527 [(truncstorei16 i32:$rS, iaddr:$src)]>;
1528 def STW : DForm_1<36, (outs), (ins gprc:$rS, memri:$src),
1529 "stw $rS, $src", IIC_LdStStore,
1530 [(store i32:$rS, iaddr:$src)]>;
1531 def STFS : DForm_1<52, (outs), (ins f4rc:$rS, memri:$dst),
1532 "stfs $rS, $dst", IIC_LdStSTFD,
1533 [(store f32:$rS, iaddr:$dst)]>;
1534 def STFD : DForm_1<54, (outs), (ins f8rc:$rS, memri:$dst),
1535 "stfd $rS, $dst", IIC_LdStSTFD,
1536 [(store f64:$rS, iaddr:$dst)]>;
1539 // Unindexed (r+i) Stores with Update (preinc).
1540 let PPC970_Unit = 2, mayStore = 1 in {
1541 def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1542 "stbu $rS, $dst", IIC_LdStStoreUpd, []>,
1543 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1544 def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1545 "sthu $rS, $dst", IIC_LdStStoreUpd, []>,
1546 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1547 def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1548 "stwu $rS, $dst", IIC_LdStStoreUpd, []>,
1549 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1550 def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memri:$dst),
1551 "stfsu $rS, $dst", IIC_LdStSTFDU, []>,
1552 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1553 def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memri:$dst),
1554 "stfdu $rS, $dst", IIC_LdStSTFDU, []>,
1555 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1558 // Patterns to match the pre-inc stores. We can't put the patterns on
1559 // the instruction definitions directly as ISel wants the address base
1560 // and offset to be separate operands, not a single complex operand.
1561 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1562 (STBU $rS, iaddroff:$ptroff, $ptrreg)>;
1563 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1564 (STHU $rS, iaddroff:$ptroff, $ptrreg)>;
1565 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1566 (STWU $rS, iaddroff:$ptroff, $ptrreg)>;
1567 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1568 (STFSU $rS, iaddroff:$ptroff, $ptrreg)>;
1569 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1570 (STFDU $rS, iaddroff:$ptroff, $ptrreg)>;
1572 // Indexed (r+r) Stores.
1573 let PPC970_Unit = 2 in {
1574 def STBX : XForm_8<31, 215, (outs), (ins gprc:$rS, memrr:$dst),
1575 "stbx $rS, $dst", IIC_LdStStore,
1576 [(truncstorei8 i32:$rS, xaddr:$dst)]>,
1577 PPC970_DGroup_Cracked;
1578 def STHX : XForm_8<31, 407, (outs), (ins gprc:$rS, memrr:$dst),
1579 "sthx $rS, $dst", IIC_LdStStore,
1580 [(truncstorei16 i32:$rS, xaddr:$dst)]>,
1581 PPC970_DGroup_Cracked;
1582 def STWX : XForm_8<31, 151, (outs), (ins gprc:$rS, memrr:$dst),
1583 "stwx $rS, $dst", IIC_LdStStore,
1584 [(store i32:$rS, xaddr:$dst)]>,
1585 PPC970_DGroup_Cracked;
1587 def STHBRX: XForm_8<31, 918, (outs), (ins gprc:$rS, memrr:$dst),
1588 "sthbrx $rS, $dst", IIC_LdStStore,
1589 [(PPCstbrx i32:$rS, xoaddr:$dst, i16)]>,
1590 PPC970_DGroup_Cracked;
1591 def STWBRX: XForm_8<31, 662, (outs), (ins gprc:$rS, memrr:$dst),
1592 "stwbrx $rS, $dst", IIC_LdStStore,
1593 [(PPCstbrx i32:$rS, xoaddr:$dst, i32)]>,
1594 PPC970_DGroup_Cracked;
1596 def STFIWX: XForm_28<31, 983, (outs), (ins f8rc:$frS, memrr:$dst),
1597 "stfiwx $frS, $dst", IIC_LdStSTFD,
1598 [(PPCstfiwx f64:$frS, xoaddr:$dst)]>;
1600 def STFSX : XForm_28<31, 663, (outs), (ins f4rc:$frS, memrr:$dst),
1601 "stfsx $frS, $dst", IIC_LdStSTFD,
1602 [(store f32:$frS, xaddr:$dst)]>;
1603 def STFDX : XForm_28<31, 727, (outs), (ins f8rc:$frS, memrr:$dst),
1604 "stfdx $frS, $dst", IIC_LdStSTFD,
1605 [(store f64:$frS, xaddr:$dst)]>;
1608 // Indexed (r+r) Stores with Update (preinc).
1609 let PPC970_Unit = 2, mayStore = 1 in {
1610 def STBUX : XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1611 "stbux $rS, $dst", IIC_LdStStoreUpd, []>,
1612 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1613 PPC970_DGroup_Cracked;
1614 def STHUX : XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1615 "sthux $rS, $dst", IIC_LdStStoreUpd, []>,
1616 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1617 PPC970_DGroup_Cracked;
1618 def STWUX : XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1619 "stwux $rS, $dst", IIC_LdStStoreUpd, []>,
1620 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1621 PPC970_DGroup_Cracked;
1622 def STFSUX: XForm_8<31, 695, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memrr:$dst),
1623 "stfsux $rS, $dst", IIC_LdStSTFDU, []>,
1624 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1625 PPC970_DGroup_Cracked;
1626 def STFDUX: XForm_8<31, 759, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memrr:$dst),
1627 "stfdux $rS, $dst", IIC_LdStSTFDU, []>,
1628 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1629 PPC970_DGroup_Cracked;
1632 // Patterns to match the pre-inc stores. We can't put the patterns on
1633 // the instruction definitions directly as ISel wants the address base
1634 // and offset to be separate operands, not a single complex operand.
1635 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1636 (STBUX $rS, $ptrreg, $ptroff)>;
1637 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1638 (STHUX $rS, $ptrreg, $ptroff)>;
1639 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1640 (STWUX $rS, $ptrreg, $ptroff)>;
1641 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1642 (STFSUX $rS, $ptrreg, $ptroff)>;
1643 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1644 (STFDUX $rS, $ptrreg, $ptroff)>;
1647 def STMW : DForm_1<47, (outs), (ins gprc:$rS, memri:$dst),
1648 "stmw $rS, $dst", IIC_LdStLMW, []>;
1650 def SYNC : XForm_24_sync<31, 598, (outs), (ins i32imm:$L),
1651 "sync $L", IIC_LdStSync, []>, Requires<[IsNotBookE]>;
1653 let isCodeGenOnly = 1 in {
1654 def MSYNC : XForm_24_sync<31, 598, (outs), (ins),
1655 "msync", IIC_LdStSync, []>, Requires<[IsBookE]> {
1660 def : Pat<(int_ppc_sync), (SYNC 0)>, Requires<[IsNotBookE]>;
1661 def : Pat<(int_ppc_sync), (MSYNC)>, Requires<[IsBookE]>;
1663 //===----------------------------------------------------------------------===//
1664 // PPC32 Arithmetic Instructions.
1667 let PPC970_Unit = 1 in { // FXU Operations.
1668 def ADDI : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$imm),
1669 "addi $rD, $rA, $imm", IIC_IntSimple,
1670 [(set i32:$rD, (add i32:$rA, imm32SExt16:$imm))]>;
1671 let BaseName = "addic" in {
1672 let Defs = [CARRY] in
1673 def ADDIC : DForm_2<12, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1674 "addic $rD, $rA, $imm", IIC_IntGeneral,
1675 [(set i32:$rD, (addc i32:$rA, imm32SExt16:$imm))]>,
1676 RecFormRel, PPC970_DGroup_Cracked;
1677 let Defs = [CARRY, CR0] in
1678 def ADDICo : DForm_2<13, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1679 "addic. $rD, $rA, $imm", IIC_IntGeneral,
1680 []>, isDOT, RecFormRel;
1682 def ADDIS : DForm_2<15, (outs gprc:$rD), (ins gprc_nor0:$rA, s17imm:$imm),
1683 "addis $rD, $rA, $imm", IIC_IntSimple,
1684 [(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>;
1685 let isCodeGenOnly = 1 in
1686 def LA : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$sym),
1687 "la $rD, $sym($rA)", IIC_IntGeneral,
1688 [(set i32:$rD, (add i32:$rA,
1689 (PPClo tglobaladdr:$sym, 0)))]>;
1690 def MULLI : DForm_2< 7, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1691 "mulli $rD, $rA, $imm", IIC_IntMulLI,
1692 [(set i32:$rD, (mul i32:$rA, imm32SExt16:$imm))]>;
1693 let Defs = [CARRY] in
1694 def SUBFIC : DForm_2< 8, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1695 "subfic $rD, $rA, $imm", IIC_IntGeneral,
1696 [(set i32:$rD, (subc imm32SExt16:$imm, i32:$rA))]>;
1698 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
1699 def LI : DForm_2_r0<14, (outs gprc:$rD), (ins s16imm:$imm),
1700 "li $rD, $imm", IIC_IntSimple,
1701 [(set i32:$rD, imm32SExt16:$imm)]>;
1702 def LIS : DForm_2_r0<15, (outs gprc:$rD), (ins s17imm:$imm),
1703 "lis $rD, $imm", IIC_IntSimple,
1704 [(set i32:$rD, imm16ShiftedSExt:$imm)]>;
1708 let PPC970_Unit = 1 in { // FXU Operations.
1709 let Defs = [CR0] in {
1710 def ANDIo : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1711 "andi. $dst, $src1, $src2", IIC_IntGeneral,
1712 [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>,
1714 def ANDISo : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1715 "andis. $dst, $src1, $src2", IIC_IntGeneral,
1716 [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>,
1719 def ORI : DForm_4<24, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1720 "ori $dst, $src1, $src2", IIC_IntSimple,
1721 [(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>;
1722 def ORIS : DForm_4<25, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1723 "oris $dst, $src1, $src2", IIC_IntSimple,
1724 [(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>;
1725 def XORI : DForm_4<26, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1726 "xori $dst, $src1, $src2", IIC_IntSimple,
1727 [(set i32:$dst, (xor i32:$src1, immZExt16:$src2))]>;
1728 def XORIS : DForm_4<27, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1729 "xoris $dst, $src1, $src2", IIC_IntSimple,
1730 [(set i32:$dst, (xor i32:$src1, imm16ShiftedZExt:$src2))]>;
1732 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IIC_IntSimple,
1734 let isCodeGenOnly = 1 in {
1735 // The POWER6 and POWER7 have special group-terminating nops.
1736 def NOP_GT_PWR6 : DForm_4_fixedreg_zero<24, 1, (outs), (ins),
1737 "ori 1, 1, 0", IIC_IntSimple, []>;
1738 def NOP_GT_PWR7 : DForm_4_fixedreg_zero<24, 2, (outs), (ins),
1739 "ori 2, 2, 0", IIC_IntSimple, []>;
1742 let isCompare = 1, neverHasSideEffects = 1 in {
1743 def CMPWI : DForm_5_ext<11, (outs crrc:$crD), (ins gprc:$rA, s16imm:$imm),
1744 "cmpwi $crD, $rA, $imm", IIC_IntCompare>;
1745 def CMPLWI : DForm_6_ext<10, (outs crrc:$dst), (ins gprc:$src1, u16imm:$src2),
1746 "cmplwi $dst, $src1, $src2", IIC_IntCompare>;
1750 let PPC970_Unit = 1, neverHasSideEffects = 1 in { // FXU Operations.
1751 let isCommutable = 1 in {
1752 defm NAND : XForm_6r<31, 476, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1753 "nand", "$rA, $rS, $rB", IIC_IntSimple,
1754 [(set i32:$rA, (not (and i32:$rS, i32:$rB)))]>;
1755 defm AND : XForm_6r<31, 28, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1756 "and", "$rA, $rS, $rB", IIC_IntSimple,
1757 [(set i32:$rA, (and i32:$rS, i32:$rB))]>;
1759 defm ANDC : XForm_6r<31, 60, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1760 "andc", "$rA, $rS, $rB", IIC_IntSimple,
1761 [(set i32:$rA, (and i32:$rS, (not i32:$rB)))]>;
1762 let isCommutable = 1 in {
1763 defm OR : XForm_6r<31, 444, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1764 "or", "$rA, $rS, $rB", IIC_IntSimple,
1765 [(set i32:$rA, (or i32:$rS, i32:$rB))]>;
1766 defm NOR : XForm_6r<31, 124, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1767 "nor", "$rA, $rS, $rB", IIC_IntSimple,
1768 [(set i32:$rA, (not (or i32:$rS, i32:$rB)))]>;
1770 defm ORC : XForm_6r<31, 412, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1771 "orc", "$rA, $rS, $rB", IIC_IntSimple,
1772 [(set i32:$rA, (or i32:$rS, (not i32:$rB)))]>;
1773 let isCommutable = 1 in {
1774 defm EQV : XForm_6r<31, 284, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1775 "eqv", "$rA, $rS, $rB", IIC_IntSimple,
1776 [(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>;
1777 defm XOR : XForm_6r<31, 316, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1778 "xor", "$rA, $rS, $rB", IIC_IntSimple,
1779 [(set i32:$rA, (xor i32:$rS, i32:$rB))]>;
1781 defm SLW : XForm_6r<31, 24, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1782 "slw", "$rA, $rS, $rB", IIC_IntGeneral,
1783 [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>;
1784 defm SRW : XForm_6r<31, 536, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1785 "srw", "$rA, $rS, $rB", IIC_IntGeneral,
1786 [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>;
1787 defm SRAW : XForm_6rc<31, 792, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1788 "sraw", "$rA, $rS, $rB", IIC_IntShift,
1789 [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>;
1792 let PPC970_Unit = 1 in { // FXU Operations.
1793 let neverHasSideEffects = 1 in {
1794 defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH),
1795 "srawi", "$rA, $rS, $SH", IIC_IntShift,
1796 [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>;
1797 defm CNTLZW : XForm_11r<31, 26, (outs gprc:$rA), (ins gprc:$rS),
1798 "cntlzw", "$rA, $rS", IIC_IntGeneral,
1799 [(set i32:$rA, (ctlz i32:$rS))]>;
1800 defm EXTSB : XForm_11r<31, 954, (outs gprc:$rA), (ins gprc:$rS),
1801 "extsb", "$rA, $rS", IIC_IntSimple,
1802 [(set i32:$rA, (sext_inreg i32:$rS, i8))]>;
1803 defm EXTSH : XForm_11r<31, 922, (outs gprc:$rA), (ins gprc:$rS),
1804 "extsh", "$rA, $rS", IIC_IntSimple,
1805 [(set i32:$rA, (sext_inreg i32:$rS, i16))]>;
1807 let isCompare = 1, neverHasSideEffects = 1 in {
1808 def CMPW : XForm_16_ext<31, 0, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
1809 "cmpw $crD, $rA, $rB", IIC_IntCompare>;
1810 def CMPLW : XForm_16_ext<31, 32, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
1811 "cmplw $crD, $rA, $rB", IIC_IntCompare>;
1814 let PPC970_Unit = 3 in { // FPU Operations.
1815 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
1816 // "fcmpo $crD, $fA, $fB", IIC_FPCompare>;
1817 let isCompare = 1, neverHasSideEffects = 1 in {
1818 def FCMPUS : XForm_17<63, 0, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB),
1819 "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
1820 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1821 def FCMPUD : XForm_17<63, 0, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB),
1822 "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
1825 let Uses = [RM] in {
1826 let neverHasSideEffects = 1 in {
1827 defm FCTIW : XForm_26r<63, 14, (outs f8rc:$frD), (ins f8rc:$frB),
1828 "fctiw", "$frD, $frB", IIC_FPGeneral,
1830 defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB),
1831 "fctiwz", "$frD, $frB", IIC_FPGeneral,
1832 [(set f64:$frD, (PPCfctiwz f64:$frB))]>;
1834 defm FRSP : XForm_26r<63, 12, (outs f4rc:$frD), (ins f8rc:$frB),
1835 "frsp", "$frD, $frB", IIC_FPGeneral,
1836 [(set f32:$frD, (fround f64:$frB))]>;
1838 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1839 defm FRIND : XForm_26r<63, 392, (outs f8rc:$frD), (ins f8rc:$frB),
1840 "frin", "$frD, $frB", IIC_FPGeneral,
1841 [(set f64:$frD, (frnd f64:$frB))]>;
1842 defm FRINS : XForm_26r<63, 392, (outs f4rc:$frD), (ins f4rc:$frB),
1843 "frin", "$frD, $frB", IIC_FPGeneral,
1844 [(set f32:$frD, (frnd f32:$frB))]>;
1847 let neverHasSideEffects = 1 in {
1848 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1849 defm FRIPD : XForm_26r<63, 456, (outs f8rc:$frD), (ins f8rc:$frB),
1850 "frip", "$frD, $frB", IIC_FPGeneral,
1851 [(set f64:$frD, (fceil f64:$frB))]>;
1852 defm FRIPS : XForm_26r<63, 456, (outs f4rc:$frD), (ins f4rc:$frB),
1853 "frip", "$frD, $frB", IIC_FPGeneral,
1854 [(set f32:$frD, (fceil f32:$frB))]>;
1855 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1856 defm FRIZD : XForm_26r<63, 424, (outs f8rc:$frD), (ins f8rc:$frB),
1857 "friz", "$frD, $frB", IIC_FPGeneral,
1858 [(set f64:$frD, (ftrunc f64:$frB))]>;
1859 defm FRIZS : XForm_26r<63, 424, (outs f4rc:$frD), (ins f4rc:$frB),
1860 "friz", "$frD, $frB", IIC_FPGeneral,
1861 [(set f32:$frD, (ftrunc f32:$frB))]>;
1862 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1863 defm FRIMD : XForm_26r<63, 488, (outs f8rc:$frD), (ins f8rc:$frB),
1864 "frim", "$frD, $frB", IIC_FPGeneral,
1865 [(set f64:$frD, (ffloor f64:$frB))]>;
1866 defm FRIMS : XForm_26r<63, 488, (outs f4rc:$frD), (ins f4rc:$frB),
1867 "frim", "$frD, $frB", IIC_FPGeneral,
1868 [(set f32:$frD, (ffloor f32:$frB))]>;
1870 defm FSQRT : XForm_26r<63, 22, (outs f8rc:$frD), (ins f8rc:$frB),
1871 "fsqrt", "$frD, $frB", IIC_FPSqrtD,
1872 [(set f64:$frD, (fsqrt f64:$frB))]>;
1873 defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$frD), (ins f4rc:$frB),
1874 "fsqrts", "$frD, $frB", IIC_FPSqrtS,
1875 [(set f32:$frD, (fsqrt f32:$frB))]>;
1880 /// Note that FMR is defined as pseudo-ops on the PPC970 because they are
1881 /// often coalesced away and we don't want the dispatch group builder to think
1882 /// that they will fill slots (which could cause the load of a LSU reject to
1883 /// sneak into a d-group with a store).
1884 let neverHasSideEffects = 1 in
1885 defm FMR : XForm_26r<63, 72, (outs f4rc:$frD), (ins f4rc:$frB),
1886 "fmr", "$frD, $frB", IIC_FPGeneral,
1887 []>, // (set f32:$frD, f32:$frB)
1890 let PPC970_Unit = 3, neverHasSideEffects = 1 in { // FPU Operations.
1891 // These are artificially split into two different forms, for 4/8 byte FP.
1892 defm FABSS : XForm_26r<63, 264, (outs f4rc:$frD), (ins f4rc:$frB),
1893 "fabs", "$frD, $frB", IIC_FPGeneral,
1894 [(set f32:$frD, (fabs f32:$frB))]>;
1895 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1896 defm FABSD : XForm_26r<63, 264, (outs f8rc:$frD), (ins f8rc:$frB),
1897 "fabs", "$frD, $frB", IIC_FPGeneral,
1898 [(set f64:$frD, (fabs f64:$frB))]>;
1899 defm FNABSS : XForm_26r<63, 136, (outs f4rc:$frD), (ins f4rc:$frB),
1900 "fnabs", "$frD, $frB", IIC_FPGeneral,
1901 [(set f32:$frD, (fneg (fabs f32:$frB)))]>;
1902 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1903 defm FNABSD : XForm_26r<63, 136, (outs f8rc:$frD), (ins f8rc:$frB),
1904 "fnabs", "$frD, $frB", IIC_FPGeneral,
1905 [(set f64:$frD, (fneg (fabs f64:$frB)))]>;
1906 defm FNEGS : XForm_26r<63, 40, (outs f4rc:$frD), (ins f4rc:$frB),
1907 "fneg", "$frD, $frB", IIC_FPGeneral,
1908 [(set f32:$frD, (fneg f32:$frB))]>;
1909 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1910 defm FNEGD : XForm_26r<63, 40, (outs f8rc:$frD), (ins f8rc:$frB),
1911 "fneg", "$frD, $frB", IIC_FPGeneral,
1912 [(set f64:$frD, (fneg f64:$frB))]>;
1914 defm FCPSGNS : XForm_28r<63, 8, (outs f4rc:$frD), (ins f4rc:$frA, f4rc:$frB),
1915 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
1916 [(set f32:$frD, (fcopysign f32:$frB, f32:$frA))]>;
1917 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1918 defm FCPSGND : XForm_28r<63, 8, (outs f8rc:$frD), (ins f8rc:$frA, f8rc:$frB),
1919 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
1920 [(set f64:$frD, (fcopysign f64:$frB, f64:$frA))]>;
1922 // Reciprocal estimates.
1923 defm FRE : XForm_26r<63, 24, (outs f8rc:$frD), (ins f8rc:$frB),
1924 "fre", "$frD, $frB", IIC_FPGeneral,
1925 [(set f64:$frD, (PPCfre f64:$frB))]>;
1926 defm FRES : XForm_26r<59, 24, (outs f4rc:$frD), (ins f4rc:$frB),
1927 "fres", "$frD, $frB", IIC_FPGeneral,
1928 [(set f32:$frD, (PPCfre f32:$frB))]>;
1929 defm FRSQRTE : XForm_26r<63, 26, (outs f8rc:$frD), (ins f8rc:$frB),
1930 "frsqrte", "$frD, $frB", IIC_FPGeneral,
1931 [(set f64:$frD, (PPCfrsqrte f64:$frB))]>;
1932 defm FRSQRTES : XForm_26r<59, 26, (outs f4rc:$frD), (ins f4rc:$frB),
1933 "frsqrtes", "$frD, $frB", IIC_FPGeneral,
1934 [(set f32:$frD, (PPCfrsqrte f32:$frB))]>;
1937 // XL-Form instructions. condition register logical ops.
1939 let neverHasSideEffects = 1 in
1940 def MCRF : XLForm_3<19, 0, (outs crrc:$BF), (ins crrc:$BFA),
1941 "mcrf $BF, $BFA", IIC_BrMCR>,
1942 PPC970_DGroup_First, PPC970_Unit_CRU;
1944 let isCommutable = 1 in {
1945 def CRAND : XLForm_1<19, 257, (outs crbitrc:$CRD),
1946 (ins crbitrc:$CRA, crbitrc:$CRB),
1947 "crand $CRD, $CRA, $CRB", IIC_BrCR,
1948 [(set i1:$CRD, (and i1:$CRA, i1:$CRB))]>;
1950 def CRNAND : XLForm_1<19, 225, (outs crbitrc:$CRD),
1951 (ins crbitrc:$CRA, crbitrc:$CRB),
1952 "crnand $CRD, $CRA, $CRB", IIC_BrCR,
1953 [(set i1:$CRD, (not (and i1:$CRA, i1:$CRB)))]>;
1955 def CROR : XLForm_1<19, 449, (outs crbitrc:$CRD),
1956 (ins crbitrc:$CRA, crbitrc:$CRB),
1957 "cror $CRD, $CRA, $CRB", IIC_BrCR,
1958 [(set i1:$CRD, (or i1:$CRA, i1:$CRB))]>;
1960 def CRXOR : XLForm_1<19, 193, (outs crbitrc:$CRD),
1961 (ins crbitrc:$CRA, crbitrc:$CRB),
1962 "crxor $CRD, $CRA, $CRB", IIC_BrCR,
1963 [(set i1:$CRD, (xor i1:$CRA, i1:$CRB))]>;
1965 def CRNOR : XLForm_1<19, 33, (outs crbitrc:$CRD),
1966 (ins crbitrc:$CRA, crbitrc:$CRB),
1967 "crnor $CRD, $CRA, $CRB", IIC_BrCR,
1968 [(set i1:$CRD, (not (or i1:$CRA, i1:$CRB)))]>;
1970 def CREQV : XLForm_1<19, 289, (outs crbitrc:$CRD),
1971 (ins crbitrc:$CRA, crbitrc:$CRB),
1972 "creqv $CRD, $CRA, $CRB", IIC_BrCR,
1973 [(set i1:$CRD, (not (xor i1:$CRA, i1:$CRB)))]>;
1976 def CRANDC : XLForm_1<19, 129, (outs crbitrc:$CRD),
1977 (ins crbitrc:$CRA, crbitrc:$CRB),
1978 "crandc $CRD, $CRA, $CRB", IIC_BrCR,
1979 [(set i1:$CRD, (and i1:$CRA, (not i1:$CRB)))]>;
1981 def CRORC : XLForm_1<19, 417, (outs crbitrc:$CRD),
1982 (ins crbitrc:$CRA, crbitrc:$CRB),
1983 "crorc $CRD, $CRA, $CRB", IIC_BrCR,
1984 [(set i1:$CRD, (or i1:$CRA, (not i1:$CRB)))]>;
1986 let isCodeGenOnly = 1 in {
1987 def CRSET : XLForm_1_ext<19, 289, (outs crbitrc:$dst), (ins),
1988 "creqv $dst, $dst, $dst", IIC_BrCR,
1989 [(set i1:$dst, 1)]>;
1991 def CRUNSET: XLForm_1_ext<19, 193, (outs crbitrc:$dst), (ins),
1992 "crxor $dst, $dst, $dst", IIC_BrCR,
1993 [(set i1:$dst, 0)]>;
1995 let Defs = [CR1EQ], CRD = 6 in {
1996 def CR6SET : XLForm_1_ext<19, 289, (outs), (ins),
1997 "creqv 6, 6, 6", IIC_BrCR,
2000 def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins),
2001 "crxor 6, 6, 6", IIC_BrCR,
2006 // XFX-Form instructions. Instructions that deal with SPRs.
2009 def MFSPR : XFXForm_1<31, 339, (outs gprc:$RT), (ins i32imm:$SPR),
2010 "mfspr $RT, $SPR", IIC_SprMFSPR>;
2011 def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RT),
2012 "mtspr $SPR, $RT", IIC_SprMTSPR>;
2014 def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR),
2015 "mftb $RT, $SPR", IIC_SprMFTB>, Deprecated<DeprecatedMFTB>;
2017 let Uses = [CTR] in {
2018 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$rT), (ins),
2019 "mfctr $rT", IIC_SprMFSPR>,
2020 PPC970_DGroup_First, PPC970_Unit_FXU;
2022 let Defs = [CTR], Pattern = [(PPCmtctr i32:$rS)] in {
2023 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
2024 "mtctr $rS", IIC_SprMTSPR>,
2025 PPC970_DGroup_First, PPC970_Unit_FXU;
2027 let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR] in {
2028 let Pattern = [(int_ppc_mtctr i32:$rS)] in
2029 def MTCTRloop : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
2030 "mtctr $rS", IIC_SprMTSPR>,
2031 PPC970_DGroup_First, PPC970_Unit_FXU;
2034 let Defs = [LR] in {
2035 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins gprc:$rS),
2036 "mtlr $rS", IIC_SprMTSPR>,
2037 PPC970_DGroup_First, PPC970_Unit_FXU;
2039 let Uses = [LR] in {
2040 def MFLR : XFXForm_1_ext<31, 339, 8, (outs gprc:$rT), (ins),
2041 "mflr $rT", IIC_SprMFSPR>,
2042 PPC970_DGroup_First, PPC970_Unit_FXU;
2045 let isCodeGenOnly = 1 in {
2046 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed
2047 // like a GPR on the PPC970. As such, copies in and out have the same
2048 // performance characteristics as an OR instruction.
2049 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins gprc:$rS),
2050 "mtspr 256, $rS", IIC_IntGeneral>,
2051 PPC970_DGroup_Single, PPC970_Unit_FXU;
2052 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), (ins),
2053 "mfspr $rT, 256", IIC_IntGeneral>,
2054 PPC970_DGroup_First, PPC970_Unit_FXU;
2056 def MTVRSAVEv : XFXForm_7_ext<31, 467, 256,
2057 (outs VRSAVERC:$reg), (ins gprc:$rS),
2058 "mtspr 256, $rS", IIC_IntGeneral>,
2059 PPC970_DGroup_Single, PPC970_Unit_FXU;
2060 def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT),
2061 (ins VRSAVERC:$reg),
2062 "mfspr $rT, 256", IIC_IntGeneral>,
2063 PPC970_DGroup_First, PPC970_Unit_FXU;
2066 // SPILL_VRSAVE - Indicate that we're dumping the VRSAVE register,
2067 // so we'll need to scavenge a register for it.
2069 def SPILL_VRSAVE : Pseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F),
2070 "#SPILL_VRSAVE", []>;
2072 // RESTORE_VRSAVE - Indicate that we're restoring the VRSAVE register (previously
2073 // spilled), so we'll need to scavenge a register for it.
2075 def RESTORE_VRSAVE : Pseudo<(outs VRSAVERC:$vrsave), (ins memri:$F),
2076 "#RESTORE_VRSAVE", []>;
2078 let neverHasSideEffects = 1 in {
2079 def MTOCRF: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins gprc:$ST),
2080 "mtocrf $FXM, $ST", IIC_BrMCRX>,
2081 PPC970_DGroup_First, PPC970_Unit_CRU;
2083 def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$rS),
2084 "mtcrf $FXM, $rS", IIC_BrMCRX>,
2085 PPC970_MicroCode, PPC970_Unit_CRU;
2087 let hasExtraSrcRegAllocReq = 1 in // to enable post-ra anti-dep breaking.
2088 def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$rT), (ins crbitm:$FXM),
2089 "mfocrf $rT, $FXM", IIC_SprMFCRF>,
2090 PPC970_DGroup_First, PPC970_Unit_CRU;
2092 def MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins),
2093 "mfcr $rT", IIC_SprMFCR>,
2094 PPC970_MicroCode, PPC970_Unit_CRU;
2095 } // neverHasSideEffects = 1
2097 // Pseudo instruction to perform FADD in round-to-zero mode.
2098 let usesCustomInserter = 1, Uses = [RM] in {
2099 def FADDrtz: Pseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "",
2100 [(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>;
2103 // The above pseudo gets expanded to make use of the following instructions
2104 // to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level.
2105 let Uses = [RM], Defs = [RM] in {
2106 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
2107 "mtfsb0 $FM", IIC_IntMTFSB0, []>,
2108 PPC970_DGroup_Single, PPC970_Unit_FPU;
2109 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
2110 "mtfsb1 $FM", IIC_IntMTFSB0, []>,
2111 PPC970_DGroup_Single, PPC970_Unit_FPU;
2112 def MTFSF : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$rT),
2113 "mtfsf $FM, $rT", IIC_IntMTFSB0, []>,
2114 PPC970_DGroup_Single, PPC970_Unit_FPU;
2116 let Uses = [RM] in {
2117 def MFFS : XForm_42<63, 583, (outs f8rc:$rT), (ins),
2118 "mffs $rT", IIC_IntMFFS,
2119 [(set f64:$rT, (PPCmffs))]>,
2120 PPC970_DGroup_Single, PPC970_Unit_FPU;
2124 let PPC970_Unit = 1, neverHasSideEffects = 1 in { // FXU Operations.
2125 // XO-Form instructions. Arithmetic instructions that can set overflow bit
2126 let isCommutable = 1 in
2127 defm ADD4 : XOForm_1r<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2128 "add", "$rT, $rA, $rB", IIC_IntSimple,
2129 [(set i32:$rT, (add i32:$rA, i32:$rB))]>;
2130 let isCodeGenOnly = 1 in
2131 def ADD4TLS : XOForm_1<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, tlsreg32:$rB),
2132 "add $rT, $rA, $rB", IIC_IntSimple,
2133 [(set i32:$rT, (add i32:$rA, tglobaltlsaddr:$rB))]>;
2134 let isCommutable = 1 in
2135 defm ADDC : XOForm_1rc<31, 10, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2136 "addc", "$rT, $rA, $rB", IIC_IntGeneral,
2137 [(set i32:$rT, (addc i32:$rA, i32:$rB))]>,
2138 PPC970_DGroup_Cracked;
2140 defm DIVW : XOForm_1r<31, 491, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2141 "divw", "$rT, $rA, $rB", IIC_IntDivW,
2142 [(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>,
2143 PPC970_DGroup_First, PPC970_DGroup_Cracked;
2144 defm DIVWU : XOForm_1r<31, 459, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2145 "divwu", "$rT, $rA, $rB", IIC_IntDivW,
2146 [(set i32:$rT, (udiv i32:$rA, i32:$rB))]>,
2147 PPC970_DGroup_First, PPC970_DGroup_Cracked;
2148 let isCommutable = 1 in {
2149 defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2150 "mulhw", "$rT, $rA, $rB", IIC_IntMulHW,
2151 [(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>;
2152 defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2153 "mulhwu", "$rT, $rA, $rB", IIC_IntMulHWU,
2154 [(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>;
2155 defm MULLW : XOForm_1r<31, 235, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2156 "mullw", "$rT, $rA, $rB", IIC_IntMulHW,
2157 [(set i32:$rT, (mul i32:$rA, i32:$rB))]>;
2159 defm SUBF : XOForm_1r<31, 40, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2160 "subf", "$rT, $rA, $rB", IIC_IntGeneral,
2161 [(set i32:$rT, (sub i32:$rB, i32:$rA))]>;
2162 defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2163 "subfc", "$rT, $rA, $rB", IIC_IntGeneral,
2164 [(set i32:$rT, (subc i32:$rB, i32:$rA))]>,
2165 PPC970_DGroup_Cracked;
2166 defm NEG : XOForm_3r<31, 104, 0, (outs gprc:$rT), (ins gprc:$rA),
2167 "neg", "$rT, $rA", IIC_IntSimple,
2168 [(set i32:$rT, (ineg i32:$rA))]>;
2169 let Uses = [CARRY] in {
2170 let isCommutable = 1 in
2171 defm ADDE : XOForm_1rc<31, 138, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2172 "adde", "$rT, $rA, $rB", IIC_IntGeneral,
2173 [(set i32:$rT, (adde i32:$rA, i32:$rB))]>;
2174 defm ADDME : XOForm_3rc<31, 234, 0, (outs gprc:$rT), (ins gprc:$rA),
2175 "addme", "$rT, $rA", IIC_IntGeneral,
2176 [(set i32:$rT, (adde i32:$rA, -1))]>;
2177 defm ADDZE : XOForm_3rc<31, 202, 0, (outs gprc:$rT), (ins gprc:$rA),
2178 "addze", "$rT, $rA", IIC_IntGeneral,
2179 [(set i32:$rT, (adde i32:$rA, 0))]>;
2180 defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2181 "subfe", "$rT, $rA, $rB", IIC_IntGeneral,
2182 [(set i32:$rT, (sube i32:$rB, i32:$rA))]>;
2183 defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$rT), (ins gprc:$rA),
2184 "subfme", "$rT, $rA", IIC_IntGeneral,
2185 [(set i32:$rT, (sube -1, i32:$rA))]>;
2186 defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$rT), (ins gprc:$rA),
2187 "subfze", "$rT, $rA", IIC_IntGeneral,
2188 [(set i32:$rT, (sube 0, i32:$rA))]>;
2192 // A-Form instructions. Most of the instructions executed in the FPU are of
2195 let PPC970_Unit = 3, neverHasSideEffects = 1 in { // FPU Operations.
2196 let Uses = [RM] in {
2197 let isCommutable = 1 in {
2198 defm FMADD : AForm_1r<63, 29,
2199 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2200 "fmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2201 [(set f64:$FRT, (fma f64:$FRA, f64:$FRC, f64:$FRB))]>;
2202 defm FMADDS : AForm_1r<59, 29,
2203 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2204 "fmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2205 [(set f32:$FRT, (fma f32:$FRA, f32:$FRC, f32:$FRB))]>;
2206 defm FMSUB : AForm_1r<63, 28,
2207 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2208 "fmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2210 (fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>;
2211 defm FMSUBS : AForm_1r<59, 28,
2212 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2213 "fmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2215 (fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>;
2216 defm FNMADD : AForm_1r<63, 31,
2217 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2218 "fnmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2220 (fneg (fma f64:$FRA, f64:$FRC, f64:$FRB)))]>;
2221 defm FNMADDS : AForm_1r<59, 31,
2222 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2223 "fnmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2225 (fneg (fma f32:$FRA, f32:$FRC, f32:$FRB)))]>;
2226 defm FNMSUB : AForm_1r<63, 30,
2227 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2228 "fnmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2229 [(set f64:$FRT, (fneg (fma f64:$FRA, f64:$FRC,
2230 (fneg f64:$FRB))))]>;
2231 defm FNMSUBS : AForm_1r<59, 30,
2232 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2233 "fnmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2234 [(set f32:$FRT, (fneg (fma f32:$FRA, f32:$FRC,
2235 (fneg f32:$FRB))))]>;
2238 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
2239 // having 4 of these, force the comparison to always be an 8-byte double (code
2240 // should use an FMRSD if the input comparison value really wants to be a float)
2241 // and 4/8 byte forms for the result and operand type..
2242 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2243 defm FSELD : AForm_1r<63, 23,
2244 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2245 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2246 [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>;
2247 defm FSELS : AForm_1r<63, 23,
2248 (outs f4rc:$FRT), (ins f8rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2249 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2250 [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>;
2251 let Uses = [RM] in {
2252 let isCommutable = 1 in {
2253 defm FADD : AForm_2r<63, 21,
2254 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2255 "fadd", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2256 [(set f64:$FRT, (fadd f64:$FRA, f64:$FRB))]>;
2257 defm FADDS : AForm_2r<59, 21,
2258 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2259 "fadds", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2260 [(set f32:$FRT, (fadd f32:$FRA, f32:$FRB))]>;
2262 defm FDIV : AForm_2r<63, 18,
2263 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2264 "fdiv", "$FRT, $FRA, $FRB", IIC_FPDivD,
2265 [(set f64:$FRT, (fdiv f64:$FRA, f64:$FRB))]>;
2266 defm FDIVS : AForm_2r<59, 18,
2267 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2268 "fdivs", "$FRT, $FRA, $FRB", IIC_FPDivS,
2269 [(set f32:$FRT, (fdiv f32:$FRA, f32:$FRB))]>;
2270 let isCommutable = 1 in {
2271 defm FMUL : AForm_3r<63, 25,
2272 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC),
2273 "fmul", "$FRT, $FRA, $FRC", IIC_FPFused,
2274 [(set f64:$FRT, (fmul f64:$FRA, f64:$FRC))]>;
2275 defm FMULS : AForm_3r<59, 25,
2276 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC),
2277 "fmuls", "$FRT, $FRA, $FRC", IIC_FPGeneral,
2278 [(set f32:$FRT, (fmul f32:$FRA, f32:$FRC))]>;
2280 defm FSUB : AForm_2r<63, 20,
2281 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2282 "fsub", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2283 [(set f64:$FRT, (fsub f64:$FRA, f64:$FRB))]>;
2284 defm FSUBS : AForm_2r<59, 20,
2285 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2286 "fsubs", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2287 [(set f32:$FRT, (fsub f32:$FRA, f32:$FRB))]>;
2291 let neverHasSideEffects = 1 in {
2292 let PPC970_Unit = 1 in { // FXU Operations.
2294 def ISEL : AForm_4<31, 15,
2295 (outs gprc:$rT), (ins gprc_nor0:$rA, gprc:$rB, crbitrc:$cond),
2296 "isel $rT, $rA, $rB, $cond", IIC_IntGeneral,
2300 let PPC970_Unit = 1 in { // FXU Operations.
2301 // M-Form instructions. rotate and mask instructions.
2303 let isCommutable = 1 in {
2304 // RLWIMI can be commuted if the rotate amount is zero.
2305 defm RLWIMI : MForm_2r<20, (outs gprc:$rA),
2306 (ins gprc:$rSi, gprc:$rS, u5imm:$SH, u5imm:$MB,
2307 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME",
2308 IIC_IntRotate, []>, PPC970_DGroup_Cracked,
2309 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">;
2311 let BaseName = "rlwinm" in {
2312 def RLWINM : MForm_2<21,
2313 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2314 "rlwinm $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
2317 def RLWINMo : MForm_2<21,
2318 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2319 "rlwinm. $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
2320 []>, isDOT, RecFormRel, PPC970_DGroup_Cracked;
2322 defm RLWNM : MForm_2r<23, (outs gprc:$rA),
2323 (ins gprc:$rS, gprc:$rB, u5imm:$MB, u5imm:$ME),
2324 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral,
2327 } // neverHasSideEffects = 1
2329 //===----------------------------------------------------------------------===//
2330 // PowerPC Instruction Patterns
2333 // Arbitrary immediate support. Implement in terms of LIS/ORI.
2334 def : Pat<(i32 imm:$imm),
2335 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
2337 // Implement the 'not' operation with the NOR instruction.
2338 def i32not : OutPatFrag<(ops node:$in),
2340 def : Pat<(not i32:$in),
2343 // ADD an arbitrary immediate.
2344 def : Pat<(add i32:$in, imm:$imm),
2345 (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
2346 // OR an arbitrary immediate.
2347 def : Pat<(or i32:$in, imm:$imm),
2348 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2349 // XOR an arbitrary immediate.
2350 def : Pat<(xor i32:$in, imm:$imm),
2351 (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2353 def : Pat<(sub imm32SExt16:$imm, i32:$in),
2354 (SUBFIC $in, imm:$imm)>;
2357 def : Pat<(shl i32:$in, (i32 imm:$imm)),
2358 (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>;
2359 def : Pat<(srl i32:$in, (i32 imm:$imm)),
2360 (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>;
2363 def : Pat<(rotl i32:$in, i32:$sh),
2364 (RLWNM $in, $sh, 0, 31)>;
2365 def : Pat<(rotl i32:$in, (i32 imm:$imm)),
2366 (RLWINM $in, imm:$imm, 0, 31)>;
2369 def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm),
2370 (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
2373 def : Pat<(PPCcall (i32 tglobaladdr:$dst)),
2374 (BL tglobaladdr:$dst)>;
2375 def : Pat<(PPCcall (i32 texternalsym:$dst)),
2376 (BL texternalsym:$dst)>;
2379 def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm),
2380 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
2382 def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
2383 (TCRETURNdi texternalsym:$dst, imm:$imm)>;
2385 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
2386 (TCRETURNri CTRRC:$dst, imm:$imm)>;
2390 // Hi and Lo for Darwin Global Addresses.
2391 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
2392 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
2393 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
2394 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
2395 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
2396 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
2397 def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>;
2398 def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>;
2399 def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in),
2400 (ADDIS $in, tglobaltlsaddr:$g)>;
2401 def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in),
2402 (ADDI $in, tglobaltlsaddr:$g)>;
2403 def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)),
2404 (ADDIS $in, tglobaladdr:$g)>;
2405 def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)),
2406 (ADDIS $in, tconstpool:$g)>;
2407 def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)),
2408 (ADDIS $in, tjumptable:$g)>;
2409 def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)),
2410 (ADDIS $in, tblockaddress:$g)>;
2412 // Support for thread-local storage.
2413 def PPC32GOT: Pseudo<(outs gprc:$rD), (ins), "#PPC32GOT",
2414 [(set i32:$rD, (PPCppc32GOT))]>;
2416 // Get the _GLOBAL_OFFSET_TABLE_ in PIC mode.
2417 // This uses two output registers, the first as the real output, the second as a
2418 // temporary register, used internally in code generation.
2419 def PPC32PICGOT: Pseudo<(outs gprc:$rD, gprc:$rT), (ins), "#PPC32PICGOT",
2420 []>, NoEncode<"$rT">;
2422 def LDgotTprelL32: Pseudo<(outs gprc:$rD), (ins s16imm:$disp, gprc_nor0:$reg),
2425 (PPCldGotTprelL tglobaltlsaddr:$disp, i32:$reg))]>;
2426 def : Pat<(PPCaddTls i32:$in, tglobaltlsaddr:$g),
2427 (ADD4TLS $in, tglobaltlsaddr:$g)>;
2429 def ADDItlsgdL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2432 (PPCaddiTlsgdL i32:$reg, tglobaltlsaddr:$disp))]>;
2433 def GETtlsADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),
2436 (PPCgetTlsAddr i32:$reg, tglobaltlsaddr:$sym))]>;
2437 def ADDItlsldL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2440 (PPCaddiTlsldL i32:$reg, tglobaltlsaddr:$disp))]>;
2441 def GETtlsldADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),
2444 (PPCgetTlsldAddr i32:$reg, tglobaltlsaddr:$sym))]>;
2445 def ADDIdtprelL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2448 (PPCaddiDtprelL i32:$reg, tglobaltlsaddr:$disp))]>;
2449 def ADDISdtprelHA32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2452 (PPCaddisDtprelHA i32:$reg,
2453 tglobaltlsaddr:$disp))]>;
2455 // Support for Position-independent code
2456 def LWZtoc: Pseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg),
2459 (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>;
2460 // Get Global (GOT) Base Register offset, from the word immediately preceding
2461 // the function label.
2462 def GetGBRO: Pseudo<(outs gprc:$rT), (ins gprc:$rI), "#GetGBRO", []>;
2463 // Update the Global(GOT) Base Register with the above offset.
2464 def UpdateGBR: Pseudo<(outs gprc:$rT), (ins gprc:$rI), "#UpdateGBR", []>;
2467 // Standard shifts. These are represented separately from the real shifts above
2468 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
2470 def : Pat<(sra i32:$rS, i32:$rB),
2472 def : Pat<(srl i32:$rS, i32:$rB),
2474 def : Pat<(shl i32:$rS, i32:$rB),
2477 def : Pat<(zextloadi1 iaddr:$src),
2479 def : Pat<(zextloadi1 xaddr:$src),
2481 def : Pat<(extloadi1 iaddr:$src),
2483 def : Pat<(extloadi1 xaddr:$src),
2485 def : Pat<(extloadi8 iaddr:$src),
2487 def : Pat<(extloadi8 xaddr:$src),
2489 def : Pat<(extloadi16 iaddr:$src),
2491 def : Pat<(extloadi16 xaddr:$src),
2493 def : Pat<(f64 (extloadf32 iaddr:$src)),
2494 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
2495 def : Pat<(f64 (extloadf32 xaddr:$src)),
2496 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
2498 def : Pat<(f64 (fextend f32:$src)),
2499 (COPY_TO_REGCLASS $src, F8RC)>;
2501 def : Pat<(atomic_fence (imm), (imm)), (SYNC 0)>, Requires<[IsNotBookE]>;
2502 def : Pat<(atomic_fence (imm), (imm)), (MSYNC)>, Requires<[IsBookE]>;
2504 // Additional FNMSUB patterns: -a*c + b == -(a*c - b)
2505 def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),
2506 (FNMSUB $A, $C, $B)>;
2507 def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B),
2508 (FNMSUB $A, $C, $B)>;
2509 def : Pat<(fma (fneg f32:$A), f32:$C, f32:$B),
2510 (FNMSUBS $A, $C, $B)>;
2511 def : Pat<(fma f32:$A, (fneg f32:$C), f32:$B),
2512 (FNMSUBS $A, $C, $B)>;
2514 // FCOPYSIGN's operand types need not agree.
2515 def : Pat<(fcopysign f64:$frB, f32:$frA),
2516 (FCPSGND (COPY_TO_REGCLASS $frA, F8RC), $frB)>;
2517 def : Pat<(fcopysign f32:$frB, f64:$frA),
2518 (FCPSGNS (COPY_TO_REGCLASS $frA, F4RC), $frB)>;
2520 include "PPCInstrAltivec.td"
2521 include "PPCInstr64Bit.td"
2522 include "PPCInstrVSX.td"
2524 def crnot : OutPatFrag<(ops node:$in),
2526 def : Pat<(not i1:$in),
2529 // Patterns for arithmetic i1 operations.
2530 def : Pat<(add i1:$a, i1:$b),
2532 def : Pat<(sub i1:$a, i1:$b),
2534 def : Pat<(mul i1:$a, i1:$b),
2537 // We're sometimes asked to materialize i1 -1, which is just 1 in this case
2538 // (-1 is used to mean all bits set).
2539 def : Pat<(i1 -1), (CRSET)>;
2541 // i1 extensions, implemented in terms of isel.
2542 def : Pat<(i32 (zext i1:$in)),
2543 (SELECT_I4 $in, (LI 1), (LI 0))>;
2544 def : Pat<(i32 (sext i1:$in)),
2545 (SELECT_I4 $in, (LI -1), (LI 0))>;
2547 def : Pat<(i64 (zext i1:$in)),
2548 (SELECT_I8 $in, (LI8 1), (LI8 0))>;
2549 def : Pat<(i64 (sext i1:$in)),
2550 (SELECT_I8 $in, (LI8 -1), (LI8 0))>;
2552 // FIXME: We should choose either a zext or a sext based on other constants
2554 def : Pat<(i32 (anyext i1:$in)),
2555 (SELECT_I4 $in, (LI 1), (LI 0))>;
2556 def : Pat<(i64 (anyext i1:$in)),
2557 (SELECT_I8 $in, (LI8 1), (LI8 0))>;
2559 // match setcc on i1 variables.
2560 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)),
2562 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)),
2564 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLE)),
2566 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULE)),
2568 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)),
2570 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGE)),
2572 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)),
2574 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGT)),
2576 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)),
2578 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETNE)),
2581 // match setcc on non-i1 (non-vector) variables. Note that SETUEQ, SETOGE,
2582 // SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for
2583 // floating-point types.
2585 multiclass CRNotPat<dag pattern, dag result> {
2586 def : Pat<pattern, (crnot result)>;
2587 def : Pat<(not pattern), result>;
2589 // We can also fold the crnot into an extension:
2590 def : Pat<(i32 (zext pattern)),
2591 (SELECT_I4 result, (LI 0), (LI 1))>;
2592 def : Pat<(i32 (sext pattern)),
2593 (SELECT_I4 result, (LI 0), (LI -1))>;
2595 // We can also fold the crnot into an extension:
2596 def : Pat<(i64 (zext pattern)),
2597 (SELECT_I8 result, (LI8 0), (LI8 1))>;
2598 def : Pat<(i64 (sext pattern)),
2599 (SELECT_I8 result, (LI8 0), (LI8 -1))>;
2601 // FIXME: We should choose either a zext or a sext based on other constants
2603 def : Pat<(i32 (anyext pattern)),
2604 (SELECT_I4 result, (LI 0), (LI 1))>;
2606 def : Pat<(i64 (anyext pattern)),
2607 (SELECT_I8 result, (LI8 0), (LI8 1))>;
2610 // FIXME: Because of what seems like a bug in TableGen's type-inference code,
2611 // we need to write imm:$imm in the output patterns below, not just $imm, or
2612 // else the resulting matcher will not correctly add the immediate operand
2613 // (making it a register operand instead).
2616 multiclass ExtSetCCPat<CondCode cc, PatFrag pfrag,
2617 OutPatFrag rfrag, OutPatFrag rfrag8> {
2618 def : Pat<(i32 (zext (i1 (pfrag i32:$s1, cc)))),
2620 def : Pat<(i64 (zext (i1 (pfrag i64:$s1, cc)))),
2622 def : Pat<(i64 (zext (i1 (pfrag i32:$s1, cc)))),
2623 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;
2624 def : Pat<(i32 (zext (i1 (pfrag i64:$s1, cc)))),
2625 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
2627 def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, cc)))),
2629 def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, cc)))),
2631 def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, cc)))),
2632 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;
2633 def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, cc)))),
2634 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
2637 // Note that we do all inversions below with i(32|64)not, instead of using
2638 // (xori x, 1) because on the A2 nor has single-cycle latency while xori
2639 // has 2-cycle latency.
2641 defm : ExtSetCCPat<SETEQ,
2642 PatFrag<(ops node:$in, node:$cc),
2643 (setcc $in, 0, $cc)>,
2644 OutPatFrag<(ops node:$in),
2645 (RLWINM (CNTLZW $in), 27, 31, 31)>,
2646 OutPatFrag<(ops node:$in),
2647 (RLDICL (CNTLZD $in), 58, 63)> >;
2649 defm : ExtSetCCPat<SETNE,
2650 PatFrag<(ops node:$in, node:$cc),
2651 (setcc $in, 0, $cc)>,
2652 OutPatFrag<(ops node:$in),
2653 (RLWINM (i32not (CNTLZW $in)), 27, 31, 31)>,
2654 OutPatFrag<(ops node:$in),
2655 (RLDICL (i64not (CNTLZD $in)), 58, 63)> >;
2657 defm : ExtSetCCPat<SETLT,
2658 PatFrag<(ops node:$in, node:$cc),
2659 (setcc $in, 0, $cc)>,
2660 OutPatFrag<(ops node:$in),
2661 (RLWINM $in, 1, 31, 31)>,
2662 OutPatFrag<(ops node:$in),
2663 (RLDICL $in, 1, 63)> >;
2665 defm : ExtSetCCPat<SETGE,
2666 PatFrag<(ops node:$in, node:$cc),
2667 (setcc $in, 0, $cc)>,
2668 OutPatFrag<(ops node:$in),
2669 (RLWINM (i32not $in), 1, 31, 31)>,
2670 OutPatFrag<(ops node:$in),
2671 (RLDICL (i64not $in), 1, 63)> >;
2673 defm : ExtSetCCPat<SETGT,
2674 PatFrag<(ops node:$in, node:$cc),
2675 (setcc $in, 0, $cc)>,
2676 OutPatFrag<(ops node:$in),
2677 (RLWINM (ANDC (NEG $in), $in), 1, 31, 31)>,
2678 OutPatFrag<(ops node:$in),
2679 (RLDICL (ANDC8 (NEG8 $in), $in), 1, 63)> >;
2681 defm : ExtSetCCPat<SETLE,
2682 PatFrag<(ops node:$in, node:$cc),
2683 (setcc $in, 0, $cc)>,
2684 OutPatFrag<(ops node:$in),
2685 (RLWINM (ORC $in, (NEG $in)), 1, 31, 31)>,
2686 OutPatFrag<(ops node:$in),
2687 (RLDICL (ORC8 $in, (NEG8 $in)), 1, 63)> >;
2689 defm : ExtSetCCPat<SETLT,
2690 PatFrag<(ops node:$in, node:$cc),
2691 (setcc $in, -1, $cc)>,
2692 OutPatFrag<(ops node:$in),
2693 (RLWINM (AND $in, (ADDI $in, 1)), 1, 31, 31)>,
2694 OutPatFrag<(ops node:$in),
2695 (RLDICL (AND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
2697 defm : ExtSetCCPat<SETGE,
2698 PatFrag<(ops node:$in, node:$cc),
2699 (setcc $in, -1, $cc)>,
2700 OutPatFrag<(ops node:$in),
2701 (RLWINM (NAND $in, (ADDI $in, 1)), 1, 31, 31)>,
2702 OutPatFrag<(ops node:$in),
2703 (RLDICL (NAND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
2705 defm : ExtSetCCPat<SETGT,
2706 PatFrag<(ops node:$in, node:$cc),
2707 (setcc $in, -1, $cc)>,
2708 OutPatFrag<(ops node:$in),
2709 (RLWINM (i32not $in), 1, 31, 31)>,
2710 OutPatFrag<(ops node:$in),
2711 (RLDICL (i64not $in), 1, 63)> >;
2713 defm : ExtSetCCPat<SETLE,
2714 PatFrag<(ops node:$in, node:$cc),
2715 (setcc $in, -1, $cc)>,
2716 OutPatFrag<(ops node:$in),
2717 (RLWINM $in, 1, 31, 31)>,
2718 OutPatFrag<(ops node:$in),
2719 (RLDICL $in, 1, 63)> >;
2722 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULT)),
2723 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
2724 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLT)),
2725 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;
2726 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGT)),
2727 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;
2728 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGT)),
2729 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;
2730 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETEQ)),
2731 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;
2732 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETEQ)),
2733 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;
2735 // For non-equality comparisons, the default code would materialize the
2736 // constant, then compare against it, like this:
2738 // ori r2, r2, 22136
2741 // Since we are just comparing for equality, we can emit this instead:
2742 // xoris r0,r3,0x1234
2743 // cmplwi cr0,r0,0x5678
2746 def : Pat<(i1 (setcc i32:$s1, imm:$imm, SETEQ)),
2747 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
2748 (LO16 imm:$imm)), sub_eq)>;
2750 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGE)),
2751 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
2752 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGE)),
2753 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;
2754 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULE)),
2755 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;
2756 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLE)),
2757 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;
2758 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETNE)),
2759 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;
2760 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETNE)),
2761 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;
2763 defm : CRNotPat<(i1 (setcc i32:$s1, imm:$imm, SETNE)),
2764 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
2765 (LO16 imm:$imm)), sub_eq)>;
2767 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETULT)),
2768 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>;
2769 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETLT)),
2770 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>;
2771 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETUGT)),
2772 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>;
2773 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETGT)),
2774 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>;
2775 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETEQ)),
2776 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>;
2778 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETUGE)),
2779 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>;
2780 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETGE)),
2781 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>;
2782 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETULE)),
2783 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>;
2784 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETLE)),
2785 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>;
2786 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETNE)),
2787 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>;
2790 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULT)),
2791 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>;
2792 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLT)),
2793 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>;
2794 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGT)),
2795 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>;
2796 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGT)),
2797 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>;
2798 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETEQ)),
2799 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>;
2800 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETEQ)),
2801 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>;
2803 // For non-equality comparisons, the default code would materialize the
2804 // constant, then compare against it, like this:
2806 // ori r2, r2, 22136
2809 // Since we are just comparing for equality, we can emit this instead:
2810 // xoris r0,r3,0x1234
2811 // cmpldi cr0,r0,0x5678
2814 def : Pat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETEQ)),
2815 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
2816 (LO16 imm:$imm)), sub_eq)>;
2818 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGE)),
2819 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>;
2820 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGE)),
2821 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>;
2822 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULE)),
2823 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>;
2824 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLE)),
2825 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>;
2826 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETNE)),
2827 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>;
2828 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETNE)),
2829 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>;
2831 defm : CRNotPat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)),
2832 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
2833 (LO16 imm:$imm)), sub_eq)>;
2835 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETULT)),
2836 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>;
2837 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETLT)),
2838 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>;
2839 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETUGT)),
2840 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;
2841 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETGT)),
2842 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
2843 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETEQ)),
2844 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
2846 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETUGE)),
2847 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>;
2848 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETGE)),
2849 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>;
2850 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETULE)),
2851 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;
2852 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETLE)),
2853 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
2854 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETNE)),
2855 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
2858 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOLT)),
2859 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
2860 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETLT)),
2861 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
2862 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOGT)),
2863 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
2864 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETGT)),
2865 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
2866 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOEQ)),
2867 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
2868 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETEQ)),
2869 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
2870 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETUO)),
2871 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>;
2873 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUGE)),
2874 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
2875 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETGE)),
2876 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
2877 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETULE)),
2878 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
2879 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETLE)),
2880 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
2881 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUNE)),
2882 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
2883 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETNE)),
2884 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
2885 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETO)),
2886 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>;
2889 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOLT)),
2890 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
2891 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETLT)),
2892 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
2893 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOGT)),
2894 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
2895 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETGT)),
2896 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
2897 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOEQ)),
2898 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
2899 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETEQ)),
2900 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
2901 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETUO)),
2902 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
2904 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUGE)),
2905 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
2906 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETGE)),
2907 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
2908 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETULE)),
2909 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
2910 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETLE)),
2911 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
2912 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUNE)),
2913 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
2914 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETNE)),
2915 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
2916 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETO)),
2917 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
2919 // match select on i1 variables:
2920 def : Pat<(i1 (select i1:$cond, i1:$tval, i1:$fval)),
2921 (CROR (CRAND $cond , $tval),
2922 (CRAND (crnot $cond), $fval))>;
2924 // match selectcc on i1 variables:
2925 // select (lhs == rhs), tval, fval is:
2926 // ((lhs == rhs) & tval) | (!(lhs == rhs) & fval)
2927 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLT)),
2928 (CROR (CRAND (CRANDC $rhs, $lhs), $tval),
2929 (CRAND (CRORC $lhs, $rhs), $fval))>;
2930 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLE)),
2931 (CROR (CRAND (CRORC $rhs, $lhs), $tval),
2932 (CRAND (CRANDC $lhs, $rhs), $fval))>;
2933 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETEQ)),
2934 (CROR (CRAND (CREQV $lhs, $rhs), $tval),
2935 (CRAND (CRXOR $lhs, $rhs), $fval))>;
2936 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGE)),
2937 (CROR (CRAND (CRORC $lhs, $rhs), $tval),
2938 (CRAND (CRANDC $rhs, $lhs), $fval))>;
2939 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGT)),
2940 (CROR (CRAND (CRANDC $lhs, $rhs), $tval),
2941 (CRAND (CRORC $rhs, $lhs), $fval))>;
2942 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETNE)),
2943 (CROR (CRAND (CREQV $lhs, $rhs), $fval),
2944 (CRAND (CRXOR $lhs, $rhs), $tval))>;
2946 // match selectcc on i1 variables with non-i1 output.
2947 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLT)),
2948 (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>;
2949 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLE)),
2950 (SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>;
2951 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETEQ)),
2952 (SELECT_I4 (CREQV $lhs, $rhs), $tval, $fval)>;
2953 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGE)),
2954 (SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>;
2955 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGT)),
2956 (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>;
2957 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETNE)),
2958 (SELECT_I4 (CRXOR $lhs, $rhs), $tval, $fval)>;
2960 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLT)),
2961 (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>;
2962 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLE)),
2963 (SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>;
2964 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETEQ)),
2965 (SELECT_I8 (CREQV $lhs, $rhs), $tval, $fval)>;
2966 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGE)),
2967 (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>;
2968 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGT)),
2969 (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>;
2970 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETNE)),
2971 (SELECT_I8 (CRXOR $lhs, $rhs), $tval, $fval)>;
2973 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)),
2974 (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>;
2975 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)),
2976 (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>;
2977 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)),
2978 (SELECT_F4 (CREQV $lhs, $rhs), $tval, $fval)>;
2979 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)),
2980 (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>;
2981 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)),
2982 (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>;
2983 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)),
2984 (SELECT_F4 (CRXOR $lhs, $rhs), $tval, $fval)>;
2986 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)),
2987 (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>;
2988 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)),
2989 (SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>;
2990 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)),
2991 (SELECT_F8 (CREQV $lhs, $rhs), $tval, $fval)>;
2992 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)),
2993 (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>;
2994 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)),
2995 (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>;
2996 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)),
2997 (SELECT_F8 (CRXOR $lhs, $rhs), $tval, $fval)>;
2999 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLT)),
3000 (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>;
3001 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLE)),
3002 (SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>;
3003 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETEQ)),
3004 (SELECT_VRRC (CREQV $lhs, $rhs), $tval, $fval)>;
3005 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGE)),
3006 (SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>;
3007 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGT)),
3008 (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>;
3009 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETNE)),
3010 (SELECT_VRRC (CRXOR $lhs, $rhs), $tval, $fval)>;
3012 let usesCustomInserter = 1 in {
3013 def ANDIo_1_EQ_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
3015 [(set i1:$dst, (trunc (not i32:$in)))]>;
3016 def ANDIo_1_GT_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
3018 [(set i1:$dst, (trunc i32:$in))]>;
3020 def ANDIo_1_EQ_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in),
3022 [(set i1:$dst, (trunc (not i64:$in)))]>;
3023 def ANDIo_1_GT_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in),
3025 [(set i1:$dst, (trunc i64:$in))]>;
3028 def : Pat<(i1 (not (trunc i32:$in))),
3029 (ANDIo_1_EQ_BIT $in)>;
3030 def : Pat<(i1 (not (trunc i64:$in))),
3031 (ANDIo_1_EQ_BIT8 $in)>;
3033 //===----------------------------------------------------------------------===//
3034 // PowerPC Instructions used for assembler/disassembler only
3037 def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins),
3038 "isync", IIC_SprISYNC, []>;
3040 def ICBI : XForm_1a<31, 982, (outs), (ins memrr:$src),
3041 "icbi $src", IIC_LdStICBI, []>;
3043 def EIEIO : XForm_24_eieio<31, 854, (outs), (ins),
3044 "eieio", IIC_LdStLoad, []>;
3046 def WAIT : XForm_24_sync<31, 62, (outs), (ins i32imm:$L),
3047 "wait $L", IIC_LdStLoad, []>;
3049 def MBAR : XForm_mbar<31, 854, (outs), (ins u5imm:$MO),
3050 "mbar $MO", IIC_LdStLoad>, Requires<[IsBookE]>;
3052 def MTSR: XForm_sr<31, 210, (outs), (ins gprc:$RS, u4imm:$SR),
3053 "mtsr $SR, $RS", IIC_SprMTSR>;
3055 def MFSR: XForm_sr<31, 595, (outs gprc:$RS), (ins u4imm:$SR),
3056 "mfsr $RS, $SR", IIC_SprMFSR>;
3058 def MTSRIN: XForm_srin<31, 242, (outs), (ins gprc:$RS, gprc:$RB),
3059 "mtsrin $RS, $RB", IIC_SprMTSR>;
3061 def MFSRIN: XForm_srin<31, 659, (outs gprc:$RS), (ins gprc:$RB),
3062 "mfsrin $RS, $RB", IIC_SprMFSR>;
3064 def MTMSR: XForm_mtmsr<31, 146, (outs), (ins gprc:$RS, i32imm:$L),
3065 "mtmsr $RS, $L", IIC_SprMTMSR>;
3067 def MFMSR : XForm_rs<31, 83, (outs gprc:$RT), (ins),
3068 "mfmsr $RT", IIC_SprMFMSR, []>;
3070 def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, i32imm:$L),
3071 "mtmsrd $RS, $L", IIC_SprMTMSRD>;
3073 def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB),
3074 "slbie $RB", IIC_SprSLBIE, []>;
3076 def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RS, gprc:$RB),
3077 "slbmte $RS, $RB", IIC_SprSLBMTE, []>;
3079 def SLBMFEE : XForm_26<31, 915, (outs gprc:$RT), (ins gprc:$RB),
3080 "slbmfee $RT, $RB", IIC_SprSLBMFEE, []>;
3082 def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", IIC_SprSLBIA, []>;
3084 def TLBSYNC : XForm_0<31, 566, (outs), (ins),
3085 "tlbsync", IIC_SprTLBSYNC, []>;
3087 def TLBIEL : XForm_16b<31, 274, (outs), (ins gprc:$RB),
3088 "tlbiel $RB", IIC_SprTLBIEL, []>;
3090 def TLBIE : XForm_26<31, 306, (outs), (ins gprc:$RS, gprc:$RB),
3091 "tlbie $RB,$RS", IIC_SprTLBIE, []>;
3093 def RFI : XForm_0<19, 50, (outs), (ins), "rfi", IIC_BrB, []>,
3094 Requires<[IsBookE]>;
3095 def RFCI : XForm_0<19, 51, (outs), (ins), "rfci", IIC_BrB, []>,
3096 Requires<[IsBookE]>;
3098 //===----------------------------------------------------------------------===//
3099 // PowerPC Assembler Instruction Aliases
3102 // Pseudo-instructions for alternate assembly syntax (never used by codegen).
3103 // These are aliases that require C++ handling to convert to the target
3104 // instruction, while InstAliases can be handled directly by tblgen.
3105 class PPCAsmPseudo<string asm, dag iops>
3107 let Namespace = "PPC";
3108 bit PPC64 = 0; // Default value, override with isPPC64
3110 let OutOperandList = (outs);
3111 let InOperandList = iops;
3113 let AsmString = asm;
3114 let isAsmParserOnly = 1;
3118 def : InstAlias<"sc", (SC 0)>;
3120 def : InstAlias<"sync", (SYNC 0)>, Requires<[IsNotBookE]>;
3121 def : InstAlias<"msync", (SYNC 0)>, Requires<[IsNotBookE]>;
3122 def : InstAlias<"lwsync", (SYNC 1)>, Requires<[IsNotBookE]>;
3123 def : InstAlias<"ptesync", (SYNC 2)>, Requires<[IsNotBookE]>;
3125 def : InstAlias<"wait", (WAIT 0)>;
3126 def : InstAlias<"waitrsv", (WAIT 1)>;
3127 def : InstAlias<"waitimpl", (WAIT 2)>;
3129 def : InstAlias<"mbar", (MBAR 0)>, Requires<[IsBookE]>;
3131 def : InstAlias<"crset $bx", (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
3132 def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
3133 def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
3134 def : InstAlias<"crnot $bx, $by", (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
3136 def : InstAlias<"mtxer $Rx", (MTSPR 1, gprc:$Rx)>;
3137 def : InstAlias<"mfxer $Rx", (MFSPR gprc:$Rx, 1)>;
3139 def : InstAlias<"mtdscr $Rx", (MTSPR 17, gprc:$Rx)>;
3140 def : InstAlias<"mfdscr $Rx", (MFSPR gprc:$Rx, 17)>;
3142 def : InstAlias<"mtdsisr $Rx", (MTSPR 18, gprc:$Rx)>;
3143 def : InstAlias<"mfdsisr $Rx", (MFSPR gprc:$Rx, 18)>;
3145 def : InstAlias<"mtdar $Rx", (MTSPR 19, gprc:$Rx)>;
3146 def : InstAlias<"mfdar $Rx", (MFSPR gprc:$Rx, 19)>;
3148 def : InstAlias<"mtdec $Rx", (MTSPR 22, gprc:$Rx)>;
3149 def : InstAlias<"mfdec $Rx", (MFSPR gprc:$Rx, 22)>;
3151 def : InstAlias<"mtsdr1 $Rx", (MTSPR 25, gprc:$Rx)>;
3152 def : InstAlias<"mfsdr1 $Rx", (MFSPR gprc:$Rx, 25)>;
3154 def : InstAlias<"mtsrr0 $Rx", (MTSPR 26, gprc:$Rx)>;
3155 def : InstAlias<"mfsrr0 $Rx", (MFSPR gprc:$Rx, 26)>;
3157 def : InstAlias<"mtsrr1 $Rx", (MTSPR 27, gprc:$Rx)>;
3158 def : InstAlias<"mfsrr1 $Rx", (MFSPR gprc:$Rx, 27)>;
3160 def : InstAlias<"mtcfar $Rx", (MTSPR 28, gprc:$Rx)>;
3161 def : InstAlias<"mfcfar $Rx", (MFSPR gprc:$Rx, 28)>;
3163 def : InstAlias<"mtamr $Rx", (MTSPR 29, gprc:$Rx)>;
3164 def : InstAlias<"mfamr $Rx", (MFSPR gprc:$Rx, 29)>;
3166 def : InstAlias<"mftb $Rx", (MFTB gprc:$Rx, 268)>;
3167 def : InstAlias<"mftbu $Rx", (MFTB gprc:$Rx, 269)>;
3169 def : InstAlias<"xnop", (XORI R0, R0, 0)>;
3171 def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3172 def : InstAlias<"mr. $rA, $rB", (OR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3174 def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3175 def : InstAlias<"not. $rA, $rB", (NOR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3177 def : InstAlias<"mtcr $rA", (MTCRF8 255, g8rc:$rA)>;
3179 def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>;
3181 def SUBI : PPCAsmPseudo<"subi $rA, $rB, $imm",
3182 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3183 def SUBIS : PPCAsmPseudo<"subis $rA, $rB, $imm",
3184 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3185 def SUBIC : PPCAsmPseudo<"subic $rA, $rB, $imm",
3186 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3187 def SUBICo : PPCAsmPseudo<"subic. $rA, $rB, $imm",
3188 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3190 def : InstAlias<"sub $rA, $rB, $rC", (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3191 def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3192 def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3193 def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3195 def : InstAlias<"mtmsrd $RS", (MTMSRD gprc:$RS, 0)>;
3196 def : InstAlias<"mtmsr $RS", (MTMSR gprc:$RS, 0)>;
3198 def : InstAlias<"mfsprg $RT, 0", (MFSPR gprc:$RT, 272)>;
3199 def : InstAlias<"mfsprg $RT, 1", (MFSPR gprc:$RT, 273)>;
3200 def : InstAlias<"mfsprg $RT, 2", (MFSPR gprc:$RT, 274)>;
3201 def : InstAlias<"mfsprg $RT, 3", (MFSPR gprc:$RT, 275)>;
3202 def : InstAlias<"mfsprg $RT, 4", (MFSPR gprc:$RT, 260)>, Requires<[IsBookE]>;
3203 def : InstAlias<"mfsprg $RT, 5", (MFSPR gprc:$RT, 261)>, Requires<[IsBookE]>;
3204 def : InstAlias<"mfsprg $RT, 6", (MFSPR gprc:$RT, 262)>, Requires<[IsBookE]>;
3205 def : InstAlias<"mfsprg $RT, 7", (MFSPR gprc:$RT, 263)>, Requires<[IsBookE]>;
3207 def : InstAlias<"mfsprg0 $RT", (MFSPR gprc:$RT, 272)>;
3208 def : InstAlias<"mfsprg1 $RT", (MFSPR gprc:$RT, 273)>;
3209 def : InstAlias<"mfsprg2 $RT", (MFSPR gprc:$RT, 274)>;
3210 def : InstAlias<"mfsprg3 $RT", (MFSPR gprc:$RT, 275)>;
3211 def : InstAlias<"mfsprg4 $RT", (MFSPR gprc:$RT, 260)>, Requires<[IsBookE]>;
3212 def : InstAlias<"mfsprg5 $RT", (MFSPR gprc:$RT, 261)>, Requires<[IsBookE]>;
3213 def : InstAlias<"mfsprg6 $RT", (MFSPR gprc:$RT, 262)>, Requires<[IsBookE]>;
3214 def : InstAlias<"mfsprg7 $RT", (MFSPR gprc:$RT, 263)>, Requires<[IsBookE]>;
3216 def : InstAlias<"mtsprg 0, $RT", (MTSPR 272, gprc:$RT)>;
3217 def : InstAlias<"mtsprg 1, $RT", (MTSPR 273, gprc:$RT)>;
3218 def : InstAlias<"mtsprg 2, $RT", (MTSPR 274, gprc:$RT)>;
3219 def : InstAlias<"mtsprg 3, $RT", (MTSPR 275, gprc:$RT)>;
3220 def : InstAlias<"mtsprg 4, $RT", (MTSPR 260, gprc:$RT)>, Requires<[IsBookE]>;
3221 def : InstAlias<"mtsprg 5, $RT", (MTSPR 261, gprc:$RT)>, Requires<[IsBookE]>;
3222 def : InstAlias<"mtsprg 6, $RT", (MTSPR 262, gprc:$RT)>, Requires<[IsBookE]>;
3223 def : InstAlias<"mtsprg 7, $RT", (MTSPR 263, gprc:$RT)>, Requires<[IsBookE]>;
3225 def : InstAlias<"mtsprg0 $RT", (MTSPR 272, gprc:$RT)>;
3226 def : InstAlias<"mtsprg1 $RT", (MTSPR 273, gprc:$RT)>;
3227 def : InstAlias<"mtsprg2 $RT", (MTSPR 274, gprc:$RT)>;
3228 def : InstAlias<"mtsprg3 $RT", (MTSPR 275, gprc:$RT)>;
3229 def : InstAlias<"mtsprg4 $RT", (MTSPR 260, gprc:$RT)>, Requires<[IsBookE]>;
3230 def : InstAlias<"mtsprg5 $RT", (MTSPR 261, gprc:$RT)>, Requires<[IsBookE]>;
3231 def : InstAlias<"mtsprg6 $RT", (MTSPR 262, gprc:$RT)>, Requires<[IsBookE]>;
3232 def : InstAlias<"mtsprg7 $RT", (MTSPR 263, gprc:$RT)>, Requires<[IsBookE]>;
3234 def : InstAlias<"mtasr $RS", (MTSPR 280, gprc:$RS)>;
3236 def : InstAlias<"mfdec $RT", (MFSPR gprc:$RT, 22)>;
3237 def : InstAlias<"mtdec $RT", (MTSPR 22, gprc:$RT)>;
3239 def : InstAlias<"mfpvr $RT", (MFSPR gprc:$RT, 287)>;
3241 def : InstAlias<"mfsdr1 $RT", (MFSPR gprc:$RT, 25)>;
3242 def : InstAlias<"mtsdr1 $RT", (MTSPR 25, gprc:$RT)>;
3244 def : InstAlias<"mfsrr0 $RT", (MFSPR gprc:$RT, 26)>;
3245 def : InstAlias<"mfsrr1 $RT", (MFSPR gprc:$RT, 27)>;
3246 def : InstAlias<"mtsrr0 $RT", (MTSPR 26, gprc:$RT)>;
3247 def : InstAlias<"mtsrr1 $RT", (MTSPR 27, gprc:$RT)>;
3249 def : InstAlias<"tlbie $RB", (TLBIE R0, gprc:$RB)>;
3251 def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b",
3252 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3253 def EXTLWIo : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b",
3254 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3255 def EXTRWI : PPCAsmPseudo<"extrwi $rA, $rS, $n, $b",
3256 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3257 def EXTRWIo : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b",
3258 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3259 def INSLWI : PPCAsmPseudo<"inslwi $rA, $rS, $n, $b",
3260 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3261 def INSLWIo : PPCAsmPseudo<"inslwi. $rA, $rS, $n, $b",
3262 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3263 def INSRWI : PPCAsmPseudo<"insrwi $rA, $rS, $n, $b",
3264 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3265 def INSRWIo : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b",
3266 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3267 def ROTRWI : PPCAsmPseudo<"rotrwi $rA, $rS, $n",
3268 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3269 def ROTRWIo : PPCAsmPseudo<"rotrwi. $rA, $rS, $n",
3270 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3271 def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n",
3272 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3273 def SLWIo : PPCAsmPseudo<"slwi. $rA, $rS, $n",
3274 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3275 def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n",
3276 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3277 def SRWIo : PPCAsmPseudo<"srwi. $rA, $rS, $n",
3278 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3279 def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n",
3280 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3281 def CLRRWIo : PPCAsmPseudo<"clrrwi. $rA, $rS, $n",
3282 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3283 def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n",
3284 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
3285 def CLRLSLWIo : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n",
3286 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
3288 def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
3289 def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
3290 def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
3291 def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNMo gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
3292 def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
3293 def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
3295 def EXTLDI : PPCAsmPseudo<"extldi $rA, $rS, $n, $b",
3296 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3297 def EXTLDIo : PPCAsmPseudo<"extldi. $rA, $rS, $n, $b",
3298 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3299 def EXTRDI : PPCAsmPseudo<"extrdi $rA, $rS, $n, $b",
3300 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3301 def EXTRDIo : PPCAsmPseudo<"extrdi. $rA, $rS, $n, $b",
3302 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3303 def INSRDI : PPCAsmPseudo<"insrdi $rA, $rS, $n, $b",
3304 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3305 def INSRDIo : PPCAsmPseudo<"insrdi. $rA, $rS, $n, $b",
3306 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3307 def ROTRDI : PPCAsmPseudo<"rotrdi $rA, $rS, $n",
3308 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3309 def ROTRDIo : PPCAsmPseudo<"rotrdi. $rA, $rS, $n",
3310 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3311 def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n",
3312 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3313 def SLDIo : PPCAsmPseudo<"sldi. $rA, $rS, $n",
3314 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3315 def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n",
3316 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3317 def SRDIo : PPCAsmPseudo<"srdi. $rA, $rS, $n",
3318 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3319 def CLRRDI : PPCAsmPseudo<"clrrdi $rA, $rS, $n",
3320 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3321 def CLRRDIo : PPCAsmPseudo<"clrrdi. $rA, $rS, $n",
3322 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3323 def CLRLSLDI : PPCAsmPseudo<"clrlsldi $rA, $rS, $b, $n",
3324 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
3325 def CLRLSLDIo : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n",
3326 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
3328 def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
3329 def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
3330 def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
3331 def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCLo g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
3332 def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
3333 def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
3335 // These generic branch instruction forms are used for the assembler parser only.
3336 // Defs and Uses are conservative, since we don't know the BO value.
3337 let PPC970_Unit = 7 in {
3338 let Defs = [CTR], Uses = [CTR, RM] in {
3339 def gBC : BForm_3<16, 0, 0, (outs),
3340 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
3341 "bc $bo, $bi, $dst">;
3342 def gBCA : BForm_3<16, 1, 0, (outs),
3343 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
3344 "bca $bo, $bi, $dst">;
3346 let Defs = [LR, CTR], Uses = [CTR, RM] in {
3347 def gBCL : BForm_3<16, 0, 1, (outs),
3348 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
3349 "bcl $bo, $bi, $dst">;
3350 def gBCLA : BForm_3<16, 1, 1, (outs),
3351 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
3352 "bcla $bo, $bi, $dst">;
3354 let Defs = [CTR], Uses = [CTR, LR, RM] in
3355 def gBCLR : XLForm_2<19, 16, 0, (outs),
3356 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3357 "bclr $bo, $bi, $bh", IIC_BrB, []>;
3358 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
3359 def gBCLRL : XLForm_2<19, 16, 1, (outs),
3360 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3361 "bclrl $bo, $bi, $bh", IIC_BrB, []>;
3362 let Defs = [CTR], Uses = [CTR, LR, RM] in
3363 def gBCCTR : XLForm_2<19, 528, 0, (outs),
3364 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3365 "bcctr $bo, $bi, $bh", IIC_BrB, []>;
3366 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
3367 def gBCCTRL : XLForm_2<19, 528, 1, (outs),
3368 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3369 "bcctrl $bo, $bi, $bh", IIC_BrB, []>;
3371 def : InstAlias<"bclr $bo, $bi", (gBCLR u5imm:$bo, crbitrc:$bi, 0)>;
3372 def : InstAlias<"bclrl $bo, $bi", (gBCLRL u5imm:$bo, crbitrc:$bi, 0)>;
3373 def : InstAlias<"bcctr $bo, $bi", (gBCCTR u5imm:$bo, crbitrc:$bi, 0)>;
3374 def : InstAlias<"bcctrl $bo, $bi", (gBCCTRL u5imm:$bo, crbitrc:$bi, 0)>;
3376 multiclass BranchSimpleMnemonic1<string name, string pm, int bo> {
3377 def : InstAlias<"b"#name#pm#" $bi, $dst", (gBC bo, crbitrc:$bi, condbrtarget:$dst)>;
3378 def : InstAlias<"b"#name#"a"#pm#" $bi, $dst", (gBCA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
3379 def : InstAlias<"b"#name#"lr"#pm#" $bi", (gBCLR bo, crbitrc:$bi, 0)>;
3380 def : InstAlias<"b"#name#"l"#pm#" $bi, $dst", (gBCL bo, crbitrc:$bi, condbrtarget:$dst)>;
3381 def : InstAlias<"b"#name#"la"#pm#" $bi, $dst", (gBCLA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
3382 def : InstAlias<"b"#name#"lrl"#pm#" $bi", (gBCLRL bo, crbitrc:$bi, 0)>;
3384 multiclass BranchSimpleMnemonic2<string name, string pm, int bo>
3385 : BranchSimpleMnemonic1<name, pm, bo> {
3386 def : InstAlias<"b"#name#"ctr"#pm#" $bi", (gBCCTR bo, crbitrc:$bi, 0)>;
3387 def : InstAlias<"b"#name#"ctrl"#pm#" $bi", (gBCCTRL bo, crbitrc:$bi, 0)>;
3389 defm : BranchSimpleMnemonic2<"t", "", 12>;
3390 defm : BranchSimpleMnemonic2<"f", "", 4>;
3391 defm : BranchSimpleMnemonic2<"t", "-", 14>;
3392 defm : BranchSimpleMnemonic2<"f", "-", 6>;
3393 defm : BranchSimpleMnemonic2<"t", "+", 15>;
3394 defm : BranchSimpleMnemonic2<"f", "+", 7>;
3395 defm : BranchSimpleMnemonic1<"dnzt", "", 8>;
3396 defm : BranchSimpleMnemonic1<"dnzf", "", 0>;
3397 defm : BranchSimpleMnemonic1<"dzt", "", 10>;
3398 defm : BranchSimpleMnemonic1<"dzf", "", 2>;
3400 multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> {
3401 def : InstAlias<"b"#name#pm#" $cc, $dst",
3402 (BCC bibo, crrc:$cc, condbrtarget:$dst)>;
3403 def : InstAlias<"b"#name#pm#" $dst",
3404 (BCC bibo, CR0, condbrtarget:$dst)>;
3406 def : InstAlias<"b"#name#"a"#pm#" $cc, $dst",
3407 (BCCA bibo, crrc:$cc, abscondbrtarget:$dst)>;
3408 def : InstAlias<"b"#name#"a"#pm#" $dst",
3409 (BCCA bibo, CR0, abscondbrtarget:$dst)>;
3411 def : InstAlias<"b"#name#"lr"#pm#" $cc",
3412 (BCCLR bibo, crrc:$cc)>;
3413 def : InstAlias<"b"#name#"lr"#pm,
3416 def : InstAlias<"b"#name#"ctr"#pm#" $cc",
3417 (BCCCTR bibo, crrc:$cc)>;
3418 def : InstAlias<"b"#name#"ctr"#pm,
3419 (BCCCTR bibo, CR0)>;
3421 def : InstAlias<"b"#name#"l"#pm#" $cc, $dst",
3422 (BCCL bibo, crrc:$cc, condbrtarget:$dst)>;
3423 def : InstAlias<"b"#name#"l"#pm#" $dst",
3424 (BCCL bibo, CR0, condbrtarget:$dst)>;
3426 def : InstAlias<"b"#name#"la"#pm#" $cc, $dst",
3427 (BCCLA bibo, crrc:$cc, abscondbrtarget:$dst)>;
3428 def : InstAlias<"b"#name#"la"#pm#" $dst",
3429 (BCCLA bibo, CR0, abscondbrtarget:$dst)>;
3431 def : InstAlias<"b"#name#"lrl"#pm#" $cc",
3432 (BCCLRL bibo, crrc:$cc)>;
3433 def : InstAlias<"b"#name#"lrl"#pm,
3434 (BCCLRL bibo, CR0)>;
3436 def : InstAlias<"b"#name#"ctrl"#pm#" $cc",
3437 (BCCCTRL bibo, crrc:$cc)>;
3438 def : InstAlias<"b"#name#"ctrl"#pm,
3439 (BCCCTRL bibo, CR0)>;
3441 multiclass BranchExtendedMnemonic<string name, int bibo> {
3442 defm : BranchExtendedMnemonicPM<name, "", bibo>;
3443 defm : BranchExtendedMnemonicPM<name, "-", !add(bibo, 2)>;
3444 defm : BranchExtendedMnemonicPM<name, "+", !add(bibo, 3)>;
3446 defm : BranchExtendedMnemonic<"lt", 12>;
3447 defm : BranchExtendedMnemonic<"gt", 44>;
3448 defm : BranchExtendedMnemonic<"eq", 76>;
3449 defm : BranchExtendedMnemonic<"un", 108>;
3450 defm : BranchExtendedMnemonic<"so", 108>;
3451 defm : BranchExtendedMnemonic<"ge", 4>;
3452 defm : BranchExtendedMnemonic<"nl", 4>;
3453 defm : BranchExtendedMnemonic<"le", 36>;
3454 defm : BranchExtendedMnemonic<"ng", 36>;
3455 defm : BranchExtendedMnemonic<"ne", 68>;
3456 defm : BranchExtendedMnemonic<"nu", 100>;
3457 defm : BranchExtendedMnemonic<"ns", 100>;
3459 def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>;
3460 def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>;
3461 def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>;
3462 def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>;
3463 def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm64:$imm)>;
3464 def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>;
3465 def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm64:$imm)>;
3466 def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>;
3468 def : InstAlias<"cmpi $bf, 0, $rA, $imm", (CMPWI crrc:$bf, gprc:$rA, s16imm:$imm)>;
3469 def : InstAlias<"cmp $bf, 0, $rA, $rB", (CMPW crrc:$bf, gprc:$rA, gprc:$rB)>;
3470 def : InstAlias<"cmpli $bf, 0, $rA, $imm", (CMPLWI crrc:$bf, gprc:$rA, u16imm:$imm)>;
3471 def : InstAlias<"cmpl $bf, 0, $rA, $rB", (CMPLW crrc:$bf, gprc:$rA, gprc:$rB)>;
3472 def : InstAlias<"cmpi $bf, 1, $rA, $imm", (CMPDI crrc:$bf, g8rc:$rA, s16imm64:$imm)>;
3473 def : InstAlias<"cmp $bf, 1, $rA, $rB", (CMPD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
3474 def : InstAlias<"cmpli $bf, 1, $rA, $imm", (CMPLDI crrc:$bf, g8rc:$rA, u16imm64:$imm)>;
3475 def : InstAlias<"cmpl $bf, 1, $rA, $rB", (CMPLD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
3477 multiclass TrapExtendedMnemonic<string name, int to> {
3478 def : InstAlias<"td"#name#"i $rA, $imm", (TDI to, g8rc:$rA, s16imm:$imm)>;
3479 def : InstAlias<"td"#name#" $rA, $rB", (TD to, g8rc:$rA, g8rc:$rB)>;
3480 def : InstAlias<"tw"#name#"i $rA, $imm", (TWI to, gprc:$rA, s16imm:$imm)>;
3481 def : InstAlias<"tw"#name#" $rA, $rB", (TW to, gprc:$rA, gprc:$rB)>;
3483 defm : TrapExtendedMnemonic<"lt", 16>;
3484 defm : TrapExtendedMnemonic<"le", 20>;
3485 defm : TrapExtendedMnemonic<"eq", 4>;
3486 defm : TrapExtendedMnemonic<"ge", 12>;
3487 defm : TrapExtendedMnemonic<"gt", 8>;
3488 defm : TrapExtendedMnemonic<"nl", 12>;
3489 defm : TrapExtendedMnemonic<"ne", 24>;
3490 defm : TrapExtendedMnemonic<"ng", 20>;
3491 defm : TrapExtendedMnemonic<"llt", 2>;
3492 defm : TrapExtendedMnemonic<"lle", 6>;
3493 defm : TrapExtendedMnemonic<"lge", 5>;
3494 defm : TrapExtendedMnemonic<"lgt", 1>;
3495 defm : TrapExtendedMnemonic<"lnl", 5>;
3496 defm : TrapExtendedMnemonic<"lng", 6>;
3497 defm : TrapExtendedMnemonic<"u", 31>;