1 //===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPCShiftOp : SDTypeProfile<1, 2, [ // PPCshl, PPCsra, PPCsrl
24 SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32>
26 def SDT_PPCCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
27 def SDT_PPCRetFlag : SDTypeProfile<0, 0, []>;
29 //===----------------------------------------------------------------------===//
30 // PowerPC specific DAG Nodes.
33 def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>;
34 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
35 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
36 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx, [SDNPHasChain]>;
38 def PPCfsel : SDNode<"PPCISD::FSEL",
39 // Type constraint for fsel.
40 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
41 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
43 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
44 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
45 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
46 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
48 def PPClve_x : SDNode<"PPCISD::LVE_X", SDTLoad, [SDNPHasChain]>;
50 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
51 // amounts. These nodes are generated by the multi-precision shift code.
52 def PPCsrl : SDNode<"PPCISD::SRL" , SDT_PPCShiftOp>;
53 def PPCsra : SDNode<"PPCISD::SRA" , SDT_PPCShiftOp>;
54 def PPCshl : SDNode<"PPCISD::SHL" , SDT_PPCShiftOp>;
56 // These are target-independent nodes, but have target-specific formats.
57 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeq,[SDNPHasChain]>;
58 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeq,[SDNPHasChain]>;
60 def retflag : SDNode<"PPCISD::RET_FLAG", SDT_PPCRetFlag,
61 [SDNPHasChain, SDNPOptInFlag]>;
63 //===----------------------------------------------------------------------===//
64 // PowerPC specific transformation functions and pattern fragments.
67 def SHL32 : SDNodeXForm<imm, [{
68 // Transformation function: 31 - imm
69 return getI32Imm(31 - N->getValue());
72 def SHL64 : SDNodeXForm<imm, [{
73 // Transformation function: 63 - imm
74 return getI32Imm(63 - N->getValue());
77 def SRL32 : SDNodeXForm<imm, [{
78 // Transformation function: 32 - imm
79 return N->getValue() ? getI32Imm(32 - N->getValue()) : getI32Imm(0);
82 def SRL64 : SDNodeXForm<imm, [{
83 // Transformation function: 64 - imm
84 return N->getValue() ? getI32Imm(64 - N->getValue()) : getI32Imm(0);
87 def LO16 : SDNodeXForm<imm, [{
88 // Transformation function: get the low 16 bits.
89 return getI32Imm((unsigned short)N->getValue());
92 def HI16 : SDNodeXForm<imm, [{
93 // Transformation function: shift the immediate value down into the low bits.
94 return getI32Imm((unsigned)N->getValue() >> 16);
97 def HA16 : SDNodeXForm<imm, [{
98 // Transformation function: shift the immediate value down into the low bits.
99 signed int Val = N->getValue();
100 return getI32Imm((Val - (signed short)Val) >> 16);
104 def immSExt16 : PatLeaf<(imm), [{
105 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
106 // field. Used by instructions like 'addi'.
107 return (int)N->getValue() == (short)N->getValue();
109 def immZExt16 : PatLeaf<(imm), [{
110 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
111 // field. Used by instructions like 'ori'.
112 return (unsigned)N->getValue() == (unsigned short)N->getValue();
115 def imm16Shifted : PatLeaf<(imm), [{
116 // imm16Shifted predicate - True if only bits in the top 16-bits of the
117 // immediate are set. Used by instructions like 'addis'.
118 return ((unsigned)N->getValue() & 0xFFFF0000U) == (unsigned)N->getValue();
122 // Example of a legalize expander: Only for PPC64.
123 def : Expander<(set i64:$dst, (fp_to_sint f64:$src)),
124 [(set f64:$tmp , (FCTIDZ f64:$src)),
125 (set i32:$tmpFI, (CreateNewFrameIndex 8, 8)),
126 (store f64:$tmp, i32:$tmpFI),
127 (set i64:$dst, (load i32:$tmpFI))],
131 //===----------------------------------------------------------------------===//
132 // PowerPC Flag Definitions.
134 class isPPC64 { bit PPC64 = 1; }
135 class isVMX { bit VMX = 1; }
137 list<Register> Defs = [CR0];
143 //===----------------------------------------------------------------------===//
144 // PowerPC Operand Definitions.
146 def u5imm : Operand<i32> {
147 let PrintMethod = "printU5ImmOperand";
149 def u6imm : Operand<i32> {
150 let PrintMethod = "printU6ImmOperand";
152 def s16imm : Operand<i32> {
153 let PrintMethod = "printS16ImmOperand";
155 def u16imm : Operand<i32> {
156 let PrintMethod = "printU16ImmOperand";
158 def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing.
159 let PrintMethod = "printS16X4ImmOperand";
161 def target : Operand<OtherVT> {
162 let PrintMethod = "printBranchOperand";
164 def calltarget : Operand<i32> {
165 let PrintMethod = "printCallOperand";
167 def aaddr : Operand<i32> {
168 let PrintMethod = "printAbsAddrOperand";
170 def piclabel: Operand<i32> {
171 let PrintMethod = "printPICLabel";
173 def symbolHi: Operand<i32> {
174 let PrintMethod = "printSymbolHi";
176 def symbolLo: Operand<i32> {
177 let PrintMethod = "printSymbolLo";
179 def crbitm: Operand<i8> {
180 let PrintMethod = "printcrbitm";
183 def memri : Operand<i32> {
184 let PrintMethod = "printMemRegImm";
185 let NumMIOperands = 2;
186 let MIOperandInfo = (ops i32imm, GPRC);
188 def memrr : Operand<i32> {
189 let PrintMethod = "printMemRegReg";
190 let NumMIOperands = 2;
191 let MIOperandInfo = (ops GPRC, GPRC);
194 // Define PowerPC specific addressing mode.
195 def iaddr : ComplexPattern<i32, 2, "SelectAddrImm", []>;
196 def xaddr : ComplexPattern<i32, 2, "SelectAddrIdx", []>;
197 def xoaddr : ComplexPattern<i32, 2, "SelectAddrIdxOnly",[]>;
199 //===----------------------------------------------------------------------===//
200 // PowerPC Instruction Predicate Definitions.
201 def FPContractions : Predicate<"!NoExcessFPPrecision">;
203 //===----------------------------------------------------------------------===//
204 // PowerPC Instruction Definitions.
206 // Pseudo-instructions:
208 let hasCtrlDep = 1 in {
209 def ADJCALLSTACKDOWN : Pseudo<(ops u16imm:$amt),
210 "; ADJCALLSTACKDOWN",
211 [(callseq_start imm:$amt)]>;
212 def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt),
214 [(callseq_end imm:$amt)]>;
216 def UPDATE_VRSAVE : Pseudo<(ops GPRC:$rD, GPRC:$rS),
217 "UPDATE_VRSAVE $rD, $rS", []>;
219 def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC",
220 [(set GPRC:$rD, (undef))]>;
221 def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "; $rD = IMPLICIT_DEF_F8",
222 [(set F8RC:$rD, (undef))]>;
223 def IMPLICIT_DEF_F4 : Pseudo<(ops F4RC:$rD), "; $rD = IMPLICIT_DEF_F4",
224 [(set F4RC:$rD, (undef))]>;
225 def IMPLICIT_DEF_VRRC : Pseudo<(ops VRRC:$rD), "; $rD = IMPLICIT_DEF_VRRC",
226 [(set VRRC:$rD, (v4f32 (undef)))]>;
228 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
229 // scheduler into a branch sequence.
230 let usesCustomDAGSchedInserter = 1, // Expanded by the scheduler.
231 PPC970_Single = 1 in {
232 def SELECT_CC_Int : Pseudo<(ops GPRC:$dst, CRRC:$cond, GPRC:$T, GPRC:$F,
233 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
234 def SELECT_CC_F4 : Pseudo<(ops F4RC:$dst, CRRC:$cond, F4RC:$T, F4RC:$F,
235 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
236 def SELECT_CC_F8 : Pseudo<(ops F8RC:$dst, CRRC:$cond, F8RC:$T, F8RC:$F,
237 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
240 let isTerminator = 1, noResults = 1, PPC970_Unit = 7 in {
242 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr", BrB, [(retflag)]>;
243 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr", BrB, []>;
247 def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label", []>,
250 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1,
251 noResults = 1, PPC970_Unit = 7 in {
252 def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm:$opc, target:$true),
253 "; COND_BRANCH", []>;
254 def B : IForm<18, 0, 0, (ops target:$dst),
258 // FIXME: 4*CR# needs to be added to the BI field!
259 // This will only work for CR0 as it stands now
260 def BLT : BForm<16, 0, 0, 12, 0, (ops CRRC:$crS, target:$block),
261 "blt $crS, $block", BrB>;
262 def BLE : BForm<16, 0, 0, 4, 1, (ops CRRC:$crS, target:$block),
263 "ble $crS, $block", BrB>;
264 def BEQ : BForm<16, 0, 0, 12, 2, (ops CRRC:$crS, target:$block),
265 "beq $crS, $block", BrB>;
266 def BGE : BForm<16, 0, 0, 4, 0, (ops CRRC:$crS, target:$block),
267 "bge $crS, $block", BrB>;
268 def BGT : BForm<16, 0, 0, 12, 1, (ops CRRC:$crS, target:$block),
269 "bgt $crS, $block", BrB>;
270 def BNE : BForm<16, 0, 0, 4, 2, (ops CRRC:$crS, target:$block),
271 "bne $crS, $block", BrB>;
272 def BUN : BForm<16, 0, 0, 12, 3, (ops CRRC:$crS, target:$block),
273 "bun $crS, $block", BrB>;
274 def BNU : BForm<16, 0, 0, 4, 3, (ops CRRC:$crS, target:$block),
275 "bnu $crS, $block", BrB>;
278 let isCall = 1, noResults = 1, PPC970_Unit = 7,
279 // All calls clobber the non-callee saved registers...
280 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
281 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
282 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
284 CR0,CR1,CR5,CR6,CR7] in {
285 // Convenient aliases for call instructions
286 def BL : IForm<18, 0, 1, (ops calltarget:$func, variable_ops),
287 "bl $func", BrB, []>;
288 def BLA : IForm<18, 1, 1, (ops aaddr:$func, variable_ops),
289 "bla $func", BrB, []>;
290 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (ops variable_ops), "bctrl", BrB,
294 // D-Form instructions. Most instructions that perform an operation on a
295 // register and an immediate are of this type.
297 let isLoad = 1, PPC970_Unit = 2 in {
298 def LBZ : DForm_1<34, (ops GPRC:$rD, memri:$src),
299 "lbz $rD, $src", LdStGeneral,
300 [(set GPRC:$rD, (zextload iaddr:$src, i8))]>;
301 def LHA : DForm_1<42, (ops GPRC:$rD, memri:$src),
302 "lha $rD, $src", LdStLHA,
303 [(set GPRC:$rD, (sextload iaddr:$src, i16))]>,
304 PPC970_DGroup_Cracked;
305 def LHZ : DForm_1<40, (ops GPRC:$rD, memri:$src),
306 "lhz $rD, $src", LdStGeneral,
307 [(set GPRC:$rD, (zextload iaddr:$src, i16))]>;
308 def LWZ : DForm_1<32, (ops GPRC:$rD, memri:$src),
309 "lwz $rD, $src", LdStGeneral,
310 [(set GPRC:$rD, (load iaddr:$src))]>;
311 def LWZU : DForm_1<35, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
312 "lwzu $rD, $disp($rA)", LdStGeneral,
315 let PPC970_Unit = 1 in { // FXU Operations.
316 def ADDI : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
317 "addi $rD, $rA, $imm", IntGeneral,
318 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
319 def ADDIC : DForm_2<12, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
320 "addic $rD, $rA, $imm", IntGeneral,
321 [(set GPRC:$rD, (addc GPRC:$rA, immSExt16:$imm))]>,
322 PPC970_DGroup_Cracked;
323 def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
324 "addic. $rD, $rA, $imm", IntGeneral,
326 def ADDIS : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$imm),
327 "addis $rD, $rA, $imm", IntGeneral,
328 [(set GPRC:$rD, (add GPRC:$rA, imm16Shifted:$imm))]>;
329 def LA : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym),
330 "la $rD, $sym($rA)", IntGeneral,
331 [(set GPRC:$rD, (add GPRC:$rA,
332 (PPClo tglobaladdr:$sym, 0)))]>;
333 def MULLI : DForm_2< 7, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
334 "mulli $rD, $rA, $imm", IntMulLI,
335 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
336 def SUBFIC : DForm_2< 8, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
337 "subfic $rD, $rA, $imm", IntGeneral,
338 [(set GPRC:$rD, (subc immSExt16:$imm, GPRC:$rA))]>;
339 def LI : DForm_2_r0<14, (ops GPRC:$rD, symbolLo:$imm),
340 "li $rD, $imm", IntGeneral,
341 [(set GPRC:$rD, immSExt16:$imm)]>;
342 def LIS : DForm_2_r0<15, (ops GPRC:$rD, symbolHi:$imm),
343 "lis $rD, $imm", IntGeneral,
344 [(set GPRC:$rD, imm16Shifted:$imm)]>;
346 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
347 def STB : DForm_3<38, (ops GPRC:$rS, memri:$src),
348 "stb $rS, $src", LdStGeneral,
349 [(truncstore GPRC:$rS, iaddr:$src, i8)]>;
350 def STH : DForm_3<44, (ops GPRC:$rS, memri:$src),
351 "sth $rS, $src", LdStGeneral,
352 [(truncstore GPRC:$rS, iaddr:$src, i16)]>;
353 def STW : DForm_3<36, (ops GPRC:$rS, memri:$src),
354 "stw $rS, $src", LdStGeneral,
355 [(store GPRC:$rS, iaddr:$src)]>;
356 def STWU : DForm_3<37, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
357 "stwu $rS, $disp($rA)", LdStGeneral,
360 let PPC970_Unit = 1 in { // FXU Operations.
361 def ANDIo : DForm_4<28, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
362 "andi. $dst, $src1, $src2", IntGeneral,
363 [(set GPRC:$dst, (and GPRC:$src1, immZExt16:$src2))]>,
365 def ANDISo : DForm_4<29, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
366 "andis. $dst, $src1, $src2", IntGeneral,
367 [(set GPRC:$dst, (and GPRC:$src1, imm16Shifted:$src2))]>,
369 def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
370 "ori $dst, $src1, $src2", IntGeneral,
371 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
372 def ORIS : DForm_4<25, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
373 "oris $dst, $src1, $src2", IntGeneral,
374 [(set GPRC:$dst, (or GPRC:$src1, imm16Shifted:$src2))]>;
375 def XORI : DForm_4<26, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
376 "xori $dst, $src1, $src2", IntGeneral,
377 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
378 def XORIS : DForm_4<27, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
379 "xoris $dst, $src1, $src2", IntGeneral,
380 [(set GPRC:$dst, (xor GPRC:$src1, imm16Shifted:$src2))]>;
381 def NOP : DForm_4_zero<24, (ops), "nop", IntGeneral,
383 def CMPI : DForm_5<11, (ops CRRC:$crD, i1imm:$L, GPRC:$rA, s16imm:$imm),
384 "cmpi $crD, $L, $rA, $imm", IntCompare>;
385 def CMPWI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
386 "cmpwi $crD, $rA, $imm", IntCompare>;
387 def CMPDI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
388 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64;
389 def CMPLI : DForm_6<10, (ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2),
390 "cmpli $dst, $size, $src1, $src2", IntCompare>;
391 def CMPLWI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
392 "cmplwi $dst, $src1, $src2", IntCompare>;
393 def CMPLDI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
394 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64;
396 let isLoad = 1, PPC970_Unit = 2 in {
397 def LFS : DForm_8<48, (ops F4RC:$rD, memri:$src),
398 "lfs $rD, $src", LdStLFDU,
399 [(set F4RC:$rD, (load iaddr:$src))]>;
400 def LFD : DForm_8<50, (ops F8RC:$rD, memri:$src),
401 "lfd $rD, $src", LdStLFD,
402 [(set F8RC:$rD, (load iaddr:$src))]>;
404 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
405 def STFS : DForm_9<52, (ops F4RC:$rS, memri:$dst),
406 "stfs $rS, $dst", LdStUX,
407 [(store F4RC:$rS, iaddr:$dst)]>;
408 def STFD : DForm_9<54, (ops F8RC:$rS, memri:$dst),
409 "stfd $rS, $dst", LdStUX,
410 [(store F8RC:$rS, iaddr:$dst)]>;
413 // DS-Form instructions. Load/Store instructions available in PPC-64
415 let isLoad = 1, PPC970_Unit = 2 in {
416 def LWA : DSForm_1<58, 2, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
417 "lwa $rT, $DS($rA)", LdStLWA,
418 []>, isPPC64, PPC970_DGroup_Cracked;
419 def LD : DSForm_2<58, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
420 "ld $rT, $DS($rA)", LdStLD,
423 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
424 def STD : DSForm_2<62, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
425 "std $rT, $DS($rA)", LdStSTD,
427 def STDU : DSForm_2<62, 1, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
428 "stdu $rT, $DS($rA)", LdStSTD,
432 // X-Form instructions. Most instructions that perform an operation on a
433 // register and another register are of this type.
435 let isLoad = 1, PPC970_Unit = 2 in {
436 def LBZX : XForm_1<31, 87, (ops GPRC:$rD, memrr:$src),
437 "lbzx $rD, $src", LdStGeneral,
438 [(set GPRC:$rD, (zextload xaddr:$src, i8))]>;
439 def LHAX : XForm_1<31, 343, (ops GPRC:$rD, memrr:$src),
440 "lhax $rD, $src", LdStLHA,
441 [(set GPRC:$rD, (sextload xaddr:$src, i16))]>,
442 PPC970_DGroup_Cracked;
443 def LHZX : XForm_1<31, 279, (ops GPRC:$rD, memrr:$src),
444 "lhzx $rD, $src", LdStGeneral,
445 [(set GPRC:$rD, (zextload xaddr:$src, i16))]>;
446 def LWAX : XForm_1<31, 341, (ops G8RC:$rD, memrr:$src),
447 "lwax $rD, $src", LdStLHA,
448 [(set G8RC:$rD, (sextload xaddr:$src, i32))]>, isPPC64,
449 PPC970_DGroup_Cracked;
450 def LWZX : XForm_1<31, 23, (ops GPRC:$rD, memrr:$src),
451 "lwzx $rD, $src", LdStGeneral,
452 [(set GPRC:$rD, (load xaddr:$src))]>;
453 def LDX : XForm_1<31, 21, (ops G8RC:$rD, memrr:$src),
454 "ldx $rD, $src", LdStLD,
455 [(set G8RC:$rD, (load xaddr:$src))]>, isPPC64;
456 def LVEBX: XForm_1<31, 7, (ops VRRC:$vD, memrr:$src),
457 "lvebx $vD, $src", LdStGeneral,
459 def LVEHX: XForm_1<31, 39, (ops VRRC:$vD, memrr:$src),
460 "lvehx $vD, $src", LdStGeneral,
462 def LVEWX: XForm_1<31, 71, (ops VRRC:$vD, memrr:$src),
463 "lvewx $vD, $src", LdStGeneral,
464 [(set VRRC:$vD, (v4f32 (PPClve_x xoaddr:$src)))]>;
465 def LVX : XForm_1<31, 103, (ops VRRC:$vD, memrr:$src),
466 "lvx $vD, $src", LdStGeneral,
467 [(set VRRC:$vD, (v4f32 (load xoaddr:$src)))]>;
469 def LVSL : XForm_1<31, 6, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
470 "lvsl $vD, $base, $rA", LdStGeneral,
471 []>, PPC970_Unit_LSU;
472 def LVSR : XForm_1<31, 38, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
473 "lvsl $vD, $base, $rA", LdStGeneral,
474 []>, PPC970_Unit_LSU;
475 let PPC970_Unit = 1 in { // FXU Operations.
476 def NAND : XForm_6<31, 476, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
477 "nand $rA, $rS, $rB", IntGeneral,
478 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
479 def AND : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
480 "and $rA, $rS, $rB", IntGeneral,
481 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
482 def ANDo : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
483 "and. $rA, $rS, $rB", IntGeneral,
485 def ANDC : XForm_6<31, 60, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
486 "andc $rA, $rS, $rB", IntGeneral,
487 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
488 def OR4 : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
489 "or $rA, $rS, $rB", IntGeneral,
490 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
491 def OR8 : XForm_6<31, 444, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
492 "or $rA, $rS, $rB", IntGeneral,
493 [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>;
494 def OR4To8 : XForm_6<31, 444, (ops G8RC:$rA, GPRC:$rS, GPRC:$rB),
495 "or $rA, $rS, $rB", IntGeneral,
497 def OR8To4 : XForm_6<31, 444, (ops GPRC:$rA, G8RC:$rS, G8RC:$rB),
498 "or $rA, $rS, $rB", IntGeneral,
500 def NOR : XForm_6<31, 124, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
501 "nor $rA, $rS, $rB", IntGeneral,
502 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
503 def ORo : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
504 "or. $rA, $rS, $rB", IntGeneral,
506 def ORC : XForm_6<31, 412, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
507 "orc $rA, $rS, $rB", IntGeneral,
508 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
509 def EQV : XForm_6<31, 284, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
510 "eqv $rA, $rS, $rB", IntGeneral,
511 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
512 def XOR : XForm_6<31, 316, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
513 "xor $rA, $rS, $rB", IntGeneral,
514 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
515 def SLD : XForm_6<31, 27, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
516 "sld $rA, $rS, $rB", IntRotateD,
517 [(set G8RC:$rA, (shl G8RC:$rS, G8RC:$rB))]>, isPPC64;
518 def SLW : XForm_6<31, 24, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
519 "slw $rA, $rS, $rB", IntGeneral,
520 [(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>;
521 def SRD : XForm_6<31, 539, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
522 "srd $rA, $rS, $rB", IntRotateD,
523 [(set G8RC:$rA, (srl G8RC:$rS, G8RC:$rB))]>, isPPC64;
524 def SRW : XForm_6<31, 536, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
525 "srw $rA, $rS, $rB", IntGeneral,
526 [(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>;
527 def SRAD : XForm_6<31, 794, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
528 "srad $rA, $rS, $rB", IntRotateD,
529 [(set G8RC:$rA, (sra G8RC:$rS, G8RC:$rB))]>, isPPC64;
530 def SRAW : XForm_6<31, 792, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
531 "sraw $rA, $rS, $rB", IntShift,
532 [(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>;
534 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
535 def STBX : XForm_8<31, 215, (ops GPRC:$rS, memrr:$dst),
536 "stbx $rS, $dst", LdStGeneral,
537 [(truncstore GPRC:$rS, xaddr:$dst, i8)]>,
538 PPC970_DGroup_Cracked;
539 def STHX : XForm_8<31, 407, (ops GPRC:$rS, memrr:$dst),
540 "sthx $rS, $dst", LdStGeneral,
541 [(truncstore GPRC:$rS, xaddr:$dst, i16)]>,
542 PPC970_DGroup_Cracked;
543 def STWX : XForm_8<31, 151, (ops GPRC:$rS, memrr:$dst),
544 "stwx $rS, $dst", LdStGeneral,
545 [(store GPRC:$rS, xaddr:$dst)]>,
546 PPC970_DGroup_Cracked;
547 def STWUX : XForm_8<31, 183, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
548 "stwux $rS, $rA, $rB", LdStGeneral,
550 def STDX : XForm_8<31, 149, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
551 "stdx $rS, $rA, $rB", LdStSTD,
552 []>, isPPC64, PPC970_DGroup_Cracked;
553 def STDUX : XForm_8<31, 181, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
554 "stdux $rS, $rA, $rB", LdStSTD,
556 def STVEBX: XForm_8<31, 135, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
557 "stvebx $rS, $rA, $rB", LdStGeneral,
559 def STVEHX: XForm_8<31, 167, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
560 "stvehx $rS, $rA, $rB", LdStGeneral,
562 def STVEWX: XForm_8<31, 199, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
563 "stvewx $rS, $rA, $rB", LdStGeneral,
565 def STVX : XForm_8<31, 231, (ops VRRC:$rS, memrr:$dst),
566 "stvx $rS, $dst", LdStGeneral,
567 [(store (v4f32 VRRC:$rS), xoaddr:$dst)]>;
569 let PPC970_Unit = 1 in { // FXU Operations.
570 def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
571 "srawi $rA, $rS, $SH", IntShift,
572 [(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>;
573 def CNTLZW : XForm_11<31, 26, (ops GPRC:$rA, GPRC:$rS),
574 "cntlzw $rA, $rS", IntGeneral,
575 [(set GPRC:$rA, (ctlz GPRC:$rS))]>;
576 def EXTSB : XForm_11<31, 954, (ops GPRC:$rA, GPRC:$rS),
577 "extsb $rA, $rS", IntGeneral,
578 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
579 def EXTSH : XForm_11<31, 922, (ops GPRC:$rA, GPRC:$rS),
580 "extsh $rA, $rS", IntGeneral,
581 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
582 def EXTSW : XForm_11<31, 986, (ops G8RC:$rA, G8RC:$rS),
583 "extsw $rA, $rS", IntGeneral,
584 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64;
585 def CMP : XForm_16<31, 0, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
586 "cmp $crD, $long, $rA, $rB", IntCompare>;
587 def CMPL : XForm_16<31, 32, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
588 "cmpl $crD, $long, $rA, $rB", IntCompare>;
589 def CMPW : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
590 "cmpw $crD, $rA, $rB", IntCompare>;
591 def CMPD : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
592 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64;
593 def CMPLW : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
594 "cmplw $crD, $rA, $rB", IntCompare>;
595 def CMPLD : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
596 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64;
598 let PPC970_Unit = 3 in { // FPU Operations.
599 //def FCMPO : XForm_17<63, 32, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
600 // "fcmpo $crD, $fA, $fB", FPCompare>;
601 def FCMPUS : XForm_17<63, 0, (ops CRRC:$crD, F4RC:$fA, F4RC:$fB),
602 "fcmpu $crD, $fA, $fB", FPCompare>;
603 def FCMPUD : XForm_17<63, 0, (ops CRRC:$crD, F8RC:$fA, F8RC:$fB),
604 "fcmpu $crD, $fA, $fB", FPCompare>;
606 let isLoad = 1, PPC970_Unit = 2 in {
607 def LFSX : XForm_25<31, 535, (ops F4RC:$frD, memrr:$src),
608 "lfsx $frD, $src", LdStLFDU,
609 [(set F4RC:$frD, (load xaddr:$src))]>;
610 def LFDX : XForm_25<31, 599, (ops F8RC:$frD, memrr:$src),
611 "lfdx $frD, $src", LdStLFDU,
612 [(set F8RC:$frD, (load xaddr:$src))]>;
614 let PPC970_Unit = 3 in { // FPU Operations.
615 def FCFID : XForm_26<63, 846, (ops F8RC:$frD, F8RC:$frB),
616 "fcfid $frD, $frB", FPGeneral,
617 [(set F8RC:$frD, (PPCfcfid F8RC:$frB))]>, isPPC64;
618 def FCTIDZ : XForm_26<63, 815, (ops F8RC:$frD, F8RC:$frB),
619 "fctidz $frD, $frB", FPGeneral,
620 [(set F8RC:$frD, (PPCfctidz F8RC:$frB))]>, isPPC64;
621 def FCTIWZ : XForm_26<63, 15, (ops F8RC:$frD, F8RC:$frB),
622 "fctiwz $frD, $frB", FPGeneral,
623 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>;
624 def FRSP : XForm_26<63, 12, (ops F4RC:$frD, F8RC:$frB),
625 "frsp $frD, $frB", FPGeneral,
626 [(set F4RC:$frD, (fround F8RC:$frB))]>;
627 def FSQRT : XForm_26<63, 22, (ops F8RC:$frD, F8RC:$frB),
628 "fsqrt $frD, $frB", FPSqrt,
629 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>;
630 def FSQRTS : XForm_26<59, 22, (ops F4RC:$frD, F4RC:$frB),
631 "fsqrts $frD, $frB", FPSqrt,
632 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>;
635 /// FMR is split into 3 versions, one for 4/8 byte FP, and one for extending.
637 /// Note that these are defined as pseudo-ops on the PPC970 because they are
638 /// often coallesced away and we don't want the dispatch group builder to think
639 /// that they will fill slots (which could cause the load of a LSU reject to
640 /// sneak into a d-group with a store).
641 def FMRS : XForm_26<63, 72, (ops F4RC:$frD, F4RC:$frB),
642 "fmr $frD, $frB", FPGeneral,
643 []>, // (set F4RC:$frD, F4RC:$frB)
645 def FMRD : XForm_26<63, 72, (ops F8RC:$frD, F8RC:$frB),
646 "fmr $frD, $frB", FPGeneral,
647 []>, // (set F8RC:$frD, F8RC:$frB)
649 def FMRSD : XForm_26<63, 72, (ops F8RC:$frD, F4RC:$frB),
650 "fmr $frD, $frB", FPGeneral,
651 [(set F8RC:$frD, (fextend F4RC:$frB))]>,
654 let PPC970_Unit = 3 in { // FPU Operations.
655 // These are artificially split into two different forms, for 4/8 byte FP.
656 def FABSS : XForm_26<63, 264, (ops F4RC:$frD, F4RC:$frB),
657 "fabs $frD, $frB", FPGeneral,
658 [(set F4RC:$frD, (fabs F4RC:$frB))]>;
659 def FABSD : XForm_26<63, 264, (ops F8RC:$frD, F8RC:$frB),
660 "fabs $frD, $frB", FPGeneral,
661 [(set F8RC:$frD, (fabs F8RC:$frB))]>;
662 def FNABSS : XForm_26<63, 136, (ops F4RC:$frD, F4RC:$frB),
663 "fnabs $frD, $frB", FPGeneral,
664 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>;
665 def FNABSD : XForm_26<63, 136, (ops F8RC:$frD, F8RC:$frB),
666 "fnabs $frD, $frB", FPGeneral,
667 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>;
668 def FNEGS : XForm_26<63, 40, (ops F4RC:$frD, F4RC:$frB),
669 "fneg $frD, $frB", FPGeneral,
670 [(set F4RC:$frD, (fneg F4RC:$frB))]>;
671 def FNEGD : XForm_26<63, 40, (ops F8RC:$frD, F8RC:$frB),
672 "fneg $frD, $frB", FPGeneral,
673 [(set F8RC:$frD, (fneg F8RC:$frB))]>;
676 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
677 def STFIWX: XForm_28<31, 983, (ops F8RC:$frS, memrr:$dst),
678 "stfiwx $frS, $dst", LdStUX,
679 [(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>;
680 def STFSX : XForm_28<31, 663, (ops F4RC:$frS, memrr:$dst),
681 "stfsx $frS, $dst", LdStUX,
682 [(store F4RC:$frS, xaddr:$dst)]>;
683 def STFDX : XForm_28<31, 727, (ops F8RC:$frS, memrr:$dst),
684 "stfdx $frS, $dst", LdStUX,
685 [(store F8RC:$frS, xaddr:$dst)]>;
688 // XL-Form instructions. condition register logical ops.
690 def MCRF : XLForm_3<19, 0, (ops CRRC:$BF, CRRC:$BFA),
691 "mcrf $BF, $BFA", BrMCR>,
692 PPC970_DGroup_First, PPC970_Unit_CRU;
694 // XFX-Form instructions. Instructions that deal with SPRs.
696 def MFCTR : XFXForm_1_ext<31, 339, 9, (ops GPRC:$rT), "mfctr $rT", SprMFSPR>,
697 PPC970_DGroup_First, PPC970_Unit_FXU;
698 def MTCTR : XFXForm_7_ext<31, 467, 9, (ops GPRC:$rS), "mtctr $rS", SprMTSPR>,
699 PPC970_DGroup_First, PPC970_Unit_FXU;
701 def MTLR : XFXForm_7_ext<31, 467, 8, (ops GPRC:$rS), "mtlr $rS", SprMTSPR>,
702 PPC970_DGroup_First, PPC970_Unit_FXU;
703 def MFLR : XFXForm_1_ext<31, 339, 8, (ops GPRC:$rT), "mflr $rT", SprMFSPR>,
704 PPC970_DGroup_First, PPC970_Unit_FXU;
706 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like
707 // a GPR on the PPC970. As such, copies in and out have the same performance
708 // characteristics as an OR instruction.
709 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (ops GPRC:$rS),
710 "mtspr 256, $rS", IntGeneral>,
711 PPC970_DGroup_Single, PPC970_Unit_FXU;
712 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (ops GPRC:$rT),
713 "mfspr $rT, 256", IntGeneral>,
714 PPC970_DGroup_First, PPC970_Unit_FXU;
716 def MFCR : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT", SprMFCR>,
717 PPC970_MicroCode, PPC970_Unit_CRU;
718 def MTCRF : XFXForm_5<31, 144, (ops crbitm:$FXM, GPRC:$rS),
719 "mtcrf $FXM, $rS", BrMCRX>,
720 PPC970_MicroCode, PPC970_Unit_CRU;
721 def MFOCRF: XFXForm_5a<31, 19, (ops GPRC:$rT, crbitm:$FXM),
722 "mfcr $rT, $FXM", SprMFCR>,
723 PPC970_DGroup_First, PPC970_Unit_CRU;
725 // XS-Form instructions. Just 'sradi'
727 let PPC970_Unit = 1 in { // FXU Operations.
728 def SRADI : XSForm_1<31, 413, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH),
729 "sradi $rA, $rS, $SH", IntRotateD>, isPPC64;
731 // XO-Form instructions. Arithmetic instructions that can set overflow bit
733 def ADD4 : XOForm_1<31, 266, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
734 "add $rT, $rA, $rB", IntGeneral,
735 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
736 def ADD8 : XOForm_1<31, 266, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
737 "add $rT, $rA, $rB", IntGeneral,
738 [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>;
739 def ADDC : XOForm_1<31, 10, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
740 "addc $rT, $rA, $rB", IntGeneral,
741 [(set GPRC:$rT, (addc GPRC:$rA, GPRC:$rB))]>,
742 PPC970_DGroup_Cracked;
743 def ADDE : XOForm_1<31, 138, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
744 "adde $rT, $rA, $rB", IntGeneral,
745 [(set GPRC:$rT, (adde GPRC:$rA, GPRC:$rB))]>;
746 def DIVD : XOForm_1<31, 489, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
747 "divd $rT, $rA, $rB", IntDivD,
748 [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64,
749 PPC970_DGroup_First, PPC970_DGroup_Cracked;
750 def DIVDU : XOForm_1<31, 457, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
751 "divdu $rT, $rA, $rB", IntDivD,
752 [(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64,
753 PPC970_DGroup_First, PPC970_DGroup_Cracked;
754 def DIVW : XOForm_1<31, 491, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
755 "divw $rT, $rA, $rB", IntDivW,
756 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>,
757 PPC970_DGroup_First, PPC970_DGroup_Cracked;
758 def DIVWU : XOForm_1<31, 459, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
759 "divwu $rT, $rA, $rB", IntDivW,
760 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>,
761 PPC970_DGroup_First, PPC970_DGroup_Cracked;
762 def MULHD : XOForm_1<31, 73, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
763 "mulhd $rT, $rA, $rB", IntMulHW,
764 [(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>;
765 def MULHDU : XOForm_1<31, 9, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
766 "mulhdu $rT, $rA, $rB", IntMulHWU,
767 [(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))]>;
768 def MULHW : XOForm_1<31, 75, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
769 "mulhw $rT, $rA, $rB", IntMulHW,
770 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
771 def MULHWU : XOForm_1<31, 11, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
772 "mulhwu $rT, $rA, $rB", IntMulHWU,
773 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
774 def MULLD : XOForm_1<31, 233, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
775 "mulld $rT, $rA, $rB", IntMulHD,
776 [(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64;
777 def MULLW : XOForm_1<31, 235, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
778 "mullw $rT, $rA, $rB", IntMulHW,
779 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
780 def SUBF : XOForm_1<31, 40, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
781 "subf $rT, $rA, $rB", IntGeneral,
782 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
783 def SUBFC : XOForm_1<31, 8, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
784 "subfc $rT, $rA, $rB", IntGeneral,
785 [(set GPRC:$rT, (subc GPRC:$rB, GPRC:$rA))]>,
786 PPC970_DGroup_Cracked;
787 def SUBFE : XOForm_1<31, 136, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
788 "subfe $rT, $rA, $rB", IntGeneral,
789 [(set GPRC:$rT, (sube GPRC:$rB, GPRC:$rA))]>;
790 def ADDME : XOForm_3<31, 234, 0, (ops GPRC:$rT, GPRC:$rA),
791 "addme $rT, $rA", IntGeneral,
792 [(set GPRC:$rT, (adde GPRC:$rA, immAllOnes))]>;
793 def ADDZE : XOForm_3<31, 202, 0, (ops GPRC:$rT, GPRC:$rA),
794 "addze $rT, $rA", IntGeneral,
795 [(set GPRC:$rT, (adde GPRC:$rA, 0))]>;
796 def NEG : XOForm_3<31, 104, 0, (ops GPRC:$rT, GPRC:$rA),
797 "neg $rT, $rA", IntGeneral,
798 [(set GPRC:$rT, (ineg GPRC:$rA))]>;
799 def SUBFME : XOForm_3<31, 232, 0, (ops GPRC:$rT, GPRC:$rA),
800 "subfme $rT, $rA", IntGeneral,
801 [(set GPRC:$rT, (sube immAllOnes, GPRC:$rA))]>;
802 def SUBFZE : XOForm_3<31, 200, 0, (ops GPRC:$rT, GPRC:$rA),
803 "subfze $rT, $rA", IntGeneral,
804 [(set GPRC:$rT, (sube 0, GPRC:$rA))]>;
807 // A-Form instructions. Most of the instructions executed in the FPU are of
810 let PPC970_Unit = 3 in { // FPU Operations.
811 def FMADD : AForm_1<63, 29,
812 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
813 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused,
814 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC),
816 Requires<[FPContractions]>;
817 def FMADDS : AForm_1<59, 29,
818 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
819 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
820 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
822 Requires<[FPContractions]>;
823 def FMSUB : AForm_1<63, 28,
824 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
825 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused,
826 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC),
828 Requires<[FPContractions]>;
829 def FMSUBS : AForm_1<59, 28,
830 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
831 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
832 [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC),
834 Requires<[FPContractions]>;
835 def FNMADD : AForm_1<63, 31,
836 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
837 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused,
838 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC),
840 Requires<[FPContractions]>;
841 def FNMADDS : AForm_1<59, 31,
842 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
843 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
844 [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC),
846 Requires<[FPContractions]>;
847 def FNMSUB : AForm_1<63, 30,
848 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
849 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused,
850 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC),
852 Requires<[FPContractions]>;
853 def FNMSUBS : AForm_1<59, 30,
854 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
855 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
856 [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC),
858 Requires<[FPContractions]>;
859 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
860 // having 4 of these, force the comparison to always be an 8-byte double (code
861 // should use an FMRSD if the input comparison value really wants to be a float)
862 // and 4/8 byte forms for the result and operand type..
863 def FSELD : AForm_1<63, 23,
864 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
865 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
866 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>;
867 def FSELS : AForm_1<63, 23,
868 (ops F4RC:$FRT, F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
869 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
870 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>;
871 def FADD : AForm_2<63, 21,
872 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
873 "fadd $FRT, $FRA, $FRB", FPGeneral,
874 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>;
875 def FADDS : AForm_2<59, 21,
876 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
877 "fadds $FRT, $FRA, $FRB", FPGeneral,
878 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>;
879 def FDIV : AForm_2<63, 18,
880 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
881 "fdiv $FRT, $FRA, $FRB", FPDivD,
882 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>;
883 def FDIVS : AForm_2<59, 18,
884 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
885 "fdivs $FRT, $FRA, $FRB", FPDivS,
886 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>;
887 def FMUL : AForm_3<63, 25,
888 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
889 "fmul $FRT, $FRA, $FRB", FPFused,
890 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>;
891 def FMULS : AForm_3<59, 25,
892 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
893 "fmuls $FRT, $FRA, $FRB", FPGeneral,
894 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>;
895 def FSUB : AForm_2<63, 20,
896 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
897 "fsub $FRT, $FRA, $FRB", FPGeneral,
898 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>;
899 def FSUBS : AForm_2<59, 20,
900 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
901 "fsubs $FRT, $FRA, $FRB", FPGeneral,
902 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>;
905 let PPC970_Unit = 1 in { // FXU Operations.
906 // M-Form instructions. rotate and mask instructions.
908 let isTwoAddress = 1, isCommutable = 1 in {
909 // RLWIMI can be commuted if the rotate amount is zero.
910 def RLWIMI : MForm_2<20,
911 (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
912 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate,
913 []>, PPC970_DGroup_Cracked;
914 def RLDIMI : MDForm_1<30, 3,
915 (ops G8RC:$rA, G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB),
916 "rldimi $rA, $rS, $SH, $MB", IntRotateD,
919 def RLWINM : MForm_2<21,
920 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
921 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
923 def RLWINMo : MForm_2<21,
924 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
925 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
926 []>, isDOT, PPC970_DGroup_Cracked;
927 def RLWNM : MForm_2<23,
928 (ops GPRC:$rA, GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
929 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral,
932 // MD-Form instructions. 64 bit rotate instructions.
934 def RLDICL : MDForm_1<30, 0,
935 (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$MB),
936 "rldicl $rA, $rS, $SH, $MB", IntRotateD,
938 def RLDICR : MDForm_1<30, 1,
939 (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$ME),
940 "rldicr $rA, $rS, $SH, $ME", IntRotateD,
944 let PPC970_Unit = 5 in { // VALU Operations.
945 // VA-Form instructions. 3-input AltiVec ops.
946 def VMADDFP : VAForm_1<46, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
947 "vmaddfp $vD, $vA, $vC, $vB", VecFP,
948 [(set VRRC:$vD, (fadd (fmul VRRC:$vA, VRRC:$vC),
950 Requires<[FPContractions]>;
951 def VNMSUBFP: VAForm_1<47, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
952 "vnmsubfp $vD, $vA, $vC, $vB", VecFP,
953 [(set VRRC:$vD, (fneg (fsub (fmul VRRC:$vA,
956 Requires<[FPContractions]>;
958 // VX-Form instructions. AltiVec arithmetic ops.
959 def VADDFP : VXForm_1<10, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
960 "vaddfp $vD, $vA, $vB", VecFP,
961 [(set VRRC:$vD, (fadd VRRC:$vA, VRRC:$vB))]>;
962 def VADDUWM : VXForm_1<128, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
963 "vadduwm $vD, $vA, $vB", VecGeneral,
964 [(set VRRC:$vD, (add VRRC:$vA, VRRC:$vB))]>;
965 def VCFSX : VXForm_1<842, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
966 "vcfsx $vD, $vB, $UIMM", VecFP,
968 def VCFUX : VXForm_1<778, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
969 "vcfux $vD, $vB, $UIMM", VecFP,
971 def VCTSXS : VXForm_1<970, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
972 "vctsxs $vD, $vB, $UIMM", VecFP,
974 def VCTUXS : VXForm_1<906, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
975 "vctuxs $vD, $vB, $UIMM", VecFP,
977 def VEXPTEFP : VXForm_2<394, (ops VRRC:$vD, VRRC:$vB),
978 "vexptefp $vD, $vB", VecFP,
980 def VLOGEFP : VXForm_2<458, (ops VRRC:$vD, VRRC:$vB),
981 "vlogefp $vD, $vB", VecFP,
983 def VMAXFP : VXForm_1<1034, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
984 "vmaxfp $vD, $vA, $vB", VecFP,
986 def VMINFP : VXForm_1<1098, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
987 "vminfp $vD, $vA, $vB", VecFP,
989 def VREFP : VXForm_2<266, (ops VRRC:$vD, VRRC:$vB),
990 "vrefp $vD, $vB", VecFP,
992 def VRFIM : VXForm_2<714, (ops VRRC:$vD, VRRC:$vB),
993 "vrfim $vD, $vB", VecFP,
995 def VRFIN : VXForm_2<522, (ops VRRC:$vD, VRRC:$vB),
996 "vrfin $vD, $vB", VecFP,
998 def VRFIP : VXForm_2<650, (ops VRRC:$vD, VRRC:$vB),
999 "vrfip $vD, $vB", VecFP,
1001 def VRFIZ : VXForm_2<586, (ops VRRC:$vD, VRRC:$vB),
1002 "vrfiz $vD, $vB", VecFP,
1004 def VRSQRTEFP : VXForm_2<330, (ops VRRC:$vD, VRRC:$vB),
1005 "vrsqrtefp $vD, $vB", VecFP,
1007 def VSUBFP : VXForm_1<74, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
1008 "vsubfp $vD, $vA, $vB", VecFP,
1009 [(set VRRC:$vD, (fsub VRRC:$vA, VRRC:$vB))]>;
1010 def VOR : VXForm_1<1156, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
1011 "vor $vD, $vA, $vB", VecFP,
1013 def VXOR : VXForm_1<1220, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
1014 "vxor $vD, $vA, $vB", VecFP,
1017 // VX-Form Pseudo Instructions
1019 def V_SET0 : VXForm_setzero<1220, (ops VRRC:$vD),
1020 "vxor $vD, $vD, $vD", VecFP,
1024 //===----------------------------------------------------------------------===//
1025 // DWARF Pseudo Instructions
1028 def DWARF_LOC : Pseudo<(ops i32imm:$line, i32imm:$col, i32imm:$file),
1029 "; .loc $file, $line, $col",
1030 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
1033 def DWARF_LABEL : Pseudo<(ops i32imm:$id),
1035 [(dwarf_label (i32 imm:$id))]>;
1037 //===----------------------------------------------------------------------===//
1038 // PowerPC Instruction Patterns
1041 // Arbitrary immediate support. Implement in terms of LIS/ORI.
1042 def : Pat<(i32 imm:$imm),
1043 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
1045 // Implement the 'not' operation with the NOR instruction.
1046 def NOT : Pat<(not GPRC:$in),
1047 (NOR GPRC:$in, GPRC:$in)>;
1049 // ADD an arbitrary immediate.
1050 def : Pat<(add GPRC:$in, imm:$imm),
1051 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
1052 // OR an arbitrary immediate.
1053 def : Pat<(or GPRC:$in, imm:$imm),
1054 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1055 // XOR an arbitrary immediate.
1056 def : Pat<(xor GPRC:$in, imm:$imm),
1057 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1059 def : Pat<(sub immSExt16:$imm, GPRC:$in),
1060 (SUBFIC GPRC:$in, imm:$imm)>;
1062 // Return void support.
1063 def : Pat<(ret), (BLR)>;
1066 def : Pat<(i64 (zext GPRC:$in)),
1067 (RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>;
1068 def : Pat<(i64 (anyext GPRC:$in)),
1069 (OR4To8 GPRC:$in, GPRC:$in)>;
1070 def : Pat<(i32 (trunc G8RC:$in)),
1071 (OR8To4 G8RC:$in, G8RC:$in)>;
1074 def : Pat<(shl GPRC:$in, (i32 imm:$imm)),
1075 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>;
1076 def : Pat<(shl G8RC:$in, (i64 imm:$imm)),
1077 (RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>;
1079 def : Pat<(srl GPRC:$in, (i32 imm:$imm)),
1080 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>;
1081 def : Pat<(srl G8RC:$in, (i64 imm:$imm)),
1082 (RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>;
1085 def : Pat<(rotl GPRC:$in, GPRC:$sh),
1086 (RLWNM GPRC:$in, GPRC:$sh, 0, 31)>;
1087 def : Pat<(rotl GPRC:$in, (i32 imm:$imm)),
1088 (RLWINM GPRC:$in, imm:$imm, 0, 31)>;
1090 // Hi and Lo for Darwin Global Addresses.
1091 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
1092 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
1093 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
1094 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
1095 def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)),
1096 (ADDIS GPRC:$in, tglobaladdr:$g)>;
1097 def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)),
1098 (ADDIS GPRC:$in, tconstpool:$g)>;
1100 def : Pat<(fmul VRRC:$vA, VRRC:$vB),
1101 (VMADDFP VRRC:$vA, (V_SET0), VRRC:$vB)>;
1103 // Fused negative multiply subtract, alternate pattern
1104 def : Pat<(fsub F8RC:$B, (fmul F8RC:$A, F8RC:$C)),
1105 (FNMSUB F8RC:$A, F8RC:$C, F8RC:$B)>,
1106 Requires<[FPContractions]>;
1107 def : Pat<(fsub F4RC:$B, (fmul F4RC:$A, F4RC:$C)),
1108 (FNMSUBS F4RC:$A, F4RC:$C, F4RC:$B)>,
1109 Requires<[FPContractions]>;
1111 // Fused multiply add and multiply sub for packed float. These are represented
1112 // separately from the real instructions above, for operations that must have
1113 // the additional precision, such as Newton-Rhapson (used by divide, sqrt)
1114 def : Pat<(PPCvmaddfp VRRC:$A, VRRC:$B, VRRC:$C),
1115 (VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>;
1116 def : Pat<(PPCvnmsubfp VRRC:$A, VRRC:$B, VRRC:$C),
1117 (VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>;
1119 // Standard shifts. These are represented separately from the real shifts above
1120 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
1122 def : Pat<(sra GPRC:$rS, GPRC:$rB),
1123 (SRAW GPRC:$rS, GPRC:$rB)>;
1124 def : Pat<(srl GPRC:$rS, GPRC:$rB),
1125 (SRW GPRC:$rS, GPRC:$rB)>;
1126 def : Pat<(shl GPRC:$rS, GPRC:$rB),
1127 (SLW GPRC:$rS, GPRC:$rB)>;
1129 def : Pat<(i32 (zextload iaddr:$src, i1)),
1131 def : Pat<(i32 (zextload xaddr:$src, i1)),
1133 def : Pat<(i32 (extload iaddr:$src, i1)),
1135 def : Pat<(i32 (extload xaddr:$src, i1)),
1137 def : Pat<(i32 (extload iaddr:$src, i8)),
1139 def : Pat<(i32 (extload xaddr:$src, i8)),
1141 def : Pat<(i32 (extload iaddr:$src, i16)),
1143 def : Pat<(i32 (extload xaddr:$src, i16)),
1145 def : Pat<(f64 (extload iaddr:$src, f32)),
1146 (FMRSD (LFS iaddr:$src))>;
1147 def : Pat<(f64 (extload xaddr:$src, f32)),
1148 (FMRSD (LFSX xaddr:$src))>;
1150 def : Pat<(v4i32 (load xoaddr:$src)),
1151 (v4i32 (LVX xoaddr:$src))>;
1152 def : Pat<(store (v4i32 VRRC:$rS), xoaddr:$dst),
1153 (STVX (v4i32 VRRC:$rS), xoaddr:$dst)>;
1154 def : Pat<(v4i32 (PPClve_x xoaddr:$src)),
1155 (v4i32 (LVEWX xoaddr:$src))>;
1157 def : Pat<(v4i32 (undef)), (v4i32 (IMPLICIT_DEF_VRRC))>;
1160 // Same as above, but using a temporary. FIXME: implement temporaries :)
1162 def : Pattern<(xor GPRC:$in, imm:$imm),
1163 [(set GPRC:$tmp, (XORI GPRC:$in, (LO16 imm:$imm))),
1164 (XORIS GPRC:$tmp, (HI16 imm:$imm))]>;