1 //===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPCShiftOp : SDTypeProfile<1, 2, [ // PPCshl, PPCsra, PPCsrl
24 SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32>
26 def SDT_PPCCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
28 def SDT_PPCvperm : SDTypeProfile<1, 3, [
29 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
32 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
33 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
36 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
37 SDTCisVT<1, i32>, SDTCisVT<2, OtherVT>
40 //===----------------------------------------------------------------------===//
41 // PowerPC specific DAG Nodes.
44 def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>;
45 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
46 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
47 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx, [SDNPHasChain]>;
49 def PPCfsel : SDNode<"PPCISD::FSEL",
50 // Type constraint for fsel.
51 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
52 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
54 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
55 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
56 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
57 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
59 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
61 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
62 // amounts. These nodes are generated by the multi-precision shift code.
63 def PPCsrl : SDNode<"PPCISD::SRL" , SDT_PPCShiftOp>;
64 def PPCsra : SDNode<"PPCISD::SRA" , SDT_PPCShiftOp>;
65 def PPCshl : SDNode<"PPCISD::SHL" , SDT_PPCShiftOp>;
67 def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>;
68 def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore, [SDNPHasChain]>;
70 // These are target-independent nodes, but have target-specific formats.
71 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeq,[SDNPHasChain]>;
72 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeq,[SDNPHasChain]>;
74 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>;
75 def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall,
76 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
77 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
78 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
79 def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTRet,
80 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
82 def retflag : SDNode<"PPCISD::RET_FLAG", SDTRet,
83 [SDNPHasChain, SDNPOptInFlag]>;
85 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
86 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutFlag]>;
88 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
89 [SDNPHasChain, SDNPOptInFlag]>;
91 //===----------------------------------------------------------------------===//
92 // PowerPC specific transformation functions and pattern fragments.
95 def SHL32 : SDNodeXForm<imm, [{
96 // Transformation function: 31 - imm
97 return getI32Imm(31 - N->getValue());
100 def SRL32 : SDNodeXForm<imm, [{
101 // Transformation function: 32 - imm
102 return N->getValue() ? getI32Imm(32 - N->getValue()) : getI32Imm(0);
105 def LO16 : SDNodeXForm<imm, [{
106 // Transformation function: get the low 16 bits.
107 return getI32Imm((unsigned short)N->getValue());
110 def HI16 : SDNodeXForm<imm, [{
111 // Transformation function: shift the immediate value down into the low bits.
112 return getI32Imm((unsigned)N->getValue() >> 16);
115 def HA16 : SDNodeXForm<imm, [{
116 // Transformation function: shift the immediate value down into the low bits.
117 signed int Val = N->getValue();
118 return getI32Imm((Val - (signed short)Val) >> 16);
122 def immSExt16 : PatLeaf<(imm), [{
123 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
124 // field. Used by instructions like 'addi'.
125 return (int)N->getValue() == (short)N->getValue();
127 def immZExt16 : PatLeaf<(imm), [{
128 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
129 // field. Used by instructions like 'ori'.
130 return (unsigned)N->getValue() == (unsigned short)N->getValue();
133 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
134 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
135 // identical in 32-bit mode, but in 64-bit mode, they return true if the
136 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
138 def imm16ShiftedZExt : PatLeaf<(imm), [{
139 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
140 // immediate are set. Used by instructions like 'xoris'.
141 return (N->getValue() & ~uint64_t(0xFFFF0000)) == 0;
144 def imm16ShiftedSExt : PatLeaf<(imm), [{
145 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
146 // immediate are set. Used by instructions like 'addis'. Identical to
147 // imm16ShiftedZExt in 32-bit mode.
148 if (N->getValue() & 0xFFFF) return false;
149 if (N->getValueType(0) == MVT::i32)
151 // For 64-bit, make sure it is sext right.
152 return N->getValue() == (uint64_t)(int)N->getValue();
156 //===----------------------------------------------------------------------===//
157 // PowerPC Flag Definitions.
159 class isPPC64 { bit PPC64 = 1; }
161 list<Register> Defs = [CR0];
167 //===----------------------------------------------------------------------===//
168 // PowerPC Operand Definitions.
170 def s5imm : Operand<i32> {
171 let PrintMethod = "printS5ImmOperand";
173 def u5imm : Operand<i32> {
174 let PrintMethod = "printU5ImmOperand";
176 def u6imm : Operand<i32> {
177 let PrintMethod = "printU6ImmOperand";
179 def s16imm : Operand<i32> {
180 let PrintMethod = "printS16ImmOperand";
182 def u16imm : Operand<i32> {
183 let PrintMethod = "printU16ImmOperand";
185 def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing.
186 let PrintMethod = "printS16X4ImmOperand";
188 def target : Operand<OtherVT> {
189 let PrintMethod = "printBranchOperand";
191 def calltarget : Operand<iPTR> {
192 let PrintMethod = "printCallOperand";
194 def aaddr : Operand<iPTR> {
195 let PrintMethod = "printAbsAddrOperand";
197 def piclabel: Operand<iPTR> {
198 let PrintMethod = "printPICLabel";
200 def symbolHi: Operand<i32> {
201 let PrintMethod = "printSymbolHi";
203 def symbolLo: Operand<i32> {
204 let PrintMethod = "printSymbolLo";
206 def crbitm: Operand<i8> {
207 let PrintMethod = "printcrbitm";
210 def memri : Operand<iPTR> {
211 let PrintMethod = "printMemRegImm";
212 let NumMIOperands = 2;
213 let MIOperandInfo = (ops i32imm, ptr_rc);
215 def memrr : Operand<iPTR> {
216 let PrintMethod = "printMemRegReg";
217 let NumMIOperands = 2;
218 let MIOperandInfo = (ops ptr_rc, ptr_rc);
220 def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits.
221 let PrintMethod = "printMemRegImmShifted";
222 let NumMIOperands = 2;
223 let MIOperandInfo = (ops i32imm, ptr_rc);
226 // Define PowerPC specific addressing mode.
227 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", []>;
228 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", []>;
229 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[]>;
230 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", []>; // "std"
232 //===----------------------------------------------------------------------===//
233 // PowerPC Instruction Predicate Definitions.
234 def FPContractions : Predicate<"!NoExcessFPPrecision">;
236 //===----------------------------------------------------------------------===//
237 // PowerPC Instruction Definitions.
239 // Pseudo-instructions:
241 let hasCtrlDep = 1 in {
242 def ADJCALLSTACKDOWN : Pseudo<(ops u16imm:$amt),
243 "; ADJCALLSTACKDOWN",
244 [(callseq_start imm:$amt)]>;
245 def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt),
247 [(callseq_end imm:$amt)]>;
249 def UPDATE_VRSAVE : Pseudo<(ops GPRC:$rD, GPRC:$rS),
250 "UPDATE_VRSAVE $rD, $rS", []>;
252 def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC",
253 [(set GPRC:$rD, (undef))]>;
254 def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "; $rD = IMPLICIT_DEF_F8",
255 [(set F8RC:$rD, (undef))]>;
256 def IMPLICIT_DEF_F4 : Pseudo<(ops F4RC:$rD), "; $rD = IMPLICIT_DEF_F4",
257 [(set F4RC:$rD, (undef))]>;
259 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
260 // scheduler into a branch sequence.
261 let usesCustomDAGSchedInserter = 1, // Expanded by the scheduler.
262 PPC970_Single = 1 in {
263 def SELECT_CC_Int : Pseudo<(ops GPRC:$dst, CRRC:$cond, GPRC:$T, GPRC:$F,
264 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
265 def SELECT_CC_F4 : Pseudo<(ops F4RC:$dst, CRRC:$cond, F4RC:$T, F4RC:$F,
266 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
267 def SELECT_CC_F8 : Pseudo<(ops F8RC:$dst, CRRC:$cond, F8RC:$T, F8RC:$F,
268 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
269 def SELECT_CC_VRRC: Pseudo<(ops VRRC:$dst, CRRC:$cond, VRRC:$T, VRRC:$F,
270 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
273 let isTerminator = 1, noResults = 1, PPC970_Unit = 7 in {
275 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr", BrB, [(retflag)]>;
276 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr", BrB, []>;
280 def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label", []>,
283 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1,
284 noResults = 1, PPC970_Unit = 7 in {
285 def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm:$opc, target:$dst),
286 "; COND_BRANCH $crS, $opc, $dst",
287 [(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]>;
288 def B : IForm<18, 0, 0, (ops target:$dst),
292 def BLT : BForm<16, 0, 0, 12, 0, (ops CRRC:$crS, target:$block),
293 "blt $crS, $block", BrB>;
294 def BLE : BForm<16, 0, 0, 4, 1, (ops CRRC:$crS, target:$block),
295 "ble $crS, $block", BrB>;
296 def BEQ : BForm<16, 0, 0, 12, 2, (ops CRRC:$crS, target:$block),
297 "beq $crS, $block", BrB>;
298 def BGE : BForm<16, 0, 0, 4, 0, (ops CRRC:$crS, target:$block),
299 "bge $crS, $block", BrB>;
300 def BGT : BForm<16, 0, 0, 12, 1, (ops CRRC:$crS, target:$block),
301 "bgt $crS, $block", BrB>;
302 def BNE : BForm<16, 0, 0, 4, 2, (ops CRRC:$crS, target:$block),
303 "bne $crS, $block", BrB>;
304 def BUN : BForm<16, 0, 0, 12, 3, (ops CRRC:$crS, target:$block),
305 "bun $crS, $block", BrB>;
306 def BNU : BForm<16, 0, 0, 4, 3, (ops CRRC:$crS, target:$block),
307 "bnu $crS, $block", BrB>;
310 let isCall = 1, noResults = 1, PPC970_Unit = 7,
311 // All calls clobber the non-callee saved registers...
312 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
313 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
314 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
316 CR0,CR1,CR5,CR6,CR7] in {
317 // Convenient aliases for call instructions
318 def BL : IForm<18, 0, 1, (ops calltarget:$func, variable_ops),
319 "bl $func", BrB, []>; // See Pat patterns below.
320 def BLA : IForm<18, 1, 1, (ops aaddr:$func, variable_ops),
321 "bla $func", BrB, [(PPCcall imm:$func)]>;
322 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (ops variable_ops), "bctrl", BrB,
326 // DCB* instructions.
327 def DCBZ : DCB_Form<1014, 0, (ops memrr:$dst),
328 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
329 PPC970_DGroup_Single;
330 def DCBZL : DCB_Form<1014, 1, (ops memrr:$dst),
331 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
332 PPC970_DGroup_Single;
334 // D-Form instructions. Most instructions that perform an operation on a
335 // register and an immediate are of this type.
337 let isLoad = 1, PPC970_Unit = 2 in {
338 def LBZ : DForm_1<34, (ops GPRC:$rD, memri:$src),
339 "lbz $rD, $src", LdStGeneral,
340 [(set GPRC:$rD, (zextload iaddr:$src, i8))]>;
341 def LHA : DForm_1<42, (ops GPRC:$rD, memri:$src),
342 "lha $rD, $src", LdStLHA,
343 [(set GPRC:$rD, (sextload iaddr:$src, i16))]>,
344 PPC970_DGroup_Cracked;
345 def LHZ : DForm_1<40, (ops GPRC:$rD, memri:$src),
346 "lhz $rD, $src", LdStGeneral,
347 [(set GPRC:$rD, (zextload iaddr:$src, i16))]>;
348 def LWZ : DForm_1<32, (ops GPRC:$rD, memri:$src),
349 "lwz $rD, $src", LdStGeneral,
350 [(set GPRC:$rD, (load iaddr:$src))]>;
351 def LWZU : DForm_1<35, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
352 "lwzu $rD, $disp($rA)", LdStGeneral,
355 let PPC970_Unit = 1 in { // FXU Operations.
356 def ADDI : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
357 "addi $rD, $rA, $imm", IntGeneral,
358 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
359 def ADDIC : DForm_2<12, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
360 "addic $rD, $rA, $imm", IntGeneral,
361 [(set GPRC:$rD, (addc GPRC:$rA, immSExt16:$imm))]>,
362 PPC970_DGroup_Cracked;
363 def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
364 "addic. $rD, $rA, $imm", IntGeneral,
366 def ADDIS : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$imm),
367 "addis $rD, $rA, $imm", IntGeneral,
368 [(set GPRC:$rD, (add GPRC:$rA, imm16ShiftedSExt:$imm))]>;
369 def LA : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym),
370 "la $rD, $sym($rA)", IntGeneral,
371 [(set GPRC:$rD, (add GPRC:$rA,
372 (PPClo tglobaladdr:$sym, 0)))]>;
373 def MULLI : DForm_2< 7, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
374 "mulli $rD, $rA, $imm", IntMulLI,
375 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
376 def SUBFIC : DForm_2< 8, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
377 "subfic $rD, $rA, $imm", IntGeneral,
378 [(set GPRC:$rD, (subc immSExt16:$imm, GPRC:$rA))]>;
379 def LI : DForm_2_r0<14, (ops GPRC:$rD, symbolLo:$imm),
380 "li $rD, $imm", IntGeneral,
381 [(set GPRC:$rD, immSExt16:$imm)]>;
382 def LIS : DForm_2_r0<15, (ops GPRC:$rD, symbolHi:$imm),
383 "lis $rD, $imm", IntGeneral,
384 [(set GPRC:$rD, imm16ShiftedSExt:$imm)]>;
386 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
387 def STB : DForm_3<38, (ops GPRC:$rS, memri:$src),
388 "stb $rS, $src", LdStGeneral,
389 [(truncstore GPRC:$rS, iaddr:$src, i8)]>;
390 def STH : DForm_3<44, (ops GPRC:$rS, memri:$src),
391 "sth $rS, $src", LdStGeneral,
392 [(truncstore GPRC:$rS, iaddr:$src, i16)]>;
393 def STW : DForm_3<36, (ops GPRC:$rS, memri:$src),
394 "stw $rS, $src", LdStGeneral,
395 [(store GPRC:$rS, iaddr:$src)]>;
396 def STWU : DForm_3<37, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
397 "stwu $rS, $disp($rA)", LdStGeneral,
400 let PPC970_Unit = 1 in { // FXU Operations.
401 def ANDIo : DForm_4<28, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
402 "andi. $dst, $src1, $src2", IntGeneral,
403 [(set GPRC:$dst, (and GPRC:$src1, immZExt16:$src2))]>,
405 def ANDISo : DForm_4<29, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
406 "andis. $dst, $src1, $src2", IntGeneral,
407 [(set GPRC:$dst, (and GPRC:$src1,imm16ShiftedZExt:$src2))]>,
409 def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
410 "ori $dst, $src1, $src2", IntGeneral,
411 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
412 def ORIS : DForm_4<25, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
413 "oris $dst, $src1, $src2", IntGeneral,
414 [(set GPRC:$dst, (or GPRC:$src1, imm16ShiftedZExt:$src2))]>;
415 def XORI : DForm_4<26, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
416 "xori $dst, $src1, $src2", IntGeneral,
417 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
418 def XORIS : DForm_4<27, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
419 "xoris $dst, $src1, $src2", IntGeneral,
420 [(set GPRC:$dst, (xor GPRC:$src1,imm16ShiftedZExt:$src2))]>;
421 def NOP : DForm_4_zero<24, (ops), "nop", IntGeneral,
423 def CMPI : DForm_5<11, (ops CRRC:$crD, i1imm:$L, GPRC:$rA, s16imm:$imm),
424 "cmpi $crD, $L, $rA, $imm", IntCompare>;
425 def CMPWI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
426 "cmpwi $crD, $rA, $imm", IntCompare>;
427 def CMPLI : DForm_6<10, (ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2),
428 "cmpli $dst, $size, $src1, $src2", IntCompare>;
429 def CMPLWI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
430 "cmplwi $dst, $src1, $src2", IntCompare>;
432 let isLoad = 1, PPC970_Unit = 2 in {
433 def LFS : DForm_8<48, (ops F4RC:$rD, memri:$src),
434 "lfs $rD, $src", LdStLFDU,
435 [(set F4RC:$rD, (load iaddr:$src))]>;
436 def LFD : DForm_8<50, (ops F8RC:$rD, memri:$src),
437 "lfd $rD, $src", LdStLFD,
438 [(set F8RC:$rD, (load iaddr:$src))]>;
440 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
441 def STFS : DForm_9<52, (ops F4RC:$rS, memri:$dst),
442 "stfs $rS, $dst", LdStUX,
443 [(store F4RC:$rS, iaddr:$dst)]>;
444 def STFD : DForm_9<54, (ops F8RC:$rS, memri:$dst),
445 "stfd $rS, $dst", LdStUX,
446 [(store F8RC:$rS, iaddr:$dst)]>;
449 // X-Form instructions. Most instructions that perform an operation on a
450 // register and another register are of this type.
452 let isLoad = 1, PPC970_Unit = 2 in {
453 def LBZX : XForm_1<31, 87, (ops GPRC:$rD, memrr:$src),
454 "lbzx $rD, $src", LdStGeneral,
455 [(set GPRC:$rD, (zextload xaddr:$src, i8))]>;
456 def LHAX : XForm_1<31, 343, (ops GPRC:$rD, memrr:$src),
457 "lhax $rD, $src", LdStLHA,
458 [(set GPRC:$rD, (sextload xaddr:$src, i16))]>,
459 PPC970_DGroup_Cracked;
460 def LHZX : XForm_1<31, 279, (ops GPRC:$rD, memrr:$src),
461 "lhzx $rD, $src", LdStGeneral,
462 [(set GPRC:$rD, (zextload xaddr:$src, i16))]>;
463 def LWZX : XForm_1<31, 23, (ops GPRC:$rD, memrr:$src),
464 "lwzx $rD, $src", LdStGeneral,
465 [(set GPRC:$rD, (load xaddr:$src))]>;
468 let PPC970_Unit = 1 in { // FXU Operations.
469 def NAND : XForm_6<31, 476, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
470 "nand $rA, $rS, $rB", IntGeneral,
471 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
472 def AND : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
473 "and $rA, $rS, $rB", IntGeneral,
474 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
475 def ANDC : XForm_6<31, 60, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
476 "andc $rA, $rS, $rB", IntGeneral,
477 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
478 def OR : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
479 "or $rA, $rS, $rB", IntGeneral,
480 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
481 def NOR : XForm_6<31, 124, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
482 "nor $rA, $rS, $rB", IntGeneral,
483 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
484 def ORC : XForm_6<31, 412, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
485 "orc $rA, $rS, $rB", IntGeneral,
486 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
487 def EQV : XForm_6<31, 284, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
488 "eqv $rA, $rS, $rB", IntGeneral,
489 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
490 def XOR : XForm_6<31, 316, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
491 "xor $rA, $rS, $rB", IntGeneral,
492 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
493 def SLW : XForm_6<31, 24, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
494 "slw $rA, $rS, $rB", IntGeneral,
495 [(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>;
496 def SRW : XForm_6<31, 536, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
497 "srw $rA, $rS, $rB", IntGeneral,
498 [(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>;
499 def SRAW : XForm_6<31, 792, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
500 "sraw $rA, $rS, $rB", IntShift,
501 [(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>;
503 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
504 def STBX : XForm_8<31, 215, (ops GPRC:$rS, memrr:$dst),
505 "stbx $rS, $dst", LdStGeneral,
506 [(truncstore GPRC:$rS, xaddr:$dst, i8)]>,
507 PPC970_DGroup_Cracked;
508 def STHX : XForm_8<31, 407, (ops GPRC:$rS, memrr:$dst),
509 "sthx $rS, $dst", LdStGeneral,
510 [(truncstore GPRC:$rS, xaddr:$dst, i16)]>,
511 PPC970_DGroup_Cracked;
512 def STWX : XForm_8<31, 151, (ops GPRC:$rS, memrr:$dst),
513 "stwx $rS, $dst", LdStGeneral,
514 [(store GPRC:$rS, xaddr:$dst)]>,
515 PPC970_DGroup_Cracked;
516 def STWUX : XForm_8<31, 183, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
517 "stwux $rS, $rA, $rB", LdStGeneral,
520 let PPC970_Unit = 1 in { // FXU Operations.
521 def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
522 "srawi $rA, $rS, $SH", IntShift,
523 [(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>;
524 def CNTLZW : XForm_11<31, 26, (ops GPRC:$rA, GPRC:$rS),
525 "cntlzw $rA, $rS", IntGeneral,
526 [(set GPRC:$rA, (ctlz GPRC:$rS))]>;
527 def EXTSB : XForm_11<31, 954, (ops GPRC:$rA, GPRC:$rS),
528 "extsb $rA, $rS", IntGeneral,
529 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
530 def EXTSH : XForm_11<31, 922, (ops GPRC:$rA, GPRC:$rS),
531 "extsh $rA, $rS", IntGeneral,
532 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
534 def CMP : XForm_16<31, 0, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
535 "cmp $crD, $long, $rA, $rB", IntCompare>;
536 def CMPL : XForm_16<31, 32, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
537 "cmpl $crD, $long, $rA, $rB", IntCompare>;
538 def CMPW : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
539 "cmpw $crD, $rA, $rB", IntCompare>;
540 def CMPLW : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
541 "cmplw $crD, $rA, $rB", IntCompare>;
543 let PPC970_Unit = 3 in { // FPU Operations.
544 //def FCMPO : XForm_17<63, 32, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
545 // "fcmpo $crD, $fA, $fB", FPCompare>;
546 def FCMPUS : XForm_17<63, 0, (ops CRRC:$crD, F4RC:$fA, F4RC:$fB),
547 "fcmpu $crD, $fA, $fB", FPCompare>;
548 def FCMPUD : XForm_17<63, 0, (ops CRRC:$crD, F8RC:$fA, F8RC:$fB),
549 "fcmpu $crD, $fA, $fB", FPCompare>;
551 let isLoad = 1, PPC970_Unit = 2 in {
552 def LFSX : XForm_25<31, 535, (ops F4RC:$frD, memrr:$src),
553 "lfsx $frD, $src", LdStLFDU,
554 [(set F4RC:$frD, (load xaddr:$src))]>;
555 def LFDX : XForm_25<31, 599, (ops F8RC:$frD, memrr:$src),
556 "lfdx $frD, $src", LdStLFDU,
557 [(set F8RC:$frD, (load xaddr:$src))]>;
559 let PPC970_Unit = 3 in { // FPU Operations.
560 def FCTIWZ : XForm_26<63, 15, (ops F8RC:$frD, F8RC:$frB),
561 "fctiwz $frD, $frB", FPGeneral,
562 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>;
563 def FRSP : XForm_26<63, 12, (ops F4RC:$frD, F8RC:$frB),
564 "frsp $frD, $frB", FPGeneral,
565 [(set F4RC:$frD, (fround F8RC:$frB))]>;
566 def FSQRT : XForm_26<63, 22, (ops F8RC:$frD, F8RC:$frB),
567 "fsqrt $frD, $frB", FPSqrt,
568 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>;
569 def FSQRTS : XForm_26<59, 22, (ops F4RC:$frD, F4RC:$frB),
570 "fsqrts $frD, $frB", FPSqrt,
571 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>;
574 /// FMR is split into 3 versions, one for 4/8 byte FP, and one for extending.
576 /// Note that these are defined as pseudo-ops on the PPC970 because they are
577 /// often coalesced away and we don't want the dispatch group builder to think
578 /// that they will fill slots (which could cause the load of a LSU reject to
579 /// sneak into a d-group with a store).
580 def FMRS : XForm_26<63, 72, (ops F4RC:$frD, F4RC:$frB),
581 "fmr $frD, $frB", FPGeneral,
582 []>, // (set F4RC:$frD, F4RC:$frB)
584 def FMRD : XForm_26<63, 72, (ops F8RC:$frD, F8RC:$frB),
585 "fmr $frD, $frB", FPGeneral,
586 []>, // (set F8RC:$frD, F8RC:$frB)
588 def FMRSD : XForm_26<63, 72, (ops F8RC:$frD, F4RC:$frB),
589 "fmr $frD, $frB", FPGeneral,
590 [(set F8RC:$frD, (fextend F4RC:$frB))]>,
593 let PPC970_Unit = 3 in { // FPU Operations.
594 // These are artificially split into two different forms, for 4/8 byte FP.
595 def FABSS : XForm_26<63, 264, (ops F4RC:$frD, F4RC:$frB),
596 "fabs $frD, $frB", FPGeneral,
597 [(set F4RC:$frD, (fabs F4RC:$frB))]>;
598 def FABSD : XForm_26<63, 264, (ops F8RC:$frD, F8RC:$frB),
599 "fabs $frD, $frB", FPGeneral,
600 [(set F8RC:$frD, (fabs F8RC:$frB))]>;
601 def FNABSS : XForm_26<63, 136, (ops F4RC:$frD, F4RC:$frB),
602 "fnabs $frD, $frB", FPGeneral,
603 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>;
604 def FNABSD : XForm_26<63, 136, (ops F8RC:$frD, F8RC:$frB),
605 "fnabs $frD, $frB", FPGeneral,
606 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>;
607 def FNEGS : XForm_26<63, 40, (ops F4RC:$frD, F4RC:$frB),
608 "fneg $frD, $frB", FPGeneral,
609 [(set F4RC:$frD, (fneg F4RC:$frB))]>;
610 def FNEGD : XForm_26<63, 40, (ops F8RC:$frD, F8RC:$frB),
611 "fneg $frD, $frB", FPGeneral,
612 [(set F8RC:$frD, (fneg F8RC:$frB))]>;
615 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
616 def STFIWX: XForm_28<31, 983, (ops F8RC:$frS, memrr:$dst),
617 "stfiwx $frS, $dst", LdStUX,
618 [(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>;
619 def STFSX : XForm_28<31, 663, (ops F4RC:$frS, memrr:$dst),
620 "stfsx $frS, $dst", LdStUX,
621 [(store F4RC:$frS, xaddr:$dst)]>;
622 def STFDX : XForm_28<31, 727, (ops F8RC:$frS, memrr:$dst),
623 "stfdx $frS, $dst", LdStUX,
624 [(store F8RC:$frS, xaddr:$dst)]>;
627 // XL-Form instructions. condition register logical ops.
629 def MCRF : XLForm_3<19, 0, (ops CRRC:$BF, CRRC:$BFA),
630 "mcrf $BF, $BFA", BrMCR>,
631 PPC970_DGroup_First, PPC970_Unit_CRU;
633 // XFX-Form instructions. Instructions that deal with SPRs.
635 def MFCTR : XFXForm_1_ext<31, 339, 9, (ops GPRC:$rT), "mfctr $rT", SprMFSPR>,
636 PPC970_DGroup_First, PPC970_Unit_FXU;
637 let Pattern = [(PPCmtctr GPRC:$rS)] in {
638 def MTCTR : XFXForm_7_ext<31, 467, 9, (ops GPRC:$rS), "mtctr $rS", SprMTSPR>,
639 PPC970_DGroup_First, PPC970_Unit_FXU;
642 def MTLR : XFXForm_7_ext<31, 467, 8, (ops GPRC:$rS), "mtlr $rS", SprMTSPR>,
643 PPC970_DGroup_First, PPC970_Unit_FXU;
644 def MFLR : XFXForm_1_ext<31, 339, 8, (ops GPRC:$rT), "mflr $rT", SprMFSPR>,
645 PPC970_DGroup_First, PPC970_Unit_FXU;
647 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like
648 // a GPR on the PPC970. As such, copies in and out have the same performance
649 // characteristics as an OR instruction.
650 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (ops GPRC:$rS),
651 "mtspr 256, $rS", IntGeneral>,
652 PPC970_DGroup_Single, PPC970_Unit_FXU;
653 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (ops GPRC:$rT),
654 "mfspr $rT, 256", IntGeneral>,
655 PPC970_DGroup_First, PPC970_Unit_FXU;
657 def MTCRF : XFXForm_5<31, 144, (ops crbitm:$FXM, GPRC:$rS),
658 "mtcrf $FXM, $rS", BrMCRX>,
659 PPC970_MicroCode, PPC970_Unit_CRU;
660 def MFCR : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT", SprMFCR>,
661 PPC970_MicroCode, PPC970_Unit_CRU;
662 def MFOCRF: XFXForm_5a<31, 19, (ops GPRC:$rT, crbitm:$FXM),
663 "mfcr $rT, $FXM", SprMFCR>,
664 PPC970_DGroup_First, PPC970_Unit_CRU;
666 let PPC970_Unit = 1 in { // FXU Operations.
668 // XO-Form instructions. Arithmetic instructions that can set overflow bit
670 def ADD4 : XOForm_1<31, 266, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
671 "add $rT, $rA, $rB", IntGeneral,
672 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
673 def ADDC : XOForm_1<31, 10, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
674 "addc $rT, $rA, $rB", IntGeneral,
675 [(set GPRC:$rT, (addc GPRC:$rA, GPRC:$rB))]>,
676 PPC970_DGroup_Cracked;
677 def ADDE : XOForm_1<31, 138, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
678 "adde $rT, $rA, $rB", IntGeneral,
679 [(set GPRC:$rT, (adde GPRC:$rA, GPRC:$rB))]>;
680 def DIVW : XOForm_1<31, 491, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
681 "divw $rT, $rA, $rB", IntDivW,
682 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>,
683 PPC970_DGroup_First, PPC970_DGroup_Cracked;
684 def DIVWU : XOForm_1<31, 459, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
685 "divwu $rT, $rA, $rB", IntDivW,
686 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>,
687 PPC970_DGroup_First, PPC970_DGroup_Cracked;
688 def MULHW : XOForm_1<31, 75, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
689 "mulhw $rT, $rA, $rB", IntMulHW,
690 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
691 def MULHWU : XOForm_1<31, 11, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
692 "mulhwu $rT, $rA, $rB", IntMulHWU,
693 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
694 def MULLW : XOForm_1<31, 235, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
695 "mullw $rT, $rA, $rB", IntMulHW,
696 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
697 def SUBF : XOForm_1<31, 40, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
698 "subf $rT, $rA, $rB", IntGeneral,
699 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
700 def SUBFC : XOForm_1<31, 8, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
701 "subfc $rT, $rA, $rB", IntGeneral,
702 [(set GPRC:$rT, (subc GPRC:$rB, GPRC:$rA))]>,
703 PPC970_DGroup_Cracked;
704 def SUBFE : XOForm_1<31, 136, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
705 "subfe $rT, $rA, $rB", IntGeneral,
706 [(set GPRC:$rT, (sube GPRC:$rB, GPRC:$rA))]>;
707 def ADDME : XOForm_3<31, 234, 0, (ops GPRC:$rT, GPRC:$rA),
708 "addme $rT, $rA", IntGeneral,
709 [(set GPRC:$rT, (adde GPRC:$rA, immAllOnes))]>;
710 def ADDZE : XOForm_3<31, 202, 0, (ops GPRC:$rT, GPRC:$rA),
711 "addze $rT, $rA", IntGeneral,
712 [(set GPRC:$rT, (adde GPRC:$rA, 0))]>;
713 def NEG : XOForm_3<31, 104, 0, (ops GPRC:$rT, GPRC:$rA),
714 "neg $rT, $rA", IntGeneral,
715 [(set GPRC:$rT, (ineg GPRC:$rA))]>;
716 def SUBFME : XOForm_3<31, 232, 0, (ops GPRC:$rT, GPRC:$rA),
717 "subfme $rT, $rA", IntGeneral,
718 [(set GPRC:$rT, (sube immAllOnes, GPRC:$rA))]>;
719 def SUBFZE : XOForm_3<31, 200, 0, (ops GPRC:$rT, GPRC:$rA),
720 "subfze $rT, $rA", IntGeneral,
721 [(set GPRC:$rT, (sube 0, GPRC:$rA))]>;
724 // A-Form instructions. Most of the instructions executed in the FPU are of
727 let PPC970_Unit = 3 in { // FPU Operations.
728 def FMADD : AForm_1<63, 29,
729 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
730 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused,
731 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC),
733 Requires<[FPContractions]>;
734 def FMADDS : AForm_1<59, 29,
735 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
736 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
737 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
739 Requires<[FPContractions]>;
740 def FMSUB : AForm_1<63, 28,
741 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
742 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused,
743 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC),
745 Requires<[FPContractions]>;
746 def FMSUBS : AForm_1<59, 28,
747 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
748 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
749 [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC),
751 Requires<[FPContractions]>;
752 def FNMADD : AForm_1<63, 31,
753 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
754 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused,
755 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC),
757 Requires<[FPContractions]>;
758 def FNMADDS : AForm_1<59, 31,
759 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
760 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
761 [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC),
763 Requires<[FPContractions]>;
764 def FNMSUB : AForm_1<63, 30,
765 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
766 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused,
767 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC),
769 Requires<[FPContractions]>;
770 def FNMSUBS : AForm_1<59, 30,
771 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
772 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
773 [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC),
775 Requires<[FPContractions]>;
776 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
777 // having 4 of these, force the comparison to always be an 8-byte double (code
778 // should use an FMRSD if the input comparison value really wants to be a float)
779 // and 4/8 byte forms for the result and operand type..
780 def FSELD : AForm_1<63, 23,
781 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
782 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
783 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>;
784 def FSELS : AForm_1<63, 23,
785 (ops F4RC:$FRT, F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
786 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
787 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>;
788 def FADD : AForm_2<63, 21,
789 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
790 "fadd $FRT, $FRA, $FRB", FPGeneral,
791 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>;
792 def FADDS : AForm_2<59, 21,
793 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
794 "fadds $FRT, $FRA, $FRB", FPGeneral,
795 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>;
796 def FDIV : AForm_2<63, 18,
797 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
798 "fdiv $FRT, $FRA, $FRB", FPDivD,
799 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>;
800 def FDIVS : AForm_2<59, 18,
801 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
802 "fdivs $FRT, $FRA, $FRB", FPDivS,
803 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>;
804 def FMUL : AForm_3<63, 25,
805 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
806 "fmul $FRT, $FRA, $FRB", FPFused,
807 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>;
808 def FMULS : AForm_3<59, 25,
809 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
810 "fmuls $FRT, $FRA, $FRB", FPGeneral,
811 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>;
812 def FSUB : AForm_2<63, 20,
813 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
814 "fsub $FRT, $FRA, $FRB", FPGeneral,
815 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>;
816 def FSUBS : AForm_2<59, 20,
817 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
818 "fsubs $FRT, $FRA, $FRB", FPGeneral,
819 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>;
822 let PPC970_Unit = 1 in { // FXU Operations.
823 // M-Form instructions. rotate and mask instructions.
825 let isTwoAddress = 1, isCommutable = 1 in {
826 // RLWIMI can be commuted if the rotate amount is zero.
827 def RLWIMI : MForm_2<20,
828 (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
829 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate,
830 []>, PPC970_DGroup_Cracked;
832 def RLWINM : MForm_2<21,
833 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
834 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
836 def RLWINMo : MForm_2<21,
837 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
838 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
839 []>, isDOT, PPC970_DGroup_Cracked;
840 def RLWNM : MForm_2<23,
841 (ops GPRC:$rA, GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
842 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral,
847 //===----------------------------------------------------------------------===//
848 // DWARF Pseudo Instructions
851 def DWARF_LOC : Pseudo<(ops i32imm:$line, i32imm:$col, i32imm:$file),
852 "; .loc $file, $line, $col",
853 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
856 def DWARF_LABEL : Pseudo<(ops i32imm:$id),
858 [(dwarf_label (i32 imm:$id))]>;
860 //===----------------------------------------------------------------------===//
861 // PowerPC Instruction Patterns
864 // Arbitrary immediate support. Implement in terms of LIS/ORI.
865 def : Pat<(i32 imm:$imm),
866 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
868 // Implement the 'not' operation with the NOR instruction.
869 def NOT : Pat<(not GPRC:$in),
870 (NOR GPRC:$in, GPRC:$in)>;
872 // ADD an arbitrary immediate.
873 def : Pat<(add GPRC:$in, imm:$imm),
874 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
875 // OR an arbitrary immediate.
876 def : Pat<(or GPRC:$in, imm:$imm),
877 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
878 // XOR an arbitrary immediate.
879 def : Pat<(xor GPRC:$in, imm:$imm),
880 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
882 def : Pat<(sub immSExt16:$imm, GPRC:$in),
883 (SUBFIC GPRC:$in, imm:$imm)>;
885 // Return void support.
886 def : Pat<(ret), (BLR)>;
889 def : Pat<(shl GPRC:$in, (i32 imm:$imm)),
890 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>;
891 def : Pat<(srl GPRC:$in, (i32 imm:$imm)),
892 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>;
895 def : Pat<(rotl GPRC:$in, GPRC:$sh),
896 (RLWNM GPRC:$in, GPRC:$sh, 0, 31)>;
897 def : Pat<(rotl GPRC:$in, (i32 imm:$imm)),
898 (RLWINM GPRC:$in, imm:$imm, 0, 31)>;
901 def : Pat<(PPCcall tglobaladdr:$dst),
902 (BL tglobaladdr:$dst)>;
903 def : Pat<(PPCcall texternalsym:$dst),
904 (BL texternalsym:$dst)>;
906 // Hi and Lo for Darwin Global Addresses.
907 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
908 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
909 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
910 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
911 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
912 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
913 def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)),
914 (ADDIS GPRC:$in, tglobaladdr:$g)>;
915 def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)),
916 (ADDIS GPRC:$in, tconstpool:$g)>;
917 def : Pat<(add GPRC:$in, (PPChi tjumptable:$g, 0)),
918 (ADDIS GPRC:$in, tjumptable:$g)>;
920 // Fused negative multiply subtract, alternate pattern
921 def : Pat<(fsub F8RC:$B, (fmul F8RC:$A, F8RC:$C)),
922 (FNMSUB F8RC:$A, F8RC:$C, F8RC:$B)>,
923 Requires<[FPContractions]>;
924 def : Pat<(fsub F4RC:$B, (fmul F4RC:$A, F4RC:$C)),
925 (FNMSUBS F4RC:$A, F4RC:$C, F4RC:$B)>,
926 Requires<[FPContractions]>;
928 // Standard shifts. These are represented separately from the real shifts above
929 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
931 def : Pat<(sra GPRC:$rS, GPRC:$rB),
932 (SRAW GPRC:$rS, GPRC:$rB)>;
933 def : Pat<(srl GPRC:$rS, GPRC:$rB),
934 (SRW GPRC:$rS, GPRC:$rB)>;
935 def : Pat<(shl GPRC:$rS, GPRC:$rB),
936 (SLW GPRC:$rS, GPRC:$rB)>;
938 def : Pat<(zextload iaddr:$src, i1),
940 def : Pat<(zextload xaddr:$src, i1),
942 def : Pat<(extload iaddr:$src, i1),
944 def : Pat<(extload xaddr:$src, i1),
946 def : Pat<(extload iaddr:$src, i8),
948 def : Pat<(extload xaddr:$src, i8),
950 def : Pat<(extload iaddr:$src, i16),
952 def : Pat<(extload xaddr:$src, i16),
954 def : Pat<(extload iaddr:$src, f32),
955 (FMRSD (LFS iaddr:$src))>;
956 def : Pat<(extload xaddr:$src, f32),
957 (FMRSD (LFSX xaddr:$src))>;
959 include "PPCInstrAltivec.td"
960 include "PPCInstr64Bit.td"