1 //===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x
24 SDTCisVT<0, f64>, SDTCisPtrTy<1>
27 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
28 def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
30 def SDT_PPCvperm : SDTypeProfile<1, 3, [
31 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
34 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
35 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
38 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
39 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
42 def SDT_PPClbrx : SDTypeProfile<1, 2, [
43 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
45 def SDT_PPCstbrx : SDTypeProfile<0, 3, [
46 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
49 def SDT_PPClarx : SDTypeProfile<1, 1, [
50 SDTCisInt<0>, SDTCisPtrTy<1>
52 def SDT_PPCstcx : SDTypeProfile<0, 2, [
53 SDTCisInt<0>, SDTCisPtrTy<1>
56 def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
57 SDTCisPtrTy<0>, SDTCisVT<1, i32>
60 def tocentry32 : Operand<iPTR> {
61 let MIOperandInfo = (ops i32imm:$imm);
64 def SDT_PPCqvfperm : SDTypeProfile<1, 3, [
65 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisVec<3>
67 def SDT_PPCqvgpci : SDTypeProfile<1, 1, [
68 SDTCisVec<0>, SDTCisInt<1>
70 def SDT_PPCqvaligni : SDTypeProfile<1, 3, [
71 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<3>
73 def SDT_PPCqvesplati : SDTypeProfile<1, 2, [
74 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisInt<2>
77 def SDT_PPCqbflt : SDTypeProfile<1, 1, [
78 SDTCisVec<0>, SDTCisVec<1>
81 def SDT_PPCqvlfsb : SDTypeProfile<1, 1, [
82 SDTCisVec<0>, SDTCisPtrTy<1>
85 //===----------------------------------------------------------------------===//
86 // PowerPC specific DAG Nodes.
89 def PPCfre : SDNode<"PPCISD::FRE", SDTFPUnaryOp, []>;
90 def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>;
92 def PPCfcfid : SDNode<"PPCISD::FCFID", SDTFPUnaryOp, []>;
93 def PPCfcfidu : SDNode<"PPCISD::FCFIDU", SDTFPUnaryOp, []>;
94 def PPCfcfids : SDNode<"PPCISD::FCFIDS", SDTFPRoundOp, []>;
95 def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>;
96 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
97 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
98 def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>;
99 def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>;
100 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
101 [SDNPHasChain, SDNPMayStore]>;
102 def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx,
103 [SDNPHasChain, SDNPMayLoad]>;
104 def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx,
105 [SDNPHasChain, SDNPMayLoad]>;
107 // Extract FPSCR (not modeled at the DAG level).
108 def PPCmffs : SDNode<"PPCISD::MFFS",
109 SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, []>;
111 // Perform FADD in round-to-zero mode.
112 def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>;
115 def PPCfsel : SDNode<"PPCISD::FSEL",
116 // Type constraint for fsel.
117 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
118 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
120 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
121 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
122 def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp,
123 [SDNPMayLoad, SDNPMemOperand]>;
124 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
125 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
127 def PPCppc32GOT : SDNode<"PPCISD::PPC32_GOT", SDTIntLeaf, []>;
129 def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>;
130 def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp,
132 def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>;
133 def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>;
134 def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>;
135 def PPCgetTlsAddr : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>;
136 def PPCaddiTlsgdLAddr : SDNode<"PPCISD::ADDI_TLSGD_L_ADDR",
137 SDTypeProfile<1, 3, [
138 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
139 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>;
140 def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>;
141 def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>;
142 def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>;
143 def PPCaddiTlsldLAddr : SDNode<"PPCISD::ADDI_TLSLD_L_ADDR",
144 SDTypeProfile<1, 3, [
145 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
146 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>;
147 def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp>;
148 def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>;
150 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
152 def PPCqvfperm : SDNode<"PPCISD::QVFPERM", SDT_PPCqvfperm, []>;
153 def PPCqvgpci : SDNode<"PPCISD::QVGPCI", SDT_PPCqvgpci, []>;
154 def PPCqvaligni : SDNode<"PPCISD::QVALIGNI", SDT_PPCqvaligni, []>;
155 def PPCqvesplati : SDNode<"PPCISD::QVESPLATI", SDT_PPCqvesplati, []>;
157 def PPCqbflt : SDNode<"PPCISD::QBFLT", SDT_PPCqbflt, []>;
159 def PPCqvlfsb : SDNode<"PPCISD::QVLFSb", SDT_PPCqvlfsb,
160 [SDNPHasChain, SDNPMayLoad]>;
162 def PPCcmpb : SDNode<"PPCISD::CMPB", SDTIntBinOp, []>;
164 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
165 // amounts. These nodes are generated by the multi-precision shift code.
166 def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>;
167 def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>;
168 def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>;
170 // These are target-independent nodes, but have target-specific formats.
171 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
172 [SDNPHasChain, SDNPOutGlue]>;
173 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd,
174 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
176 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
177 def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall,
178 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
180 def PPCcall_nop : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall,
181 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
183 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
184 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
185 def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone,
186 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
188 def PPCbctrl_load_toc : SDNode<"PPCISD::BCTRL_LOAD_TOC",
189 SDTypeProfile<0, 1, []>,
190 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
193 def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone,
194 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
196 def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
197 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
199 def PPCeh_sjlj_setjmp : SDNode<"PPCISD::EH_SJLJ_SETJMP",
200 SDTypeProfile<1, 1, [SDTCisInt<0>,
202 [SDNPHasChain, SDNPSideEffect]>;
203 def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP",
204 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
205 [SDNPHasChain, SDNPSideEffect]>;
207 def SDT_PPCsc : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
208 def PPCsc : SDNode<"PPCISD::SC", SDT_PPCsc,
209 [SDNPHasChain, SDNPSideEffect]>;
211 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
212 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>;
214 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
215 [SDNPHasChain, SDNPOptInGlue]>;
217 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
218 [SDNPHasChain, SDNPMayLoad]>;
219 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
220 [SDNPHasChain, SDNPMayStore]>;
222 // Instructions to set/unset CR bit 6 for SVR4 vararg calls
223 def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone,
224 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
225 def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone,
226 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
228 // Instructions to support atomic operations
229 def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx,
230 [SDNPHasChain, SDNPMayLoad]>;
231 def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx,
232 [SDNPHasChain, SDNPMayStore]>;
234 // Instructions to support dynamic alloca.
235 def SDTDynOp : SDTypeProfile<1, 2, []>;
236 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
238 //===----------------------------------------------------------------------===//
239 // PowerPC specific transformation functions and pattern fragments.
242 def SHL32 : SDNodeXForm<imm, [{
243 // Transformation function: 31 - imm
244 return getI32Imm(31 - N->getZExtValue());
247 def SRL32 : SDNodeXForm<imm, [{
248 // Transformation function: 32 - imm
249 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0);
252 def LO16 : SDNodeXForm<imm, [{
253 // Transformation function: get the low 16 bits.
254 return getI32Imm((unsigned short)N->getZExtValue());
257 def HI16 : SDNodeXForm<imm, [{
258 // Transformation function: shift the immediate value down into the low bits.
259 return getI32Imm((unsigned)N->getZExtValue() >> 16);
262 def HA16 : SDNodeXForm<imm, [{
263 // Transformation function: shift the immediate value down into the low bits.
264 signed int Val = N->getZExtValue();
265 return getI32Imm((Val - (signed short)Val) >> 16);
267 def MB : SDNodeXForm<imm, [{
268 // Transformation function: get the start bit of a mask
270 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
271 return getI32Imm(mb);
274 def ME : SDNodeXForm<imm, [{
275 // Transformation function: get the end bit of a mask
277 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
278 return getI32Imm(me);
280 def maskimm32 : PatLeaf<(imm), [{
281 // maskImm predicate - True if immediate is a run of ones.
283 if (N->getValueType(0) == MVT::i32)
284 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
289 def imm32SExt16 : Operand<i32>, ImmLeaf<i32, [{
290 // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit
291 // sign extended field. Used by instructions like 'addi'.
292 return (int32_t)Imm == (short)Imm;
294 def imm64SExt16 : Operand<i64>, ImmLeaf<i64, [{
295 // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit
296 // sign extended field. Used by instructions like 'addi'.
297 return (int64_t)Imm == (short)Imm;
299 def immZExt16 : PatLeaf<(imm), [{
300 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
301 // field. Used by instructions like 'ori'.
302 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
305 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
306 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
307 // identical in 32-bit mode, but in 64-bit mode, they return true if the
308 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
310 def imm16ShiftedZExt : PatLeaf<(imm), [{
311 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
312 // immediate are set. Used by instructions like 'xoris'.
313 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
316 def imm16ShiftedSExt : PatLeaf<(imm), [{
317 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
318 // immediate are set. Used by instructions like 'addis'. Identical to
319 // imm16ShiftedZExt in 32-bit mode.
320 if (N->getZExtValue() & 0xFFFF) return false;
321 if (N->getValueType(0) == MVT::i32)
323 // For 64-bit, make sure it is sext right.
324 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
327 def imm64ZExt32 : Operand<i64>, ImmLeaf<i64, [{
328 // imm64ZExt32 predicate - True if the i64 immediate fits in a 32-bit
329 // zero extended field.
330 return isUInt<32>(Imm);
333 // Some r+i load/store instructions (such as LD, STD, LDU, etc.) that require
334 // restricted memrix (4-aligned) constants are alignment sensitive. If these
335 // offsets are hidden behind TOC entries than the values of the lower-order
336 // bits cannot be checked directly. As a result, we need to also incorporate
337 // an alignment check into the relevant patterns.
339 def aligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
340 return cast<LoadSDNode>(N)->getAlignment() >= 4;
342 def aligned4store : PatFrag<(ops node:$val, node:$ptr),
343 (store node:$val, node:$ptr), [{
344 return cast<StoreSDNode>(N)->getAlignment() >= 4;
346 def aligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
347 return cast<LoadSDNode>(N)->getAlignment() >= 4;
349 def aligned4pre_store : PatFrag<
350 (ops node:$val, node:$base, node:$offset),
351 (pre_store node:$val, node:$base, node:$offset), [{
352 return cast<StoreSDNode>(N)->getAlignment() >= 4;
355 def unaligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
356 return cast<LoadSDNode>(N)->getAlignment() < 4;
358 def unaligned4store : PatFrag<(ops node:$val, node:$ptr),
359 (store node:$val, node:$ptr), [{
360 return cast<StoreSDNode>(N)->getAlignment() < 4;
362 def unaligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
363 return cast<LoadSDNode>(N)->getAlignment() < 4;
366 //===----------------------------------------------------------------------===//
367 // PowerPC Flag Definitions.
369 class isPPC64 { bit PPC64 = 1; }
370 class isDOT { bit RC = 1; }
372 class RegConstraint<string C> {
373 string Constraints = C;
375 class NoEncode<string E> {
376 string DisableEncoding = E;
380 //===----------------------------------------------------------------------===//
381 // PowerPC Operand Definitions.
383 // In the default PowerPC assembler syntax, registers are specified simply
384 // by number, so they cannot be distinguished from immediate values (without
385 // looking at the opcode). This means that the default operand matching logic
386 // for the asm parser does not work, and we need to specify custom matchers.
387 // Since those can only be specified with RegisterOperand classes and not
388 // directly on the RegisterClass, all instructions patterns used by the asm
389 // parser need to use a RegisterOperand (instead of a RegisterClass) for
390 // all their register operands.
391 // For this purpose, we define one RegisterOperand for each RegisterClass,
392 // using the same name as the class, just in lower case.
394 def PPCRegGPRCAsmOperand : AsmOperandClass {
395 let Name = "RegGPRC"; let PredicateMethod = "isRegNumber";
397 def gprc : RegisterOperand<GPRC> {
398 let ParserMatchClass = PPCRegGPRCAsmOperand;
400 def PPCRegG8RCAsmOperand : AsmOperandClass {
401 let Name = "RegG8RC"; let PredicateMethod = "isRegNumber";
403 def g8rc : RegisterOperand<G8RC> {
404 let ParserMatchClass = PPCRegG8RCAsmOperand;
406 def PPCRegGPRCNoR0AsmOperand : AsmOperandClass {
407 let Name = "RegGPRCNoR0"; let PredicateMethod = "isRegNumber";
409 def gprc_nor0 : RegisterOperand<GPRC_NOR0> {
410 let ParserMatchClass = PPCRegGPRCNoR0AsmOperand;
412 def PPCRegG8RCNoX0AsmOperand : AsmOperandClass {
413 let Name = "RegG8RCNoX0"; let PredicateMethod = "isRegNumber";
415 def g8rc_nox0 : RegisterOperand<G8RC_NOX0> {
416 let ParserMatchClass = PPCRegG8RCNoX0AsmOperand;
418 def PPCRegF8RCAsmOperand : AsmOperandClass {
419 let Name = "RegF8RC"; let PredicateMethod = "isRegNumber";
421 def f8rc : RegisterOperand<F8RC> {
422 let ParserMatchClass = PPCRegF8RCAsmOperand;
424 def PPCRegF4RCAsmOperand : AsmOperandClass {
425 let Name = "RegF4RC"; let PredicateMethod = "isRegNumber";
427 def f4rc : RegisterOperand<F4RC> {
428 let ParserMatchClass = PPCRegF4RCAsmOperand;
430 def PPCRegVRRCAsmOperand : AsmOperandClass {
431 let Name = "RegVRRC"; let PredicateMethod = "isRegNumber";
433 def vrrc : RegisterOperand<VRRC> {
434 let ParserMatchClass = PPCRegVRRCAsmOperand;
436 def PPCRegCRBITRCAsmOperand : AsmOperandClass {
437 let Name = "RegCRBITRC"; let PredicateMethod = "isCRBitNumber";
439 def crbitrc : RegisterOperand<CRBITRC> {
440 let ParserMatchClass = PPCRegCRBITRCAsmOperand;
442 def PPCRegCRRCAsmOperand : AsmOperandClass {
443 let Name = "RegCRRC"; let PredicateMethod = "isCCRegNumber";
445 def crrc : RegisterOperand<CRRC> {
446 let ParserMatchClass = PPCRegCRRCAsmOperand;
449 def PPCU1ImmAsmOperand : AsmOperandClass {
450 let Name = "U1Imm"; let PredicateMethod = "isU1Imm";
451 let RenderMethod = "addImmOperands";
453 def u1imm : Operand<i32> {
454 let PrintMethod = "printU1ImmOperand";
455 let ParserMatchClass = PPCU1ImmAsmOperand;
458 def PPCU2ImmAsmOperand : AsmOperandClass {
459 let Name = "U2Imm"; let PredicateMethod = "isU2Imm";
460 let RenderMethod = "addImmOperands";
462 def u2imm : Operand<i32> {
463 let PrintMethod = "printU2ImmOperand";
464 let ParserMatchClass = PPCU2ImmAsmOperand;
467 def PPCU4ImmAsmOperand : AsmOperandClass {
468 let Name = "U4Imm"; let PredicateMethod = "isU4Imm";
469 let RenderMethod = "addImmOperands";
471 def u4imm : Operand<i32> {
472 let PrintMethod = "printU4ImmOperand";
473 let ParserMatchClass = PPCU4ImmAsmOperand;
475 def PPCS5ImmAsmOperand : AsmOperandClass {
476 let Name = "S5Imm"; let PredicateMethod = "isS5Imm";
477 let RenderMethod = "addImmOperands";
479 def s5imm : Operand<i32> {
480 let PrintMethod = "printS5ImmOperand";
481 let ParserMatchClass = PPCS5ImmAsmOperand;
482 let DecoderMethod = "decodeSImmOperand<5>";
484 def PPCU5ImmAsmOperand : AsmOperandClass {
485 let Name = "U5Imm"; let PredicateMethod = "isU5Imm";
486 let RenderMethod = "addImmOperands";
488 def u5imm : Operand<i32> {
489 let PrintMethod = "printU5ImmOperand";
490 let ParserMatchClass = PPCU5ImmAsmOperand;
491 let DecoderMethod = "decodeUImmOperand<5>";
493 def PPCU6ImmAsmOperand : AsmOperandClass {
494 let Name = "U6Imm"; let PredicateMethod = "isU6Imm";
495 let RenderMethod = "addImmOperands";
497 def u6imm : Operand<i32> {
498 let PrintMethod = "printU6ImmOperand";
499 let ParserMatchClass = PPCU6ImmAsmOperand;
500 let DecoderMethod = "decodeUImmOperand<6>";
502 def PPCU12ImmAsmOperand : AsmOperandClass {
503 let Name = "U12Imm"; let PredicateMethod = "isU12Imm";
504 let RenderMethod = "addImmOperands";
506 def u12imm : Operand<i32> {
507 let PrintMethod = "printU12ImmOperand";
508 let ParserMatchClass = PPCU12ImmAsmOperand;
509 let DecoderMethod = "decodeUImmOperand<12>";
511 def PPCS16ImmAsmOperand : AsmOperandClass {
512 let Name = "S16Imm"; let PredicateMethod = "isS16Imm";
513 let RenderMethod = "addS16ImmOperands";
515 def s16imm : Operand<i32> {
516 let PrintMethod = "printS16ImmOperand";
517 let EncoderMethod = "getImm16Encoding";
518 let ParserMatchClass = PPCS16ImmAsmOperand;
519 let DecoderMethod = "decodeSImmOperand<16>";
521 def PPCU16ImmAsmOperand : AsmOperandClass {
522 let Name = "U16Imm"; let PredicateMethod = "isU16Imm";
523 let RenderMethod = "addU16ImmOperands";
525 def u16imm : Operand<i32> {
526 let PrintMethod = "printU16ImmOperand";
527 let EncoderMethod = "getImm16Encoding";
528 let ParserMatchClass = PPCU16ImmAsmOperand;
529 let DecoderMethod = "decodeUImmOperand<16>";
531 def PPCS17ImmAsmOperand : AsmOperandClass {
532 let Name = "S17Imm"; let PredicateMethod = "isS17Imm";
533 let RenderMethod = "addS16ImmOperands";
535 def s17imm : Operand<i32> {
536 // This operand type is used for addis/lis to allow the assembler parser
537 // to accept immediates in the range -65536..65535 for compatibility with
538 // the GNU assembler. The operand is treated as 16-bit otherwise.
539 let PrintMethod = "printS16ImmOperand";
540 let EncoderMethod = "getImm16Encoding";
541 let ParserMatchClass = PPCS17ImmAsmOperand;
542 let DecoderMethod = "decodeSImmOperand<16>";
544 def PPCDirectBrAsmOperand : AsmOperandClass {
545 let Name = "DirectBr"; let PredicateMethod = "isDirectBr";
546 let RenderMethod = "addBranchTargetOperands";
548 def directbrtarget : Operand<OtherVT> {
549 let PrintMethod = "printBranchOperand";
550 let EncoderMethod = "getDirectBrEncoding";
551 let ParserMatchClass = PPCDirectBrAsmOperand;
553 def absdirectbrtarget : Operand<OtherVT> {
554 let PrintMethod = "printAbsBranchOperand";
555 let EncoderMethod = "getAbsDirectBrEncoding";
556 let ParserMatchClass = PPCDirectBrAsmOperand;
558 def PPCCondBrAsmOperand : AsmOperandClass {
559 let Name = "CondBr"; let PredicateMethod = "isCondBr";
560 let RenderMethod = "addBranchTargetOperands";
562 def condbrtarget : Operand<OtherVT> {
563 let PrintMethod = "printBranchOperand";
564 let EncoderMethod = "getCondBrEncoding";
565 let ParserMatchClass = PPCCondBrAsmOperand;
567 def abscondbrtarget : Operand<OtherVT> {
568 let PrintMethod = "printAbsBranchOperand";
569 let EncoderMethod = "getAbsCondBrEncoding";
570 let ParserMatchClass = PPCCondBrAsmOperand;
572 def calltarget : Operand<iPTR> {
573 let PrintMethod = "printBranchOperand";
574 let EncoderMethod = "getDirectBrEncoding";
575 let ParserMatchClass = PPCDirectBrAsmOperand;
577 def abscalltarget : Operand<iPTR> {
578 let PrintMethod = "printAbsBranchOperand";
579 let EncoderMethod = "getAbsDirectBrEncoding";
580 let ParserMatchClass = PPCDirectBrAsmOperand;
582 def PPCCRBitMaskOperand : AsmOperandClass {
583 let Name = "CRBitMask"; let PredicateMethod = "isCRBitMask";
585 def crbitm: Operand<i8> {
586 let PrintMethod = "printcrbitm";
587 let EncoderMethod = "get_crbitm_encoding";
588 let DecoderMethod = "decodeCRBitMOperand";
589 let ParserMatchClass = PPCCRBitMaskOperand;
592 // A version of ptr_rc which excludes R0 (or X0 in 64-bit mode).
593 def PPCRegGxRCNoR0Operand : AsmOperandClass {
594 let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber";
596 def ptr_rc_nor0 : Operand<iPTR>, PointerLikeRegClass<1> {
597 let ParserMatchClass = PPCRegGxRCNoR0Operand;
599 // A version of ptr_rc usable with the asm parser.
600 def PPCRegGxRCOperand : AsmOperandClass {
601 let Name = "RegGxRC"; let PredicateMethod = "isRegNumber";
603 def ptr_rc_idx : Operand<iPTR>, PointerLikeRegClass<0> {
604 let ParserMatchClass = PPCRegGxRCOperand;
607 def PPCDispRIOperand : AsmOperandClass {
608 let Name = "DispRI"; let PredicateMethod = "isS16Imm";
609 let RenderMethod = "addS16ImmOperands";
611 def dispRI : Operand<iPTR> {
612 let ParserMatchClass = PPCDispRIOperand;
614 def PPCDispRIXOperand : AsmOperandClass {
615 let Name = "DispRIX"; let PredicateMethod = "isS16ImmX4";
616 let RenderMethod = "addImmOperands";
618 def dispRIX : Operand<iPTR> {
619 let ParserMatchClass = PPCDispRIXOperand;
621 def PPCDispSPE8Operand : AsmOperandClass {
622 let Name = "DispSPE8"; let PredicateMethod = "isU8ImmX8";
623 let RenderMethod = "addImmOperands";
625 def dispSPE8 : Operand<iPTR> {
626 let ParserMatchClass = PPCDispSPE8Operand;
628 def PPCDispSPE4Operand : AsmOperandClass {
629 let Name = "DispSPE4"; let PredicateMethod = "isU7ImmX4";
630 let RenderMethod = "addImmOperands";
632 def dispSPE4 : Operand<iPTR> {
633 let ParserMatchClass = PPCDispSPE4Operand;
635 def PPCDispSPE2Operand : AsmOperandClass {
636 let Name = "DispSPE2"; let PredicateMethod = "isU6ImmX2";
637 let RenderMethod = "addImmOperands";
639 def dispSPE2 : Operand<iPTR> {
640 let ParserMatchClass = PPCDispSPE2Operand;
643 def memri : Operand<iPTR> {
644 let PrintMethod = "printMemRegImm";
645 let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg);
646 let EncoderMethod = "getMemRIEncoding";
647 let DecoderMethod = "decodeMemRIOperands";
649 def memrr : Operand<iPTR> {
650 let PrintMethod = "printMemRegReg";
651 let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc_idx:$offreg);
653 def memrix : Operand<iPTR> { // memri where the imm is 4-aligned.
654 let PrintMethod = "printMemRegImm";
655 let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg);
656 let EncoderMethod = "getMemRIXEncoding";
657 let DecoderMethod = "decodeMemRIXOperands";
659 def spe8dis : Operand<iPTR> { // SPE displacement where the imm is 8-aligned.
660 let PrintMethod = "printMemRegImm";
661 let MIOperandInfo = (ops dispSPE8:$imm, ptr_rc_nor0:$reg);
662 let EncoderMethod = "getSPE8DisEncoding";
664 def spe4dis : Operand<iPTR> { // SPE displacement where the imm is 4-aligned.
665 let PrintMethod = "printMemRegImm";
666 let MIOperandInfo = (ops dispSPE4:$imm, ptr_rc_nor0:$reg);
667 let EncoderMethod = "getSPE4DisEncoding";
669 def spe2dis : Operand<iPTR> { // SPE displacement where the imm is 2-aligned.
670 let PrintMethod = "printMemRegImm";
671 let MIOperandInfo = (ops dispSPE2:$imm, ptr_rc_nor0:$reg);
672 let EncoderMethod = "getSPE2DisEncoding";
675 // A single-register address. This is used with the SjLj
676 // pseudo-instructions.
677 def memr : Operand<iPTR> {
678 let MIOperandInfo = (ops ptr_rc:$ptrreg);
680 def PPCTLSRegOperand : AsmOperandClass {
681 let Name = "TLSReg"; let PredicateMethod = "isTLSReg";
682 let RenderMethod = "addTLSRegOperands";
684 def tlsreg32 : Operand<i32> {
685 let EncoderMethod = "getTLSRegEncoding";
686 let ParserMatchClass = PPCTLSRegOperand;
688 def tlsgd32 : Operand<i32> {}
689 def tlscall32 : Operand<i32> {
690 let PrintMethod = "printTLSCall";
691 let MIOperandInfo = (ops calltarget:$func, tlsgd32:$sym);
692 let EncoderMethod = "getTLSCallEncoding";
695 // PowerPC Predicate operand.
696 def pred : Operand<OtherVT> {
697 let PrintMethod = "printPredicateOperand";
698 let MIOperandInfo = (ops i32imm:$bibo, crrc:$reg);
701 // Define PowerPC specific addressing mode.
702 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
703 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
704 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
705 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmX4", [], []>; // "std"
707 // The address in a single register. This is used with the SjLj
708 // pseudo-instructions.
709 def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>;
711 /// This is just the offset part of iaddr, used for preinc.
712 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
714 //===----------------------------------------------------------------------===//
715 // PowerPC Instruction Predicate Definitions.
716 def In32BitMode : Predicate<"!PPCSubTarget->isPPC64()">;
717 def In64BitMode : Predicate<"PPCSubTarget->isPPC64()">;
718 def IsBookE : Predicate<"PPCSubTarget->isBookE()">;
719 def IsNotBookE : Predicate<"!PPCSubTarget->isBookE()">;
720 def HasOnlyMSYNC : Predicate<"PPCSubTarget->hasOnlyMSYNC()">;
721 def HasSYNC : Predicate<"!PPCSubTarget->hasOnlyMSYNC()">;
722 def IsPPC4xx : Predicate<"PPCSubTarget->isPPC4xx()">;
723 def IsPPC6xx : Predicate<"PPCSubTarget->isPPC6xx()">;
724 def IsE500 : Predicate<"PPCSubTarget->isE500()">;
725 def HasSPE : Predicate<"PPCSubTarget->HasSPE()">;
726 def HasICBT : Predicate<"PPCSubTarget->hasICBT()">;
728 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
729 def NaNsFPMath : Predicate<"!TM.Options.NoNaNsFPMath">;
731 //===----------------------------------------------------------------------===//
732 // PowerPC Multiclass Definitions.
734 multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
735 string asmbase, string asmstr, InstrItinClass itin,
737 let BaseName = asmbase in {
738 def NAME : XForm_6<opcode, xo, OOL, IOL,
739 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
740 pattern>, RecFormRel;
742 def o : XForm_6<opcode, xo, OOL, IOL,
743 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
744 []>, isDOT, RecFormRel;
748 multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
749 string asmbase, string asmstr, InstrItinClass itin,
751 let BaseName = asmbase in {
752 let Defs = [CARRY] in
753 def NAME : XForm_6<opcode, xo, OOL, IOL,
754 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
755 pattern>, RecFormRel;
756 let Defs = [CARRY, CR0] in
757 def o : XForm_6<opcode, xo, OOL, IOL,
758 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
759 []>, isDOT, RecFormRel;
763 multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
764 string asmbase, string asmstr, InstrItinClass itin,
766 let BaseName = asmbase in {
767 let Defs = [CARRY] in
768 def NAME : XForm_10<opcode, xo, OOL, IOL,
769 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
770 pattern>, RecFormRel;
771 let Defs = [CARRY, CR0] in
772 def o : XForm_10<opcode, xo, OOL, IOL,
773 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
774 []>, isDOT, RecFormRel;
778 multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
779 string asmbase, string asmstr, InstrItinClass itin,
781 let BaseName = asmbase in {
782 def NAME : XForm_11<opcode, xo, OOL, IOL,
783 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
784 pattern>, RecFormRel;
786 def o : XForm_11<opcode, xo, OOL, IOL,
787 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
788 []>, isDOT, RecFormRel;
792 multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
793 string asmbase, string asmstr, InstrItinClass itin,
795 let BaseName = asmbase in {
796 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
797 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
798 pattern>, RecFormRel;
800 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
801 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
802 []>, isDOT, RecFormRel;
806 multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
807 string asmbase, string asmstr, InstrItinClass itin,
809 let BaseName = asmbase in {
810 let Defs = [CARRY] in
811 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
812 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
813 pattern>, RecFormRel;
814 let Defs = [CARRY, CR0] in
815 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
816 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
817 []>, isDOT, RecFormRel;
821 multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
822 string asmbase, string asmstr, InstrItinClass itin,
824 let BaseName = asmbase in {
825 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
826 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
827 pattern>, RecFormRel;
829 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
830 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
831 []>, isDOT, RecFormRel;
835 multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
836 string asmbase, string asmstr, InstrItinClass itin,
838 let BaseName = asmbase in {
839 let Defs = [CARRY] in
840 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
841 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
842 pattern>, RecFormRel;
843 let Defs = [CARRY, CR0] in
844 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
845 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
846 []>, isDOT, RecFormRel;
850 multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL,
851 string asmbase, string asmstr, InstrItinClass itin,
853 let BaseName = asmbase in {
854 def NAME : MForm_2<opcode, OOL, IOL,
855 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
856 pattern>, RecFormRel;
858 def o : MForm_2<opcode, OOL, IOL,
859 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
860 []>, isDOT, RecFormRel;
864 multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
865 string asmbase, string asmstr, InstrItinClass itin,
867 let BaseName = asmbase in {
868 def NAME : MDForm_1<opcode, xo, OOL, IOL,
869 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
870 pattern>, RecFormRel;
872 def o : MDForm_1<opcode, xo, OOL, IOL,
873 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
874 []>, isDOT, RecFormRel;
878 multiclass MDSForm_1r<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
879 string asmbase, string asmstr, InstrItinClass itin,
881 let BaseName = asmbase in {
882 def NAME : MDSForm_1<opcode, xo, OOL, IOL,
883 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
884 pattern>, RecFormRel;
886 def o : MDSForm_1<opcode, xo, OOL, IOL,
887 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
888 []>, isDOT, RecFormRel;
892 multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
893 string asmbase, string asmstr, InstrItinClass itin,
895 let BaseName = asmbase in {
896 let Defs = [CARRY] in
897 def NAME : XSForm_1<opcode, xo, OOL, IOL,
898 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
899 pattern>, RecFormRel;
900 let Defs = [CARRY, CR0] in
901 def o : XSForm_1<opcode, xo, OOL, IOL,
902 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
903 []>, isDOT, RecFormRel;
907 multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
908 string asmbase, string asmstr, InstrItinClass itin,
910 let BaseName = asmbase in {
911 def NAME : XForm_26<opcode, xo, OOL, IOL,
912 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
913 pattern>, RecFormRel;
915 def o : XForm_26<opcode, xo, OOL, IOL,
916 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
917 []>, isDOT, RecFormRel;
921 multiclass XForm_28r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
922 string asmbase, string asmstr, InstrItinClass itin,
924 let BaseName = asmbase in {
925 def NAME : XForm_28<opcode, xo, OOL, IOL,
926 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
927 pattern>, RecFormRel;
929 def o : XForm_28<opcode, xo, OOL, IOL,
930 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
931 []>, isDOT, RecFormRel;
935 multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
936 string asmbase, string asmstr, InstrItinClass itin,
938 let BaseName = asmbase in {
939 def NAME : AForm_1<opcode, xo, OOL, IOL,
940 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
941 pattern>, RecFormRel;
943 def o : AForm_1<opcode, xo, OOL, IOL,
944 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
945 []>, isDOT, RecFormRel;
949 multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
950 string asmbase, string asmstr, InstrItinClass itin,
952 let BaseName = asmbase in {
953 def NAME : AForm_2<opcode, xo, OOL, IOL,
954 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
955 pattern>, RecFormRel;
957 def o : AForm_2<opcode, xo, OOL, IOL,
958 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
959 []>, isDOT, RecFormRel;
963 multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
964 string asmbase, string asmstr, InstrItinClass itin,
966 let BaseName = asmbase in {
967 def NAME : AForm_3<opcode, xo, OOL, IOL,
968 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
969 pattern>, RecFormRel;
971 def o : AForm_3<opcode, xo, OOL, IOL,
972 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
973 []>, isDOT, RecFormRel;
977 //===----------------------------------------------------------------------===//
978 // PowerPC Instruction Definitions.
980 // Pseudo-instructions:
982 let hasCtrlDep = 1 in {
983 let Defs = [R1], Uses = [R1] in {
984 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt",
985 [(callseq_start timm:$amt)]>;
986 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt2",
987 [(callseq_end timm:$amt1, timm:$amt2)]>;
990 def UPDATE_VRSAVE : Pseudo<(outs gprc:$rD), (ins gprc:$rS),
991 "UPDATE_VRSAVE $rD, $rS", []>;
994 let Defs = [R1], Uses = [R1] in
995 def DYNALLOC : Pseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC",
997 (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>;
999 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
1000 // instruction selection into a branch sequence.
1001 let usesCustomInserter = 1, // Expanded after instruction selection.
1002 PPC970_Single = 1 in {
1003 // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes
1004 // because either operand might become the first operand in an isel, and
1005 // that operand cannot be r0.
1006 def SELECT_CC_I4 : Pseudo<(outs gprc:$dst), (ins crrc:$cond,
1007 gprc_nor0:$T, gprc_nor0:$F,
1008 i32imm:$BROPC), "#SELECT_CC_I4",
1010 def SELECT_CC_I8 : Pseudo<(outs g8rc:$dst), (ins crrc:$cond,
1011 g8rc_nox0:$T, g8rc_nox0:$F,
1012 i32imm:$BROPC), "#SELECT_CC_I8",
1014 def SELECT_CC_F4 : Pseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F,
1015 i32imm:$BROPC), "#SELECT_CC_F4",
1017 def SELECT_CC_F8 : Pseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F,
1018 i32imm:$BROPC), "#SELECT_CC_F8",
1020 def SELECT_CC_VRRC: Pseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F,
1021 i32imm:$BROPC), "#SELECT_CC_VRRC",
1024 // SELECT_* pseudo instructions, like SELECT_CC_* but taking condition
1025 // register bit directly.
1026 def SELECT_I4 : Pseudo<(outs gprc:$dst), (ins crbitrc:$cond,
1027 gprc_nor0:$T, gprc_nor0:$F), "#SELECT_I4",
1028 [(set i32:$dst, (select i1:$cond, i32:$T, i32:$F))]>;
1029 def SELECT_I8 : Pseudo<(outs g8rc:$dst), (ins crbitrc:$cond,
1030 g8rc_nox0:$T, g8rc_nox0:$F), "#SELECT_I8",
1031 [(set i64:$dst, (select i1:$cond, i64:$T, i64:$F))]>;
1032 def SELECT_F4 : Pseudo<(outs f4rc:$dst), (ins crbitrc:$cond,
1033 f4rc:$T, f4rc:$F), "#SELECT_F4",
1034 [(set f32:$dst, (select i1:$cond, f32:$T, f32:$F))]>;
1035 def SELECT_F8 : Pseudo<(outs f8rc:$dst), (ins crbitrc:$cond,
1036 f8rc:$T, f8rc:$F), "#SELECT_F8",
1037 [(set f64:$dst, (select i1:$cond, f64:$T, f64:$F))]>;
1038 def SELECT_VRRC: Pseudo<(outs vrrc:$dst), (ins crbitrc:$cond,
1039 vrrc:$T, vrrc:$F), "#SELECT_VRRC",
1041 (select i1:$cond, v4i32:$T, v4i32:$F))]>;
1044 // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
1045 // scavenge a register for it.
1046 let mayStore = 1 in {
1047 def SPILL_CR : Pseudo<(outs), (ins crrc:$cond, memri:$F),
1049 def SPILL_CRBIT : Pseudo<(outs), (ins crbitrc:$cond, memri:$F),
1050 "#SPILL_CRBIT", []>;
1053 // RESTORE_CR - Indicate that we're restoring the CR register (previously
1054 // spilled), so we'll need to scavenge a register for it.
1055 let mayLoad = 1 in {
1056 def RESTORE_CR : Pseudo<(outs crrc:$cond), (ins memri:$F),
1058 def RESTORE_CRBIT : Pseudo<(outs crbitrc:$cond), (ins memri:$F),
1059 "#RESTORE_CRBIT", []>;
1062 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
1063 let isReturn = 1, Uses = [LR, RM] in
1064 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB,
1065 [(retflag)]>, Requires<[In32BitMode]>;
1066 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in {
1067 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
1070 let isCodeGenOnly = 1 in {
1071 def BCCCTR : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
1072 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB,
1075 def BCCTR : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi),
1076 "bcctr 12, $bi, 0", IIC_BrB, []>;
1077 def BCCTRn : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi),
1078 "bcctr 4, $bi, 0", IIC_BrB, []>;
1084 def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>,
1087 def MoveGOTtoLR : Pseudo<(outs), (ins), "#MoveGOTtoLR", []>,
1090 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
1091 let isBarrier = 1 in {
1092 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst),
1095 def BA : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$dst),
1096 "ba $dst", IIC_BrB, []>;
1099 // BCC represents an arbitrary conditional branch on a predicate.
1100 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
1101 // a two-value operand where a dag node expects two operands. :(
1102 let isCodeGenOnly = 1 in {
1103 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst),
1104 "b${cond:cc}${cond:pm} ${cond:reg}, $dst"
1105 /*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$dst)]*/>;
1106 def BCCA : BForm<16, 1, 0, (outs), (ins pred:$cond, abscondbrtarget:$dst),
1107 "b${cond:cc}a${cond:pm} ${cond:reg}, $dst">;
1109 let isReturn = 1, Uses = [LR, RM] in
1110 def BCCLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$cond),
1111 "b${cond:cc}lr${cond:pm} ${cond:reg}", IIC_BrB, []>;
1114 let isCodeGenOnly = 1 in {
1115 let Pattern = [(brcond i1:$bi, bb:$dst)] in
1116 def BC : BForm_4<16, 12, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
1117 "bc 12, $bi, $dst">;
1119 let Pattern = [(brcond (not i1:$bi), bb:$dst)] in
1120 def BCn : BForm_4<16, 4, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
1123 let isReturn = 1, Uses = [LR, RM] in
1124 def BCLR : XLForm_2_br2<19, 16, 12, 0, (outs), (ins crbitrc:$bi),
1125 "bclr 12, $bi, 0", IIC_BrB, []>;
1126 def BCLRn : XLForm_2_br2<19, 16, 4, 0, (outs), (ins crbitrc:$bi),
1127 "bclr 4, $bi, 0", IIC_BrB, []>;
1130 let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in {
1131 def BDZLR : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
1132 "bdzlr", IIC_BrB, []>;
1133 def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
1134 "bdnzlr", IIC_BrB, []>;
1135 def BDZLRp : XLForm_2_ext<19, 16, 27, 0, 0, (outs), (ins),
1136 "bdzlr+", IIC_BrB, []>;
1137 def BDNZLRp: XLForm_2_ext<19, 16, 25, 0, 0, (outs), (ins),
1138 "bdnzlr+", IIC_BrB, []>;
1139 def BDZLRm : XLForm_2_ext<19, 16, 26, 0, 0, (outs), (ins),
1140 "bdzlr-", IIC_BrB, []>;
1141 def BDNZLRm: XLForm_2_ext<19, 16, 24, 0, 0, (outs), (ins),
1142 "bdnzlr-", IIC_BrB, []>;
1145 let Defs = [CTR], Uses = [CTR] in {
1146 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
1148 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
1150 def BDZA : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$dst),
1152 def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$dst),
1154 def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$dst),
1156 def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$dst),
1158 def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$dst),
1160 def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$dst),
1162 def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$dst),
1164 def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$dst),
1166 def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$dst),
1168 def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$dst),
1173 // The unconditional BCL used by the SjLj setjmp code.
1174 let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7 in {
1175 let Defs = [LR], Uses = [RM] in {
1176 def BCLalways : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst),
1177 "bcl 20, 31, $dst">;
1181 let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
1182 // Convenient aliases for call instructions
1183 let Uses = [RM] in {
1184 def BL : IForm<18, 0, 1, (outs), (ins calltarget:$func),
1185 "bl $func", IIC_BrB, []>; // See Pat patterns below.
1186 def BLA : IForm<18, 1, 1, (outs), (ins abscalltarget:$func),
1187 "bla $func", IIC_BrB, [(PPCcall (i32 imm:$func))]>;
1189 let isCodeGenOnly = 1 in {
1190 def BL_TLS : IForm<18, 0, 1, (outs), (ins tlscall32:$func),
1191 "bl $func", IIC_BrB, []>;
1192 def BCCL : BForm<16, 0, 1, (outs), (ins pred:$cond, condbrtarget:$dst),
1193 "b${cond:cc}l${cond:pm} ${cond:reg}, $dst">;
1194 def BCCLA : BForm<16, 1, 1, (outs), (ins pred:$cond, abscondbrtarget:$dst),
1195 "b${cond:cc}la${cond:pm} ${cond:reg}, $dst">;
1197 def BCL : BForm_4<16, 12, 0, 1, (outs),
1198 (ins crbitrc:$bi, condbrtarget:$dst),
1199 "bcl 12, $bi, $dst">;
1200 def BCLn : BForm_4<16, 4, 0, 1, (outs),
1201 (ins crbitrc:$bi, condbrtarget:$dst),
1202 "bcl 4, $bi, $dst">;
1205 let Uses = [CTR, RM] in {
1206 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
1207 "bctrl", IIC_BrB, [(PPCbctrl)]>,
1208 Requires<[In32BitMode]>;
1210 let isCodeGenOnly = 1 in {
1211 def BCCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
1212 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB,
1215 def BCCTRL : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi),
1216 "bcctrl 12, $bi, 0", IIC_BrB, []>;
1217 def BCCTRLn : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi),
1218 "bcctrl 4, $bi, 0", IIC_BrB, []>;
1221 let Uses = [LR, RM] in {
1222 def BLRL : XLForm_2_ext<19, 16, 20, 0, 1, (outs), (ins),
1223 "blrl", IIC_BrB, []>;
1225 let isCodeGenOnly = 1 in {
1226 def BCCLRL : XLForm_2_br<19, 16, 1, (outs), (ins pred:$cond),
1227 "b${cond:cc}lrl${cond:pm} ${cond:reg}", IIC_BrB,
1230 def BCLRL : XLForm_2_br2<19, 16, 12, 1, (outs), (ins crbitrc:$bi),
1231 "bclrl 12, $bi, 0", IIC_BrB, []>;
1232 def BCLRLn : XLForm_2_br2<19, 16, 4, 1, (outs), (ins crbitrc:$bi),
1233 "bclrl 4, $bi, 0", IIC_BrB, []>;
1236 let Defs = [CTR], Uses = [CTR, RM] in {
1237 def BDZL : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$dst),
1239 def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$dst),
1241 def BDZLA : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$dst),
1243 def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$dst),
1245 def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$dst),
1247 def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$dst),
1249 def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$dst),
1251 def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$dst),
1253 def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$dst),
1255 def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$dst),
1257 def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$dst),
1259 def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$dst),
1262 let Defs = [CTR], Uses = [CTR, LR, RM] in {
1263 def BDZLRL : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins),
1264 "bdzlrl", IIC_BrB, []>;
1265 def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins),
1266 "bdnzlrl", IIC_BrB, []>;
1267 def BDZLRLp : XLForm_2_ext<19, 16, 27, 0, 1, (outs), (ins),
1268 "bdzlrl+", IIC_BrB, []>;
1269 def BDNZLRLp: XLForm_2_ext<19, 16, 25, 0, 1, (outs), (ins),
1270 "bdnzlrl+", IIC_BrB, []>;
1271 def BDZLRLm : XLForm_2_ext<19, 16, 26, 0, 1, (outs), (ins),
1272 "bdzlrl-", IIC_BrB, []>;
1273 def BDNZLRLm: XLForm_2_ext<19, 16, 24, 0, 1, (outs), (ins),
1274 "bdnzlrl-", IIC_BrB, []>;
1278 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1279 def TCRETURNdi :Pseudo< (outs),
1280 (ins calltarget:$dst, i32imm:$offset),
1281 "#TC_RETURNd $dst $offset",
1285 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1286 def TCRETURNai :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
1287 "#TC_RETURNa $func $offset",
1288 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
1290 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1291 def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset),
1292 "#TC_RETURNr $dst $offset",
1296 let isCodeGenOnly = 1 in {
1298 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
1299 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in
1300 def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
1301 []>, Requires<[In32BitMode]>;
1303 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1304 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1305 def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
1309 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1310 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1311 def TAILBA : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst),
1317 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
1319 def EH_SjLj_SetJmp32 : Pseudo<(outs gprc:$dst), (ins memr:$buf),
1320 "#EH_SJLJ_SETJMP32",
1321 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
1322 Requires<[In32BitMode]>;
1323 let isTerminator = 1 in
1324 def EH_SjLj_LongJmp32 : Pseudo<(outs), (ins memr:$buf),
1325 "#EH_SJLJ_LONGJMP32",
1326 [(PPCeh_sjlj_longjmp addr:$buf)]>,
1327 Requires<[In32BitMode]>;
1330 let isBranch = 1, isTerminator = 1 in {
1331 def EH_SjLj_Setup : Pseudo<(outs), (ins directbrtarget:$dst),
1332 "#EH_SjLj_Setup\t$dst", []>;
1336 let PPC970_Unit = 7 in {
1337 def SC : SCForm<17, 1, (outs), (ins i32imm:$lev),
1338 "sc $lev", IIC_BrB, [(PPCsc (i32 imm:$lev))]>;
1341 // DCB* instructions.
1342 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst), "dcba $dst",
1343 IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
1344 PPC970_DGroup_Single;
1345 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst), "dcbf $dst",
1346 IIC_LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
1347 PPC970_DGroup_Single;
1348 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst), "dcbi $dst",
1349 IIC_LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
1350 PPC970_DGroup_Single;
1351 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst), "dcbst $dst",
1352 IIC_LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
1353 PPC970_DGroup_Single;
1354 def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst), "dcbt $dst",
1355 IIC_LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
1356 PPC970_DGroup_Single;
1357 def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst), "dcbtst $dst",
1358 IIC_LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
1359 PPC970_DGroup_Single;
1360 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst), "dcbz $dst",
1361 IIC_LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
1362 PPC970_DGroup_Single;
1363 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), "dcbzl $dst",
1364 IIC_LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
1365 PPC970_DGroup_Single;
1367 def ICBT : XForm_icbt<31, 22, (outs), (ins u4imm:$CT, memrr:$src),
1368 "icbt $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>;
1370 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
1371 (DCBT xoaddr:$dst)>; // data prefetch for loads
1372 def : Pat<(prefetch xoaddr:$dst, (i32 1), imm, (i32 1)),
1373 (DCBTST xoaddr:$dst)>; // data prefetch for stores
1374 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 0)),
1375 (ICBT 0, xoaddr:$dst)>, Requires<[HasICBT]>; // inst prefetch (for read)
1377 // Atomic operations
1378 let usesCustomInserter = 1 in {
1379 let Defs = [CR0] in {
1380 def ATOMIC_LOAD_ADD_I8 : Pseudo<
1381 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I8",
1382 [(set i32:$dst, (atomic_load_add_8 xoaddr:$ptr, i32:$incr))]>;
1383 def ATOMIC_LOAD_SUB_I8 : Pseudo<
1384 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I8",
1385 [(set i32:$dst, (atomic_load_sub_8 xoaddr:$ptr, i32:$incr))]>;
1386 def ATOMIC_LOAD_AND_I8 : Pseudo<
1387 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I8",
1388 [(set i32:$dst, (atomic_load_and_8 xoaddr:$ptr, i32:$incr))]>;
1389 def ATOMIC_LOAD_OR_I8 : Pseudo<
1390 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I8",
1391 [(set i32:$dst, (atomic_load_or_8 xoaddr:$ptr, i32:$incr))]>;
1392 def ATOMIC_LOAD_XOR_I8 : Pseudo<
1393 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "ATOMIC_LOAD_XOR_I8",
1394 [(set i32:$dst, (atomic_load_xor_8 xoaddr:$ptr, i32:$incr))]>;
1395 def ATOMIC_LOAD_NAND_I8 : Pseudo<
1396 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8",
1397 [(set i32:$dst, (atomic_load_nand_8 xoaddr:$ptr, i32:$incr))]>;
1398 def ATOMIC_LOAD_ADD_I16 : Pseudo<
1399 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16",
1400 [(set i32:$dst, (atomic_load_add_16 xoaddr:$ptr, i32:$incr))]>;
1401 def ATOMIC_LOAD_SUB_I16 : Pseudo<
1402 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I16",
1403 [(set i32:$dst, (atomic_load_sub_16 xoaddr:$ptr, i32:$incr))]>;
1404 def ATOMIC_LOAD_AND_I16 : Pseudo<
1405 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I16",
1406 [(set i32:$dst, (atomic_load_and_16 xoaddr:$ptr, i32:$incr))]>;
1407 def ATOMIC_LOAD_OR_I16 : Pseudo<
1408 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I16",
1409 [(set i32:$dst, (atomic_load_or_16 xoaddr:$ptr, i32:$incr))]>;
1410 def ATOMIC_LOAD_XOR_I16 : Pseudo<
1411 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I16",
1412 [(set i32:$dst, (atomic_load_xor_16 xoaddr:$ptr, i32:$incr))]>;
1413 def ATOMIC_LOAD_NAND_I16 : Pseudo<
1414 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I16",
1415 [(set i32:$dst, (atomic_load_nand_16 xoaddr:$ptr, i32:$incr))]>;
1416 def ATOMIC_LOAD_ADD_I32 : Pseudo<
1417 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I32",
1418 [(set i32:$dst, (atomic_load_add_32 xoaddr:$ptr, i32:$incr))]>;
1419 def ATOMIC_LOAD_SUB_I32 : Pseudo<
1420 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I32",
1421 [(set i32:$dst, (atomic_load_sub_32 xoaddr:$ptr, i32:$incr))]>;
1422 def ATOMIC_LOAD_AND_I32 : Pseudo<
1423 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I32",
1424 [(set i32:$dst, (atomic_load_and_32 xoaddr:$ptr, i32:$incr))]>;
1425 def ATOMIC_LOAD_OR_I32 : Pseudo<
1426 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I32",
1427 [(set i32:$dst, (atomic_load_or_32 xoaddr:$ptr, i32:$incr))]>;
1428 def ATOMIC_LOAD_XOR_I32 : Pseudo<
1429 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I32",
1430 [(set i32:$dst, (atomic_load_xor_32 xoaddr:$ptr, i32:$incr))]>;
1431 def ATOMIC_LOAD_NAND_I32 : Pseudo<
1432 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I32",
1433 [(set i32:$dst, (atomic_load_nand_32 xoaddr:$ptr, i32:$incr))]>;
1435 def ATOMIC_CMP_SWAP_I8 : Pseudo<
1436 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I8",
1437 [(set i32:$dst, (atomic_cmp_swap_8 xoaddr:$ptr, i32:$old, i32:$new))]>;
1438 def ATOMIC_CMP_SWAP_I16 : Pseudo<
1439 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new",
1440 [(set i32:$dst, (atomic_cmp_swap_16 xoaddr:$ptr, i32:$old, i32:$new))]>;
1441 def ATOMIC_CMP_SWAP_I32 : Pseudo<
1442 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new",
1443 [(set i32:$dst, (atomic_cmp_swap_32 xoaddr:$ptr, i32:$old, i32:$new))]>;
1445 def ATOMIC_SWAP_I8 : Pseudo<
1446 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_i8",
1447 [(set i32:$dst, (atomic_swap_8 xoaddr:$ptr, i32:$new))]>;
1448 def ATOMIC_SWAP_I16 : Pseudo<
1449 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I16",
1450 [(set i32:$dst, (atomic_swap_16 xoaddr:$ptr, i32:$new))]>;
1451 def ATOMIC_SWAP_I32 : Pseudo<
1452 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I32",
1453 [(set i32:$dst, (atomic_swap_32 xoaddr:$ptr, i32:$new))]>;
1457 // Instructions to support atomic operations
1458 def LWARX : XForm_1<31, 20, (outs gprc:$rD), (ins memrr:$src),
1459 "lwarx $rD, $src", IIC_LdStLWARX,
1460 [(set i32:$rD, (PPClarx xoaddr:$src))]>;
1463 def STWCX : XForm_1<31, 150, (outs), (ins gprc:$rS, memrr:$dst),
1464 "stwcx. $rS, $dst", IIC_LdStSTWCX,
1465 [(PPCstcx i32:$rS, xoaddr:$dst)]>,
1468 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
1469 def TRAP : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>;
1471 def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm),
1472 "twi $to, $rA, $imm", IIC_IntTrapW, []>;
1473 def TW : XForm_1<31, 4, (outs), (ins u5imm:$to, gprc:$rA, gprc:$rB),
1474 "tw $to, $rA, $rB", IIC_IntTrapW, []>;
1475 def TDI : DForm_base<2, (outs), (ins u5imm:$to, g8rc:$rA, s16imm:$imm),
1476 "tdi $to, $rA, $imm", IIC_IntTrapD, []>;
1477 def TD : XForm_1<31, 68, (outs), (ins u5imm:$to, g8rc:$rA, g8rc:$rB),
1478 "td $to, $rA, $rB", IIC_IntTrapD, []>;
1480 //===----------------------------------------------------------------------===//
1481 // PPC32 Load Instructions.
1484 // Unindexed (r+i) Loads.
1485 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
1486 def LBZ : DForm_1<34, (outs gprc:$rD), (ins memri:$src),
1487 "lbz $rD, $src", IIC_LdStLoad,
1488 [(set i32:$rD, (zextloadi8 iaddr:$src))]>;
1489 def LHA : DForm_1<42, (outs gprc:$rD), (ins memri:$src),
1490 "lha $rD, $src", IIC_LdStLHA,
1491 [(set i32:$rD, (sextloadi16 iaddr:$src))]>,
1492 PPC970_DGroup_Cracked;
1493 def LHZ : DForm_1<40, (outs gprc:$rD), (ins memri:$src),
1494 "lhz $rD, $src", IIC_LdStLoad,
1495 [(set i32:$rD, (zextloadi16 iaddr:$src))]>;
1496 def LWZ : DForm_1<32, (outs gprc:$rD), (ins memri:$src),
1497 "lwz $rD, $src", IIC_LdStLoad,
1498 [(set i32:$rD, (load iaddr:$src))]>;
1500 def LFS : DForm_1<48, (outs f4rc:$rD), (ins memri:$src),
1501 "lfs $rD, $src", IIC_LdStLFD,
1502 [(set f32:$rD, (load iaddr:$src))]>;
1503 def LFD : DForm_1<50, (outs f8rc:$rD), (ins memri:$src),
1504 "lfd $rD, $src", IIC_LdStLFD,
1505 [(set f64:$rD, (load iaddr:$src))]>;
1508 // Unindexed (r+i) Loads with Update (preinc).
1509 let mayLoad = 1, hasSideEffects = 0 in {
1510 def LBZU : DForm_1<35, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1511 "lbzu $rD, $addr", IIC_LdStLoadUpd,
1512 []>, RegConstraint<"$addr.reg = $ea_result">,
1513 NoEncode<"$ea_result">;
1515 def LHAU : DForm_1<43, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1516 "lhau $rD, $addr", IIC_LdStLHAU,
1517 []>, RegConstraint<"$addr.reg = $ea_result">,
1518 NoEncode<"$ea_result">;
1520 def LHZU : DForm_1<41, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1521 "lhzu $rD, $addr", IIC_LdStLoadUpd,
1522 []>, RegConstraint<"$addr.reg = $ea_result">,
1523 NoEncode<"$ea_result">;
1525 def LWZU : DForm_1<33, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1526 "lwzu $rD, $addr", IIC_LdStLoadUpd,
1527 []>, RegConstraint<"$addr.reg = $ea_result">,
1528 NoEncode<"$ea_result">;
1530 def LFSU : DForm_1<49, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1531 "lfsu $rD, $addr", IIC_LdStLFDU,
1532 []>, RegConstraint<"$addr.reg = $ea_result">,
1533 NoEncode<"$ea_result">;
1535 def LFDU : DForm_1<51, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1536 "lfdu $rD, $addr", IIC_LdStLFDU,
1537 []>, RegConstraint<"$addr.reg = $ea_result">,
1538 NoEncode<"$ea_result">;
1541 // Indexed (r+r) Loads with Update (preinc).
1542 def LBZUX : XForm_1<31, 119, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1544 "lbzux $rD, $addr", IIC_LdStLoadUpdX,
1545 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1546 NoEncode<"$ea_result">;
1548 def LHAUX : XForm_1<31, 375, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1550 "lhaux $rD, $addr", IIC_LdStLHAUX,
1551 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1552 NoEncode<"$ea_result">;
1554 def LHZUX : XForm_1<31, 311, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1556 "lhzux $rD, $addr", IIC_LdStLoadUpdX,
1557 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1558 NoEncode<"$ea_result">;
1560 def LWZUX : XForm_1<31, 55, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1562 "lwzux $rD, $addr", IIC_LdStLoadUpdX,
1563 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1564 NoEncode<"$ea_result">;
1566 def LFSUX : XForm_1<31, 567, (outs f4rc:$rD, ptr_rc_nor0:$ea_result),
1568 "lfsux $rD, $addr", IIC_LdStLFDUX,
1569 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1570 NoEncode<"$ea_result">;
1572 def LFDUX : XForm_1<31, 631, (outs f8rc:$rD, ptr_rc_nor0:$ea_result),
1574 "lfdux $rD, $addr", IIC_LdStLFDUX,
1575 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1576 NoEncode<"$ea_result">;
1580 // Indexed (r+r) Loads.
1582 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
1583 def LBZX : XForm_1<31, 87, (outs gprc:$rD), (ins memrr:$src),
1584 "lbzx $rD, $src", IIC_LdStLoad,
1585 [(set i32:$rD, (zextloadi8 xaddr:$src))]>;
1586 def LHAX : XForm_1<31, 343, (outs gprc:$rD), (ins memrr:$src),
1587 "lhax $rD, $src", IIC_LdStLHA,
1588 [(set i32:$rD, (sextloadi16 xaddr:$src))]>,
1589 PPC970_DGroup_Cracked;
1590 def LHZX : XForm_1<31, 279, (outs gprc:$rD), (ins memrr:$src),
1591 "lhzx $rD, $src", IIC_LdStLoad,
1592 [(set i32:$rD, (zextloadi16 xaddr:$src))]>;
1593 def LWZX : XForm_1<31, 23, (outs gprc:$rD), (ins memrr:$src),
1594 "lwzx $rD, $src", IIC_LdStLoad,
1595 [(set i32:$rD, (load xaddr:$src))]>;
1598 def LHBRX : XForm_1<31, 790, (outs gprc:$rD), (ins memrr:$src),
1599 "lhbrx $rD, $src", IIC_LdStLoad,
1600 [(set i32:$rD, (PPClbrx xoaddr:$src, i16))]>;
1601 def LWBRX : XForm_1<31, 534, (outs gprc:$rD), (ins memrr:$src),
1602 "lwbrx $rD, $src", IIC_LdStLoad,
1603 [(set i32:$rD, (PPClbrx xoaddr:$src, i32))]>;
1605 def LFSX : XForm_25<31, 535, (outs f4rc:$frD), (ins memrr:$src),
1606 "lfsx $frD, $src", IIC_LdStLFD,
1607 [(set f32:$frD, (load xaddr:$src))]>;
1608 def LFDX : XForm_25<31, 599, (outs f8rc:$frD), (ins memrr:$src),
1609 "lfdx $frD, $src", IIC_LdStLFD,
1610 [(set f64:$frD, (load xaddr:$src))]>;
1612 def LFIWAX : XForm_25<31, 855, (outs f8rc:$frD), (ins memrr:$src),
1613 "lfiwax $frD, $src", IIC_LdStLFD,
1614 [(set f64:$frD, (PPClfiwax xoaddr:$src))]>;
1615 def LFIWZX : XForm_25<31, 887, (outs f8rc:$frD), (ins memrr:$src),
1616 "lfiwzx $frD, $src", IIC_LdStLFD,
1617 [(set f64:$frD, (PPClfiwzx xoaddr:$src))]>;
1621 def LMW : DForm_1<46, (outs gprc:$rD), (ins memri:$src),
1622 "lmw $rD, $src", IIC_LdStLMW, []>;
1624 //===----------------------------------------------------------------------===//
1625 // PPC32 Store Instructions.
1628 // Unindexed (r+i) Stores.
1629 let PPC970_Unit = 2 in {
1630 def STB : DForm_1<38, (outs), (ins gprc:$rS, memri:$src),
1631 "stb $rS, $src", IIC_LdStStore,
1632 [(truncstorei8 i32:$rS, iaddr:$src)]>;
1633 def STH : DForm_1<44, (outs), (ins gprc:$rS, memri:$src),
1634 "sth $rS, $src", IIC_LdStStore,
1635 [(truncstorei16 i32:$rS, iaddr:$src)]>;
1636 def STW : DForm_1<36, (outs), (ins gprc:$rS, memri:$src),
1637 "stw $rS, $src", IIC_LdStStore,
1638 [(store i32:$rS, iaddr:$src)]>;
1639 def STFS : DForm_1<52, (outs), (ins f4rc:$rS, memri:$dst),
1640 "stfs $rS, $dst", IIC_LdStSTFD,
1641 [(store f32:$rS, iaddr:$dst)]>;
1642 def STFD : DForm_1<54, (outs), (ins f8rc:$rS, memri:$dst),
1643 "stfd $rS, $dst", IIC_LdStSTFD,
1644 [(store f64:$rS, iaddr:$dst)]>;
1647 // Unindexed (r+i) Stores with Update (preinc).
1648 let PPC970_Unit = 2, mayStore = 1 in {
1649 def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1650 "stbu $rS, $dst", IIC_LdStStoreUpd, []>,
1651 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1652 def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1653 "sthu $rS, $dst", IIC_LdStStoreUpd, []>,
1654 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1655 def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1656 "stwu $rS, $dst", IIC_LdStStoreUpd, []>,
1657 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1658 def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memri:$dst),
1659 "stfsu $rS, $dst", IIC_LdStSTFDU, []>,
1660 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1661 def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memri:$dst),
1662 "stfdu $rS, $dst", IIC_LdStSTFDU, []>,
1663 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1666 // Patterns to match the pre-inc stores. We can't put the patterns on
1667 // the instruction definitions directly as ISel wants the address base
1668 // and offset to be separate operands, not a single complex operand.
1669 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1670 (STBU $rS, iaddroff:$ptroff, $ptrreg)>;
1671 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1672 (STHU $rS, iaddroff:$ptroff, $ptrreg)>;
1673 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1674 (STWU $rS, iaddroff:$ptroff, $ptrreg)>;
1675 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1676 (STFSU $rS, iaddroff:$ptroff, $ptrreg)>;
1677 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1678 (STFDU $rS, iaddroff:$ptroff, $ptrreg)>;
1680 // Indexed (r+r) Stores.
1681 let PPC970_Unit = 2 in {
1682 def STBX : XForm_8<31, 215, (outs), (ins gprc:$rS, memrr:$dst),
1683 "stbx $rS, $dst", IIC_LdStStore,
1684 [(truncstorei8 i32:$rS, xaddr:$dst)]>,
1685 PPC970_DGroup_Cracked;
1686 def STHX : XForm_8<31, 407, (outs), (ins gprc:$rS, memrr:$dst),
1687 "sthx $rS, $dst", IIC_LdStStore,
1688 [(truncstorei16 i32:$rS, xaddr:$dst)]>,
1689 PPC970_DGroup_Cracked;
1690 def STWX : XForm_8<31, 151, (outs), (ins gprc:$rS, memrr:$dst),
1691 "stwx $rS, $dst", IIC_LdStStore,
1692 [(store i32:$rS, xaddr:$dst)]>,
1693 PPC970_DGroup_Cracked;
1695 def STHBRX: XForm_8<31, 918, (outs), (ins gprc:$rS, memrr:$dst),
1696 "sthbrx $rS, $dst", IIC_LdStStore,
1697 [(PPCstbrx i32:$rS, xoaddr:$dst, i16)]>,
1698 PPC970_DGroup_Cracked;
1699 def STWBRX: XForm_8<31, 662, (outs), (ins gprc:$rS, memrr:$dst),
1700 "stwbrx $rS, $dst", IIC_LdStStore,
1701 [(PPCstbrx i32:$rS, xoaddr:$dst, i32)]>,
1702 PPC970_DGroup_Cracked;
1704 def STFIWX: XForm_28<31, 983, (outs), (ins f8rc:$frS, memrr:$dst),
1705 "stfiwx $frS, $dst", IIC_LdStSTFD,
1706 [(PPCstfiwx f64:$frS, xoaddr:$dst)]>;
1708 def STFSX : XForm_28<31, 663, (outs), (ins f4rc:$frS, memrr:$dst),
1709 "stfsx $frS, $dst", IIC_LdStSTFD,
1710 [(store f32:$frS, xaddr:$dst)]>;
1711 def STFDX : XForm_28<31, 727, (outs), (ins f8rc:$frS, memrr:$dst),
1712 "stfdx $frS, $dst", IIC_LdStSTFD,
1713 [(store f64:$frS, xaddr:$dst)]>;
1716 // Indexed (r+r) Stores with Update (preinc).
1717 let PPC970_Unit = 2, mayStore = 1 in {
1718 def STBUX : XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1719 "stbux $rS, $dst", IIC_LdStStoreUpd, []>,
1720 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1721 PPC970_DGroup_Cracked;
1722 def STHUX : XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1723 "sthux $rS, $dst", IIC_LdStStoreUpd, []>,
1724 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1725 PPC970_DGroup_Cracked;
1726 def STWUX : XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1727 "stwux $rS, $dst", IIC_LdStStoreUpd, []>,
1728 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1729 PPC970_DGroup_Cracked;
1730 def STFSUX: XForm_8<31, 695, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memrr:$dst),
1731 "stfsux $rS, $dst", IIC_LdStSTFDU, []>,
1732 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1733 PPC970_DGroup_Cracked;
1734 def STFDUX: XForm_8<31, 759, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memrr:$dst),
1735 "stfdux $rS, $dst", IIC_LdStSTFDU, []>,
1736 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1737 PPC970_DGroup_Cracked;
1740 // Patterns to match the pre-inc stores. We can't put the patterns on
1741 // the instruction definitions directly as ISel wants the address base
1742 // and offset to be separate operands, not a single complex operand.
1743 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1744 (STBUX $rS, $ptrreg, $ptroff)>;
1745 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1746 (STHUX $rS, $ptrreg, $ptroff)>;
1747 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1748 (STWUX $rS, $ptrreg, $ptroff)>;
1749 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1750 (STFSUX $rS, $ptrreg, $ptroff)>;
1751 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1752 (STFDUX $rS, $ptrreg, $ptroff)>;
1755 def STMW : DForm_1<47, (outs), (ins gprc:$rS, memri:$dst),
1756 "stmw $rS, $dst", IIC_LdStLMW, []>;
1758 def SYNC : XForm_24_sync<31, 598, (outs), (ins i32imm:$L),
1759 "sync $L", IIC_LdStSync, []>;
1761 let isCodeGenOnly = 1 in {
1762 def MSYNC : XForm_24_sync<31, 598, (outs), (ins),
1763 "msync", IIC_LdStSync, []> {
1768 def : Pat<(int_ppc_sync), (SYNC 0)>, Requires<[HasSYNC]>;
1769 def : Pat<(int_ppc_lwsync), (SYNC 1)>, Requires<[HasSYNC]>;
1770 def : Pat<(int_ppc_sync), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
1771 def : Pat<(int_ppc_lwsync), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
1773 //===----------------------------------------------------------------------===//
1774 // PPC32 Arithmetic Instructions.
1777 let PPC970_Unit = 1 in { // FXU Operations.
1778 def ADDI : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$imm),
1779 "addi $rD, $rA, $imm", IIC_IntSimple,
1780 [(set i32:$rD, (add i32:$rA, imm32SExt16:$imm))]>;
1781 let BaseName = "addic" in {
1782 let Defs = [CARRY] in
1783 def ADDIC : DForm_2<12, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1784 "addic $rD, $rA, $imm", IIC_IntGeneral,
1785 [(set i32:$rD, (addc i32:$rA, imm32SExt16:$imm))]>,
1786 RecFormRel, PPC970_DGroup_Cracked;
1787 let Defs = [CARRY, CR0] in
1788 def ADDICo : DForm_2<13, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1789 "addic. $rD, $rA, $imm", IIC_IntGeneral,
1790 []>, isDOT, RecFormRel;
1792 def ADDIS : DForm_2<15, (outs gprc:$rD), (ins gprc_nor0:$rA, s17imm:$imm),
1793 "addis $rD, $rA, $imm", IIC_IntSimple,
1794 [(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>;
1795 let isCodeGenOnly = 1 in
1796 def LA : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$sym),
1797 "la $rD, $sym($rA)", IIC_IntGeneral,
1798 [(set i32:$rD, (add i32:$rA,
1799 (PPClo tglobaladdr:$sym, 0)))]>;
1800 def MULLI : DForm_2< 7, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1801 "mulli $rD, $rA, $imm", IIC_IntMulLI,
1802 [(set i32:$rD, (mul i32:$rA, imm32SExt16:$imm))]>;
1803 let Defs = [CARRY] in
1804 def SUBFIC : DForm_2< 8, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1805 "subfic $rD, $rA, $imm", IIC_IntGeneral,
1806 [(set i32:$rD, (subc imm32SExt16:$imm, i32:$rA))]>;
1808 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
1809 def LI : DForm_2_r0<14, (outs gprc:$rD), (ins s16imm:$imm),
1810 "li $rD, $imm", IIC_IntSimple,
1811 [(set i32:$rD, imm32SExt16:$imm)]>;
1812 def LIS : DForm_2_r0<15, (outs gprc:$rD), (ins s17imm:$imm),
1813 "lis $rD, $imm", IIC_IntSimple,
1814 [(set i32:$rD, imm16ShiftedSExt:$imm)]>;
1818 let PPC970_Unit = 1 in { // FXU Operations.
1819 let Defs = [CR0] in {
1820 def ANDIo : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1821 "andi. $dst, $src1, $src2", IIC_IntGeneral,
1822 [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>,
1824 def ANDISo : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1825 "andis. $dst, $src1, $src2", IIC_IntGeneral,
1826 [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>,
1829 def ORI : DForm_4<24, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1830 "ori $dst, $src1, $src2", IIC_IntSimple,
1831 [(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>;
1832 def ORIS : DForm_4<25, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1833 "oris $dst, $src1, $src2", IIC_IntSimple,
1834 [(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>;
1835 def XORI : DForm_4<26, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1836 "xori $dst, $src1, $src2", IIC_IntSimple,
1837 [(set i32:$dst, (xor i32:$src1, immZExt16:$src2))]>;
1838 def XORIS : DForm_4<27, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1839 "xoris $dst, $src1, $src2", IIC_IntSimple,
1840 [(set i32:$dst, (xor i32:$src1, imm16ShiftedZExt:$src2))]>;
1842 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IIC_IntSimple,
1844 let isCodeGenOnly = 1 in {
1845 // The POWER6 and POWER7 have special group-terminating nops.
1846 def NOP_GT_PWR6 : DForm_4_fixedreg_zero<24, 1, (outs), (ins),
1847 "ori 1, 1, 0", IIC_IntSimple, []>;
1848 def NOP_GT_PWR7 : DForm_4_fixedreg_zero<24, 2, (outs), (ins),
1849 "ori 2, 2, 0", IIC_IntSimple, []>;
1852 let isCompare = 1, hasSideEffects = 0 in {
1853 def CMPWI : DForm_5_ext<11, (outs crrc:$crD), (ins gprc:$rA, s16imm:$imm),
1854 "cmpwi $crD, $rA, $imm", IIC_IntCompare>;
1855 def CMPLWI : DForm_6_ext<10, (outs crrc:$dst), (ins gprc:$src1, u16imm:$src2),
1856 "cmplwi $dst, $src1, $src2", IIC_IntCompare>;
1860 let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations.
1861 let isCommutable = 1 in {
1862 defm NAND : XForm_6r<31, 476, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1863 "nand", "$rA, $rS, $rB", IIC_IntSimple,
1864 [(set i32:$rA, (not (and i32:$rS, i32:$rB)))]>;
1865 defm AND : XForm_6r<31, 28, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1866 "and", "$rA, $rS, $rB", IIC_IntSimple,
1867 [(set i32:$rA, (and i32:$rS, i32:$rB))]>;
1869 defm ANDC : XForm_6r<31, 60, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1870 "andc", "$rA, $rS, $rB", IIC_IntSimple,
1871 [(set i32:$rA, (and i32:$rS, (not i32:$rB)))]>;
1872 let isCommutable = 1 in {
1873 defm OR : XForm_6r<31, 444, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1874 "or", "$rA, $rS, $rB", IIC_IntSimple,
1875 [(set i32:$rA, (or i32:$rS, i32:$rB))]>;
1876 defm NOR : XForm_6r<31, 124, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1877 "nor", "$rA, $rS, $rB", IIC_IntSimple,
1878 [(set i32:$rA, (not (or i32:$rS, i32:$rB)))]>;
1880 defm ORC : XForm_6r<31, 412, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1881 "orc", "$rA, $rS, $rB", IIC_IntSimple,
1882 [(set i32:$rA, (or i32:$rS, (not i32:$rB)))]>;
1883 let isCommutable = 1 in {
1884 defm EQV : XForm_6r<31, 284, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1885 "eqv", "$rA, $rS, $rB", IIC_IntSimple,
1886 [(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>;
1887 defm XOR : XForm_6r<31, 316, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1888 "xor", "$rA, $rS, $rB", IIC_IntSimple,
1889 [(set i32:$rA, (xor i32:$rS, i32:$rB))]>;
1891 defm SLW : XForm_6r<31, 24, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1892 "slw", "$rA, $rS, $rB", IIC_IntGeneral,
1893 [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>;
1894 defm SRW : XForm_6r<31, 536, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1895 "srw", "$rA, $rS, $rB", IIC_IntGeneral,
1896 [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>;
1897 defm SRAW : XForm_6rc<31, 792, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1898 "sraw", "$rA, $rS, $rB", IIC_IntShift,
1899 [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>;
1902 let PPC970_Unit = 1 in { // FXU Operations.
1903 let hasSideEffects = 0 in {
1904 defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH),
1905 "srawi", "$rA, $rS, $SH", IIC_IntShift,
1906 [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>;
1907 defm CNTLZW : XForm_11r<31, 26, (outs gprc:$rA), (ins gprc:$rS),
1908 "cntlzw", "$rA, $rS", IIC_IntGeneral,
1909 [(set i32:$rA, (ctlz i32:$rS))]>;
1910 defm EXTSB : XForm_11r<31, 954, (outs gprc:$rA), (ins gprc:$rS),
1911 "extsb", "$rA, $rS", IIC_IntSimple,
1912 [(set i32:$rA, (sext_inreg i32:$rS, i8))]>;
1913 defm EXTSH : XForm_11r<31, 922, (outs gprc:$rA), (ins gprc:$rS),
1914 "extsh", "$rA, $rS", IIC_IntSimple,
1915 [(set i32:$rA, (sext_inreg i32:$rS, i16))]>;
1917 let isCommutable = 1 in
1918 def CMPB : XForm_6<31, 508, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1919 "cmpb $rA, $rS, $rB", IIC_IntGeneral,
1920 [(set i32:$rA, (PPCcmpb i32:$rS, i32:$rB))]>;
1922 let isCompare = 1, hasSideEffects = 0 in {
1923 def CMPW : XForm_16_ext<31, 0, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
1924 "cmpw $crD, $rA, $rB", IIC_IntCompare>;
1925 def CMPLW : XForm_16_ext<31, 32, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
1926 "cmplw $crD, $rA, $rB", IIC_IntCompare>;
1929 let PPC970_Unit = 3 in { // FPU Operations.
1930 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
1931 // "fcmpo $crD, $fA, $fB", IIC_FPCompare>;
1932 let isCompare = 1, hasSideEffects = 0 in {
1933 def FCMPUS : XForm_17<63, 0, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB),
1934 "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
1935 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1936 def FCMPUD : XForm_17<63, 0, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB),
1937 "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
1940 let Uses = [RM] in {
1941 let hasSideEffects = 0 in {
1942 defm FCTIW : XForm_26r<63, 14, (outs f8rc:$frD), (ins f8rc:$frB),
1943 "fctiw", "$frD, $frB", IIC_FPGeneral,
1945 defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB),
1946 "fctiwz", "$frD, $frB", IIC_FPGeneral,
1947 [(set f64:$frD, (PPCfctiwz f64:$frB))]>;
1949 defm FRSP : XForm_26r<63, 12, (outs f4rc:$frD), (ins f8rc:$frB),
1950 "frsp", "$frD, $frB", IIC_FPGeneral,
1951 [(set f32:$frD, (fround f64:$frB))]>;
1953 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1954 defm FRIND : XForm_26r<63, 392, (outs f8rc:$frD), (ins f8rc:$frB),
1955 "frin", "$frD, $frB", IIC_FPGeneral,
1956 [(set f64:$frD, (frnd f64:$frB))]>;
1957 defm FRINS : XForm_26r<63, 392, (outs f4rc:$frD), (ins f4rc:$frB),
1958 "frin", "$frD, $frB", IIC_FPGeneral,
1959 [(set f32:$frD, (frnd f32:$frB))]>;
1962 let hasSideEffects = 0 in {
1963 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1964 defm FRIPD : XForm_26r<63, 456, (outs f8rc:$frD), (ins f8rc:$frB),
1965 "frip", "$frD, $frB", IIC_FPGeneral,
1966 [(set f64:$frD, (fceil f64:$frB))]>;
1967 defm FRIPS : XForm_26r<63, 456, (outs f4rc:$frD), (ins f4rc:$frB),
1968 "frip", "$frD, $frB", IIC_FPGeneral,
1969 [(set f32:$frD, (fceil f32:$frB))]>;
1970 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1971 defm FRIZD : XForm_26r<63, 424, (outs f8rc:$frD), (ins f8rc:$frB),
1972 "friz", "$frD, $frB", IIC_FPGeneral,
1973 [(set f64:$frD, (ftrunc f64:$frB))]>;
1974 defm FRIZS : XForm_26r<63, 424, (outs f4rc:$frD), (ins f4rc:$frB),
1975 "friz", "$frD, $frB", IIC_FPGeneral,
1976 [(set f32:$frD, (ftrunc f32:$frB))]>;
1977 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1978 defm FRIMD : XForm_26r<63, 488, (outs f8rc:$frD), (ins f8rc:$frB),
1979 "frim", "$frD, $frB", IIC_FPGeneral,
1980 [(set f64:$frD, (ffloor f64:$frB))]>;
1981 defm FRIMS : XForm_26r<63, 488, (outs f4rc:$frD), (ins f4rc:$frB),
1982 "frim", "$frD, $frB", IIC_FPGeneral,
1983 [(set f32:$frD, (ffloor f32:$frB))]>;
1985 defm FSQRT : XForm_26r<63, 22, (outs f8rc:$frD), (ins f8rc:$frB),
1986 "fsqrt", "$frD, $frB", IIC_FPSqrtD,
1987 [(set f64:$frD, (fsqrt f64:$frB))]>;
1988 defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$frD), (ins f4rc:$frB),
1989 "fsqrts", "$frD, $frB", IIC_FPSqrtS,
1990 [(set f32:$frD, (fsqrt f32:$frB))]>;
1995 /// Note that FMR is defined as pseudo-ops on the PPC970 because they are
1996 /// often coalesced away and we don't want the dispatch group builder to think
1997 /// that they will fill slots (which could cause the load of a LSU reject to
1998 /// sneak into a d-group with a store).
1999 let hasSideEffects = 0 in
2000 defm FMR : XForm_26r<63, 72, (outs f4rc:$frD), (ins f4rc:$frB),
2001 "fmr", "$frD, $frB", IIC_FPGeneral,
2002 []>, // (set f32:$frD, f32:$frB)
2005 let PPC970_Unit = 3, hasSideEffects = 0 in { // FPU Operations.
2006 // These are artificially split into two different forms, for 4/8 byte FP.
2007 defm FABSS : XForm_26r<63, 264, (outs f4rc:$frD), (ins f4rc:$frB),
2008 "fabs", "$frD, $frB", IIC_FPGeneral,
2009 [(set f32:$frD, (fabs f32:$frB))]>;
2010 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2011 defm FABSD : XForm_26r<63, 264, (outs f8rc:$frD), (ins f8rc:$frB),
2012 "fabs", "$frD, $frB", IIC_FPGeneral,
2013 [(set f64:$frD, (fabs f64:$frB))]>;
2014 defm FNABSS : XForm_26r<63, 136, (outs f4rc:$frD), (ins f4rc:$frB),
2015 "fnabs", "$frD, $frB", IIC_FPGeneral,
2016 [(set f32:$frD, (fneg (fabs f32:$frB)))]>;
2017 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2018 defm FNABSD : XForm_26r<63, 136, (outs f8rc:$frD), (ins f8rc:$frB),
2019 "fnabs", "$frD, $frB", IIC_FPGeneral,
2020 [(set f64:$frD, (fneg (fabs f64:$frB)))]>;
2021 defm FNEGS : XForm_26r<63, 40, (outs f4rc:$frD), (ins f4rc:$frB),
2022 "fneg", "$frD, $frB", IIC_FPGeneral,
2023 [(set f32:$frD, (fneg f32:$frB))]>;
2024 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2025 defm FNEGD : XForm_26r<63, 40, (outs f8rc:$frD), (ins f8rc:$frB),
2026 "fneg", "$frD, $frB", IIC_FPGeneral,
2027 [(set f64:$frD, (fneg f64:$frB))]>;
2029 defm FCPSGNS : XForm_28r<63, 8, (outs f4rc:$frD), (ins f4rc:$frA, f4rc:$frB),
2030 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
2031 [(set f32:$frD, (fcopysign f32:$frB, f32:$frA))]>;
2032 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2033 defm FCPSGND : XForm_28r<63, 8, (outs f8rc:$frD), (ins f8rc:$frA, f8rc:$frB),
2034 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
2035 [(set f64:$frD, (fcopysign f64:$frB, f64:$frA))]>;
2037 // Reciprocal estimates.
2038 defm FRE : XForm_26r<63, 24, (outs f8rc:$frD), (ins f8rc:$frB),
2039 "fre", "$frD, $frB", IIC_FPGeneral,
2040 [(set f64:$frD, (PPCfre f64:$frB))]>;
2041 defm FRES : XForm_26r<59, 24, (outs f4rc:$frD), (ins f4rc:$frB),
2042 "fres", "$frD, $frB", IIC_FPGeneral,
2043 [(set f32:$frD, (PPCfre f32:$frB))]>;
2044 defm FRSQRTE : XForm_26r<63, 26, (outs f8rc:$frD), (ins f8rc:$frB),
2045 "frsqrte", "$frD, $frB", IIC_FPGeneral,
2046 [(set f64:$frD, (PPCfrsqrte f64:$frB))]>;
2047 defm FRSQRTES : XForm_26r<59, 26, (outs f4rc:$frD), (ins f4rc:$frB),
2048 "frsqrtes", "$frD, $frB", IIC_FPGeneral,
2049 [(set f32:$frD, (PPCfrsqrte f32:$frB))]>;
2052 // XL-Form instructions. condition register logical ops.
2054 let hasSideEffects = 0 in
2055 def MCRF : XLForm_3<19, 0, (outs crrc:$BF), (ins crrc:$BFA),
2056 "mcrf $BF, $BFA", IIC_BrMCR>,
2057 PPC970_DGroup_First, PPC970_Unit_CRU;
2059 // FIXME: According to the ISA (section 2.5.1 of version 2.06), the
2060 // condition-register logical instructions have preferred forms. Specifically,
2061 // it is preferred that the bit specified by the BT field be in the same
2062 // condition register as that specified by the bit BB. We might want to account
2063 // for this via hinting the register allocator and anti-dep breakers, or we
2064 // could constrain the register class to force this constraint and then loosen
2065 // it during register allocation via convertToThreeAddress or some similar
2068 let isCommutable = 1 in {
2069 def CRAND : XLForm_1<19, 257, (outs crbitrc:$CRD),
2070 (ins crbitrc:$CRA, crbitrc:$CRB),
2071 "crand $CRD, $CRA, $CRB", IIC_BrCR,
2072 [(set i1:$CRD, (and i1:$CRA, i1:$CRB))]>;
2074 def CRNAND : XLForm_1<19, 225, (outs crbitrc:$CRD),
2075 (ins crbitrc:$CRA, crbitrc:$CRB),
2076 "crnand $CRD, $CRA, $CRB", IIC_BrCR,
2077 [(set i1:$CRD, (not (and i1:$CRA, i1:$CRB)))]>;
2079 def CROR : XLForm_1<19, 449, (outs crbitrc:$CRD),
2080 (ins crbitrc:$CRA, crbitrc:$CRB),
2081 "cror $CRD, $CRA, $CRB", IIC_BrCR,
2082 [(set i1:$CRD, (or i1:$CRA, i1:$CRB))]>;
2084 def CRXOR : XLForm_1<19, 193, (outs crbitrc:$CRD),
2085 (ins crbitrc:$CRA, crbitrc:$CRB),
2086 "crxor $CRD, $CRA, $CRB", IIC_BrCR,
2087 [(set i1:$CRD, (xor i1:$CRA, i1:$CRB))]>;
2089 def CRNOR : XLForm_1<19, 33, (outs crbitrc:$CRD),
2090 (ins crbitrc:$CRA, crbitrc:$CRB),
2091 "crnor $CRD, $CRA, $CRB", IIC_BrCR,
2092 [(set i1:$CRD, (not (or i1:$CRA, i1:$CRB)))]>;
2094 def CREQV : XLForm_1<19, 289, (outs crbitrc:$CRD),
2095 (ins crbitrc:$CRA, crbitrc:$CRB),
2096 "creqv $CRD, $CRA, $CRB", IIC_BrCR,
2097 [(set i1:$CRD, (not (xor i1:$CRA, i1:$CRB)))]>;
2100 def CRANDC : XLForm_1<19, 129, (outs crbitrc:$CRD),
2101 (ins crbitrc:$CRA, crbitrc:$CRB),
2102 "crandc $CRD, $CRA, $CRB", IIC_BrCR,
2103 [(set i1:$CRD, (and i1:$CRA, (not i1:$CRB)))]>;
2105 def CRORC : XLForm_1<19, 417, (outs crbitrc:$CRD),
2106 (ins crbitrc:$CRA, crbitrc:$CRB),
2107 "crorc $CRD, $CRA, $CRB", IIC_BrCR,
2108 [(set i1:$CRD, (or i1:$CRA, (not i1:$CRB)))]>;
2110 let isCodeGenOnly = 1 in {
2111 def CRSET : XLForm_1_ext<19, 289, (outs crbitrc:$dst), (ins),
2112 "creqv $dst, $dst, $dst", IIC_BrCR,
2113 [(set i1:$dst, 1)]>;
2115 def CRUNSET: XLForm_1_ext<19, 193, (outs crbitrc:$dst), (ins),
2116 "crxor $dst, $dst, $dst", IIC_BrCR,
2117 [(set i1:$dst, 0)]>;
2119 let Defs = [CR1EQ], CRD = 6 in {
2120 def CR6SET : XLForm_1_ext<19, 289, (outs), (ins),
2121 "creqv 6, 6, 6", IIC_BrCR,
2124 def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins),
2125 "crxor 6, 6, 6", IIC_BrCR,
2130 // XFX-Form instructions. Instructions that deal with SPRs.
2133 def MFSPR : XFXForm_1<31, 339, (outs gprc:$RT), (ins i32imm:$SPR),
2134 "mfspr $RT, $SPR", IIC_SprMFSPR>;
2135 def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RT),
2136 "mtspr $SPR, $RT", IIC_SprMTSPR>;
2138 def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR),
2139 "mftb $RT, $SPR", IIC_SprMFTB>, Deprecated<DeprecatedMFTB>;
2141 // A pseudo-instruction used to implement the read of the 64-bit cycle counter
2142 // on a 32-bit target.
2143 let hasSideEffects = 1, usesCustomInserter = 1 in
2144 def ReadTB : Pseudo<(outs gprc:$lo, gprc:$hi), (ins),
2147 let Uses = [CTR] in {
2148 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$rT), (ins),
2149 "mfctr $rT", IIC_SprMFSPR>,
2150 PPC970_DGroup_First, PPC970_Unit_FXU;
2152 let Defs = [CTR], Pattern = [(PPCmtctr i32:$rS)] in {
2153 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
2154 "mtctr $rS", IIC_SprMTSPR>,
2155 PPC970_DGroup_First, PPC970_Unit_FXU;
2157 let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR] in {
2158 let Pattern = [(int_ppc_mtctr i32:$rS)] in
2159 def MTCTRloop : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
2160 "mtctr $rS", IIC_SprMTSPR>,
2161 PPC970_DGroup_First, PPC970_Unit_FXU;
2164 let Defs = [LR] in {
2165 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins gprc:$rS),
2166 "mtlr $rS", IIC_SprMTSPR>,
2167 PPC970_DGroup_First, PPC970_Unit_FXU;
2169 let Uses = [LR] in {
2170 def MFLR : XFXForm_1_ext<31, 339, 8, (outs gprc:$rT), (ins),
2171 "mflr $rT", IIC_SprMFSPR>,
2172 PPC970_DGroup_First, PPC970_Unit_FXU;
2175 let isCodeGenOnly = 1 in {
2176 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed
2177 // like a GPR on the PPC970. As such, copies in and out have the same
2178 // performance characteristics as an OR instruction.
2179 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins gprc:$rS),
2180 "mtspr 256, $rS", IIC_IntGeneral>,
2181 PPC970_DGroup_Single, PPC970_Unit_FXU;
2182 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), (ins),
2183 "mfspr $rT, 256", IIC_IntGeneral>,
2184 PPC970_DGroup_First, PPC970_Unit_FXU;
2186 def MTVRSAVEv : XFXForm_7_ext<31, 467, 256,
2187 (outs VRSAVERC:$reg), (ins gprc:$rS),
2188 "mtspr 256, $rS", IIC_IntGeneral>,
2189 PPC970_DGroup_Single, PPC970_Unit_FXU;
2190 def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT),
2191 (ins VRSAVERC:$reg),
2192 "mfspr $rT, 256", IIC_IntGeneral>,
2193 PPC970_DGroup_First, PPC970_Unit_FXU;
2196 // SPILL_VRSAVE - Indicate that we're dumping the VRSAVE register,
2197 // so we'll need to scavenge a register for it.
2199 def SPILL_VRSAVE : Pseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F),
2200 "#SPILL_VRSAVE", []>;
2202 // RESTORE_VRSAVE - Indicate that we're restoring the VRSAVE register (previously
2203 // spilled), so we'll need to scavenge a register for it.
2205 def RESTORE_VRSAVE : Pseudo<(outs VRSAVERC:$vrsave), (ins memri:$F),
2206 "#RESTORE_VRSAVE", []>;
2208 let hasSideEffects = 0 in {
2209 def MTOCRF: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins gprc:$ST),
2210 "mtocrf $FXM, $ST", IIC_BrMCRX>,
2211 PPC970_DGroup_First, PPC970_Unit_CRU;
2213 def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$rS),
2214 "mtcrf $FXM, $rS", IIC_BrMCRX>,
2215 PPC970_MicroCode, PPC970_Unit_CRU;
2217 let hasExtraSrcRegAllocReq = 1 in // to enable post-ra anti-dep breaking.
2218 def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$rT), (ins crbitm:$FXM),
2219 "mfocrf $rT, $FXM", IIC_SprMFCRF>,
2220 PPC970_DGroup_First, PPC970_Unit_CRU;
2222 def MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins),
2223 "mfcr $rT", IIC_SprMFCR>,
2224 PPC970_MicroCode, PPC970_Unit_CRU;
2225 } // hasSideEffects = 0
2227 // Pseudo instruction to perform FADD in round-to-zero mode.
2228 let usesCustomInserter = 1, Uses = [RM] in {
2229 def FADDrtz: Pseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "",
2230 [(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>;
2233 // The above pseudo gets expanded to make use of the following instructions
2234 // to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level.
2235 let Uses = [RM], Defs = [RM] in {
2236 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
2237 "mtfsb0 $FM", IIC_IntMTFSB0, []>,
2238 PPC970_DGroup_Single, PPC970_Unit_FPU;
2239 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
2240 "mtfsb1 $FM", IIC_IntMTFSB0, []>,
2241 PPC970_DGroup_Single, PPC970_Unit_FPU;
2242 let isCodeGenOnly = 1 in
2243 def MTFSFb : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$rT),
2244 "mtfsf $FM, $rT", IIC_IntMTFSB0, []>,
2245 PPC970_DGroup_Single, PPC970_Unit_FPU;
2247 let Uses = [RM] in {
2248 def MFFS : XForm_42<63, 583, (outs f8rc:$rT), (ins),
2249 "mffs $rT", IIC_IntMFFS,
2250 [(set f64:$rT, (PPCmffs))]>,
2251 PPC970_DGroup_Single, PPC970_Unit_FPU;
2254 def MFFSo : XForm_42<63, 583, (outs f8rc:$rT), (ins),
2255 "mffs. $rT", IIC_IntMFFS, []>, isDOT;
2259 let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations.
2260 // XO-Form instructions. Arithmetic instructions that can set overflow bit
2261 let isCommutable = 1 in
2262 defm ADD4 : XOForm_1r<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2263 "add", "$rT, $rA, $rB", IIC_IntSimple,
2264 [(set i32:$rT, (add i32:$rA, i32:$rB))]>;
2265 let isCodeGenOnly = 1 in
2266 def ADD4TLS : XOForm_1<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, tlsreg32:$rB),
2267 "add $rT, $rA, $rB", IIC_IntSimple,
2268 [(set i32:$rT, (add i32:$rA, tglobaltlsaddr:$rB))]>;
2269 let isCommutable = 1 in
2270 defm ADDC : XOForm_1rc<31, 10, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2271 "addc", "$rT, $rA, $rB", IIC_IntGeneral,
2272 [(set i32:$rT, (addc i32:$rA, i32:$rB))]>,
2273 PPC970_DGroup_Cracked;
2275 defm DIVW : XOForm_1r<31, 491, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2276 "divw", "$rT, $rA, $rB", IIC_IntDivW,
2277 [(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>,
2278 PPC970_DGroup_First, PPC970_DGroup_Cracked;
2279 defm DIVWU : XOForm_1r<31, 459, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2280 "divwu", "$rT, $rA, $rB", IIC_IntDivW,
2281 [(set i32:$rT, (udiv i32:$rA, i32:$rB))]>,
2282 PPC970_DGroup_First, PPC970_DGroup_Cracked;
2283 let isCommutable = 1 in {
2284 defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2285 "mulhw", "$rT, $rA, $rB", IIC_IntMulHW,
2286 [(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>;
2287 defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2288 "mulhwu", "$rT, $rA, $rB", IIC_IntMulHWU,
2289 [(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>;
2290 defm MULLW : XOForm_1r<31, 235, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2291 "mullw", "$rT, $rA, $rB", IIC_IntMulHW,
2292 [(set i32:$rT, (mul i32:$rA, i32:$rB))]>;
2294 defm SUBF : XOForm_1r<31, 40, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2295 "subf", "$rT, $rA, $rB", IIC_IntGeneral,
2296 [(set i32:$rT, (sub i32:$rB, i32:$rA))]>;
2297 defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2298 "subfc", "$rT, $rA, $rB", IIC_IntGeneral,
2299 [(set i32:$rT, (subc i32:$rB, i32:$rA))]>,
2300 PPC970_DGroup_Cracked;
2301 defm NEG : XOForm_3r<31, 104, 0, (outs gprc:$rT), (ins gprc:$rA),
2302 "neg", "$rT, $rA", IIC_IntSimple,
2303 [(set i32:$rT, (ineg i32:$rA))]>;
2304 let Uses = [CARRY] in {
2305 let isCommutable = 1 in
2306 defm ADDE : XOForm_1rc<31, 138, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2307 "adde", "$rT, $rA, $rB", IIC_IntGeneral,
2308 [(set i32:$rT, (adde i32:$rA, i32:$rB))]>;
2309 defm ADDME : XOForm_3rc<31, 234, 0, (outs gprc:$rT), (ins gprc:$rA),
2310 "addme", "$rT, $rA", IIC_IntGeneral,
2311 [(set i32:$rT, (adde i32:$rA, -1))]>;
2312 defm ADDZE : XOForm_3rc<31, 202, 0, (outs gprc:$rT), (ins gprc:$rA),
2313 "addze", "$rT, $rA", IIC_IntGeneral,
2314 [(set i32:$rT, (adde i32:$rA, 0))]>;
2315 defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2316 "subfe", "$rT, $rA, $rB", IIC_IntGeneral,
2317 [(set i32:$rT, (sube i32:$rB, i32:$rA))]>;
2318 defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$rT), (ins gprc:$rA),
2319 "subfme", "$rT, $rA", IIC_IntGeneral,
2320 [(set i32:$rT, (sube -1, i32:$rA))]>;
2321 defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$rT), (ins gprc:$rA),
2322 "subfze", "$rT, $rA", IIC_IntGeneral,
2323 [(set i32:$rT, (sube 0, i32:$rA))]>;
2327 // A-Form instructions. Most of the instructions executed in the FPU are of
2330 let PPC970_Unit = 3, hasSideEffects = 0 in { // FPU Operations.
2331 let Uses = [RM] in {
2332 let isCommutable = 1 in {
2333 defm FMADD : AForm_1r<63, 29,
2334 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2335 "fmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2336 [(set f64:$FRT, (fma f64:$FRA, f64:$FRC, f64:$FRB))]>;
2337 defm FMADDS : AForm_1r<59, 29,
2338 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2339 "fmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2340 [(set f32:$FRT, (fma f32:$FRA, f32:$FRC, f32:$FRB))]>;
2341 defm FMSUB : AForm_1r<63, 28,
2342 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2343 "fmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2345 (fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>;
2346 defm FMSUBS : AForm_1r<59, 28,
2347 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2348 "fmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2350 (fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>;
2351 defm FNMADD : AForm_1r<63, 31,
2352 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2353 "fnmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2355 (fneg (fma f64:$FRA, f64:$FRC, f64:$FRB)))]>;
2356 defm FNMADDS : AForm_1r<59, 31,
2357 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2358 "fnmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2360 (fneg (fma f32:$FRA, f32:$FRC, f32:$FRB)))]>;
2361 defm FNMSUB : AForm_1r<63, 30,
2362 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2363 "fnmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2364 [(set f64:$FRT, (fneg (fma f64:$FRA, f64:$FRC,
2365 (fneg f64:$FRB))))]>;
2366 defm FNMSUBS : AForm_1r<59, 30,
2367 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2368 "fnmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2369 [(set f32:$FRT, (fneg (fma f32:$FRA, f32:$FRC,
2370 (fneg f32:$FRB))))]>;
2373 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
2374 // having 4 of these, force the comparison to always be an 8-byte double (code
2375 // should use an FMRSD if the input comparison value really wants to be a float)
2376 // and 4/8 byte forms for the result and operand type..
2377 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2378 defm FSELD : AForm_1r<63, 23,
2379 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2380 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2381 [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>;
2382 defm FSELS : AForm_1r<63, 23,
2383 (outs f4rc:$FRT), (ins f8rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2384 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2385 [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>;
2386 let Uses = [RM] in {
2387 let isCommutable = 1 in {
2388 defm FADD : AForm_2r<63, 21,
2389 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2390 "fadd", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2391 [(set f64:$FRT, (fadd f64:$FRA, f64:$FRB))]>;
2392 defm FADDS : AForm_2r<59, 21,
2393 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2394 "fadds", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2395 [(set f32:$FRT, (fadd f32:$FRA, f32:$FRB))]>;
2397 defm FDIV : AForm_2r<63, 18,
2398 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2399 "fdiv", "$FRT, $FRA, $FRB", IIC_FPDivD,
2400 [(set f64:$FRT, (fdiv f64:$FRA, f64:$FRB))]>;
2401 defm FDIVS : AForm_2r<59, 18,
2402 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2403 "fdivs", "$FRT, $FRA, $FRB", IIC_FPDivS,
2404 [(set f32:$FRT, (fdiv f32:$FRA, f32:$FRB))]>;
2405 let isCommutable = 1 in {
2406 defm FMUL : AForm_3r<63, 25,
2407 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC),
2408 "fmul", "$FRT, $FRA, $FRC", IIC_FPFused,
2409 [(set f64:$FRT, (fmul f64:$FRA, f64:$FRC))]>;
2410 defm FMULS : AForm_3r<59, 25,
2411 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC),
2412 "fmuls", "$FRT, $FRA, $FRC", IIC_FPGeneral,
2413 [(set f32:$FRT, (fmul f32:$FRA, f32:$FRC))]>;
2415 defm FSUB : AForm_2r<63, 20,
2416 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2417 "fsub", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2418 [(set f64:$FRT, (fsub f64:$FRA, f64:$FRB))]>;
2419 defm FSUBS : AForm_2r<59, 20,
2420 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2421 "fsubs", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2422 [(set f32:$FRT, (fsub f32:$FRA, f32:$FRB))]>;
2426 let hasSideEffects = 0 in {
2427 let PPC970_Unit = 1 in { // FXU Operations.
2429 def ISEL : AForm_4<31, 15,
2430 (outs gprc:$rT), (ins gprc_nor0:$rA, gprc:$rB, crbitrc:$cond),
2431 "isel $rT, $rA, $rB, $cond", IIC_IntISEL,
2435 let PPC970_Unit = 1 in { // FXU Operations.
2436 // M-Form instructions. rotate and mask instructions.
2438 let isCommutable = 1 in {
2439 // RLWIMI can be commuted if the rotate amount is zero.
2440 defm RLWIMI : MForm_2r<20, (outs gprc:$rA),
2441 (ins gprc:$rSi, gprc:$rS, u5imm:$SH, u5imm:$MB,
2442 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME",
2443 IIC_IntRotate, []>, PPC970_DGroup_Cracked,
2444 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">;
2446 let BaseName = "rlwinm" in {
2447 def RLWINM : MForm_2<21,
2448 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2449 "rlwinm $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
2452 def RLWINMo : MForm_2<21,
2453 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2454 "rlwinm. $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
2455 []>, isDOT, RecFormRel, PPC970_DGroup_Cracked;
2457 defm RLWNM : MForm_2r<23, (outs gprc:$rA),
2458 (ins gprc:$rS, gprc:$rB, u5imm:$MB, u5imm:$ME),
2459 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral,
2462 } // hasSideEffects = 0
2464 //===----------------------------------------------------------------------===//
2465 // PowerPC Instruction Patterns
2468 // Arbitrary immediate support. Implement in terms of LIS/ORI.
2469 def : Pat<(i32 imm:$imm),
2470 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
2472 // Implement the 'not' operation with the NOR instruction.
2473 def i32not : OutPatFrag<(ops node:$in),
2475 def : Pat<(not i32:$in),
2478 // ADD an arbitrary immediate.
2479 def : Pat<(add i32:$in, imm:$imm),
2480 (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
2481 // OR an arbitrary immediate.
2482 def : Pat<(or i32:$in, imm:$imm),
2483 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2484 // XOR an arbitrary immediate.
2485 def : Pat<(xor i32:$in, imm:$imm),
2486 (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2488 def : Pat<(sub imm32SExt16:$imm, i32:$in),
2489 (SUBFIC $in, imm:$imm)>;
2492 def : Pat<(shl i32:$in, (i32 imm:$imm)),
2493 (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>;
2494 def : Pat<(srl i32:$in, (i32 imm:$imm)),
2495 (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>;
2498 def : Pat<(rotl i32:$in, i32:$sh),
2499 (RLWNM $in, $sh, 0, 31)>;
2500 def : Pat<(rotl i32:$in, (i32 imm:$imm)),
2501 (RLWINM $in, imm:$imm, 0, 31)>;
2504 def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm),
2505 (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
2508 def : Pat<(PPCcall (i32 tglobaladdr:$dst)),
2509 (BL tglobaladdr:$dst)>;
2510 def : Pat<(PPCcall (i32 texternalsym:$dst)),
2511 (BL texternalsym:$dst)>;
2513 def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm),
2514 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
2516 def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
2517 (TCRETURNdi texternalsym:$dst, imm:$imm)>;
2519 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
2520 (TCRETURNri CTRRC:$dst, imm:$imm)>;
2524 // Hi and Lo for Darwin Global Addresses.
2525 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
2526 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
2527 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
2528 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
2529 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
2530 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
2531 def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>;
2532 def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>;
2533 def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in),
2534 (ADDIS $in, tglobaltlsaddr:$g)>;
2535 def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in),
2536 (ADDI $in, tglobaltlsaddr:$g)>;
2537 def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)),
2538 (ADDIS $in, tglobaladdr:$g)>;
2539 def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)),
2540 (ADDIS $in, tconstpool:$g)>;
2541 def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)),
2542 (ADDIS $in, tjumptable:$g)>;
2543 def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)),
2544 (ADDIS $in, tblockaddress:$g)>;
2546 // Support for thread-local storage.
2547 def PPC32GOT: Pseudo<(outs gprc:$rD), (ins), "#PPC32GOT",
2548 [(set i32:$rD, (PPCppc32GOT))]>;
2550 // Get the _GLOBAL_OFFSET_TABLE_ in PIC mode.
2551 // This uses two output registers, the first as the real output, the second as a
2552 // temporary register, used internally in code generation.
2553 def PPC32PICGOT: Pseudo<(outs gprc:$rD, gprc:$rT), (ins), "#PPC32PICGOT",
2554 []>, NoEncode<"$rT">;
2556 def LDgotTprelL32: Pseudo<(outs gprc:$rD), (ins s16imm:$disp, gprc_nor0:$reg),
2559 (PPCldGotTprelL tglobaltlsaddr:$disp, i32:$reg))]>;
2560 def : Pat<(PPCaddTls i32:$in, tglobaltlsaddr:$g),
2561 (ADD4TLS $in, tglobaltlsaddr:$g)>;
2563 def ADDItlsgdL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2566 (PPCaddiTlsgdL i32:$reg, tglobaltlsaddr:$disp))]>;
2567 // LR is a true define, while the rest of the Defs are clobbers. R3 is
2568 // explicitly defined when this op is created, so not mentioned here.
2569 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2570 Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2571 def GETtlsADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),
2574 (PPCgetTlsAddr i32:$reg, tglobaltlsaddr:$sym))]>;
2575 // Combined op for ADDItlsgdL32 and GETtlsADDR32, late expanded. R3 and LR
2576 // are true defines while the rest of the Defs are clobbers.
2577 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2578 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2579 def ADDItlsgdLADDR32 : Pseudo<(outs gprc:$rD),
2580 (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym),
2581 "#ADDItlsgdLADDR32",
2583 (PPCaddiTlsgdLAddr i32:$reg,
2584 tglobaltlsaddr:$disp,
2585 tglobaltlsaddr:$sym))]>;
2586 def ADDItlsldL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2589 (PPCaddiTlsldL i32:$reg, tglobaltlsaddr:$disp))]>;
2590 // LR is a true define, while the rest of the Defs are clobbers. R3 is
2591 // explicitly defined when this op is created, so not mentioned here.
2592 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2593 Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2594 def GETtlsldADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),
2597 (PPCgetTlsldAddr i32:$reg,
2598 tglobaltlsaddr:$sym))]>;
2599 // Combined op for ADDItlsldL32 and GETtlsADDR32, late expanded. R3 and LR
2600 // are true defines while the rest of the Defs are clobbers.
2601 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2602 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2603 def ADDItlsldLADDR32 : Pseudo<(outs gprc:$rD),
2604 (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym),
2605 "#ADDItlsldLADDR32",
2607 (PPCaddiTlsldLAddr i32:$reg,
2608 tglobaltlsaddr:$disp,
2609 tglobaltlsaddr:$sym))]>;
2610 def ADDIdtprelL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2613 (PPCaddiDtprelL i32:$reg, tglobaltlsaddr:$disp))]>;
2614 def ADDISdtprelHA32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2617 (PPCaddisDtprelHA i32:$reg,
2618 tglobaltlsaddr:$disp))]>;
2620 // Support for Position-independent code
2621 def LWZtoc : Pseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg),
2624 (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>;
2625 // Get Global (GOT) Base Register offset, from the word immediately preceding
2626 // the function label.
2627 def UpdateGBR : Pseudo<(outs gprc:$rD, gprc:$rT), (ins gprc:$rI), "#UpdateGBR", []>;
2630 // Standard shifts. These are represented separately from the real shifts above
2631 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
2633 def : Pat<(sra i32:$rS, i32:$rB),
2635 def : Pat<(srl i32:$rS, i32:$rB),
2637 def : Pat<(shl i32:$rS, i32:$rB),
2640 def : Pat<(zextloadi1 iaddr:$src),
2642 def : Pat<(zextloadi1 xaddr:$src),
2644 def : Pat<(extloadi1 iaddr:$src),
2646 def : Pat<(extloadi1 xaddr:$src),
2648 def : Pat<(extloadi8 iaddr:$src),
2650 def : Pat<(extloadi8 xaddr:$src),
2652 def : Pat<(extloadi16 iaddr:$src),
2654 def : Pat<(extloadi16 xaddr:$src),
2656 def : Pat<(f64 (extloadf32 iaddr:$src)),
2657 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
2658 def : Pat<(f64 (extloadf32 xaddr:$src)),
2659 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
2661 def : Pat<(f64 (fextend f32:$src)),
2662 (COPY_TO_REGCLASS $src, F8RC)>;
2664 // Only seq_cst fences require the heavyweight sync (SYNC 0).
2665 // All others can use the lightweight sync (SYNC 1).
2666 // source: http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
2667 // The rule for seq_cst is duplicated to work with both 64 bits and 32 bits
2668 // versions of Power.
2669 def : Pat<(atomic_fence (i64 7), (imm)), (SYNC 0)>, Requires<[HasSYNC]>;
2670 def : Pat<(atomic_fence (i32 7), (imm)), (SYNC 0)>, Requires<[HasSYNC]>;
2671 def : Pat<(atomic_fence (imm), (imm)), (SYNC 1)>, Requires<[HasSYNC]>;
2672 def : Pat<(atomic_fence (imm), (imm)), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
2674 // Additional FNMSUB patterns: -a*c + b == -(a*c - b)
2675 def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),
2676 (FNMSUB $A, $C, $B)>;
2677 def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B),
2678 (FNMSUB $A, $C, $B)>;
2679 def : Pat<(fma (fneg f32:$A), f32:$C, f32:$B),
2680 (FNMSUBS $A, $C, $B)>;
2681 def : Pat<(fma f32:$A, (fneg f32:$C), f32:$B),
2682 (FNMSUBS $A, $C, $B)>;
2684 // FCOPYSIGN's operand types need not agree.
2685 def : Pat<(fcopysign f64:$frB, f32:$frA),
2686 (FCPSGND (COPY_TO_REGCLASS $frA, F8RC), $frB)>;
2687 def : Pat<(fcopysign f32:$frB, f64:$frA),
2688 (FCPSGNS (COPY_TO_REGCLASS $frA, F4RC), $frB)>;
2690 include "PPCInstrAltivec.td"
2691 include "PPCInstrSPE.td"
2692 include "PPCInstr64Bit.td"
2693 include "PPCInstrVSX.td"
2694 include "PPCInstrQPX.td"
2696 def crnot : OutPatFrag<(ops node:$in),
2698 def : Pat<(not i1:$in),
2701 // Patterns for arithmetic i1 operations.
2702 def : Pat<(add i1:$a, i1:$b),
2704 def : Pat<(sub i1:$a, i1:$b),
2706 def : Pat<(mul i1:$a, i1:$b),
2709 // We're sometimes asked to materialize i1 -1, which is just 1 in this case
2710 // (-1 is used to mean all bits set).
2711 def : Pat<(i1 -1), (CRSET)>;
2713 // i1 extensions, implemented in terms of isel.
2714 def : Pat<(i32 (zext i1:$in)),
2715 (SELECT_I4 $in, (LI 1), (LI 0))>;
2716 def : Pat<(i32 (sext i1:$in)),
2717 (SELECT_I4 $in, (LI -1), (LI 0))>;
2719 def : Pat<(i64 (zext i1:$in)),
2720 (SELECT_I8 $in, (LI8 1), (LI8 0))>;
2721 def : Pat<(i64 (sext i1:$in)),
2722 (SELECT_I8 $in, (LI8 -1), (LI8 0))>;
2724 // FIXME: We should choose either a zext or a sext based on other constants
2726 def : Pat<(i32 (anyext i1:$in)),
2727 (SELECT_I4 $in, (LI 1), (LI 0))>;
2728 def : Pat<(i64 (anyext i1:$in)),
2729 (SELECT_I8 $in, (LI8 1), (LI8 0))>;
2731 // match setcc on i1 variables.
2732 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)),
2734 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)),
2736 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLE)),
2738 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULE)),
2740 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)),
2742 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGE)),
2744 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)),
2746 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGT)),
2748 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)),
2750 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETNE)),
2753 // match setcc on non-i1 (non-vector) variables. Note that SETUEQ, SETOGE,
2754 // SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for
2755 // floating-point types.
2757 multiclass CRNotPat<dag pattern, dag result> {
2758 def : Pat<pattern, (crnot result)>;
2759 def : Pat<(not pattern), result>;
2761 // We can also fold the crnot into an extension:
2762 def : Pat<(i32 (zext pattern)),
2763 (SELECT_I4 result, (LI 0), (LI 1))>;
2764 def : Pat<(i32 (sext pattern)),
2765 (SELECT_I4 result, (LI 0), (LI -1))>;
2767 // We can also fold the crnot into an extension:
2768 def : Pat<(i64 (zext pattern)),
2769 (SELECT_I8 result, (LI8 0), (LI8 1))>;
2770 def : Pat<(i64 (sext pattern)),
2771 (SELECT_I8 result, (LI8 0), (LI8 -1))>;
2773 // FIXME: We should choose either a zext or a sext based on other constants
2775 def : Pat<(i32 (anyext pattern)),
2776 (SELECT_I4 result, (LI 0), (LI 1))>;
2778 def : Pat<(i64 (anyext pattern)),
2779 (SELECT_I8 result, (LI8 0), (LI8 1))>;
2782 // FIXME: Because of what seems like a bug in TableGen's type-inference code,
2783 // we need to write imm:$imm in the output patterns below, not just $imm, or
2784 // else the resulting matcher will not correctly add the immediate operand
2785 // (making it a register operand instead).
2788 multiclass ExtSetCCPat<CondCode cc, PatFrag pfrag,
2789 OutPatFrag rfrag, OutPatFrag rfrag8> {
2790 def : Pat<(i32 (zext (i1 (pfrag i32:$s1, cc)))),
2792 def : Pat<(i64 (zext (i1 (pfrag i64:$s1, cc)))),
2794 def : Pat<(i64 (zext (i1 (pfrag i32:$s1, cc)))),
2795 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;
2796 def : Pat<(i32 (zext (i1 (pfrag i64:$s1, cc)))),
2797 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
2799 def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, cc)))),
2801 def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, cc)))),
2803 def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, cc)))),
2804 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;
2805 def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, cc)))),
2806 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
2809 // Note that we do all inversions below with i(32|64)not, instead of using
2810 // (xori x, 1) because on the A2 nor has single-cycle latency while xori
2811 // has 2-cycle latency.
2813 defm : ExtSetCCPat<SETEQ,
2814 PatFrag<(ops node:$in, node:$cc),
2815 (setcc $in, 0, $cc)>,
2816 OutPatFrag<(ops node:$in),
2817 (RLWINM (CNTLZW $in), 27, 31, 31)>,
2818 OutPatFrag<(ops node:$in),
2819 (RLDICL (CNTLZD $in), 58, 63)> >;
2821 defm : ExtSetCCPat<SETNE,
2822 PatFrag<(ops node:$in, node:$cc),
2823 (setcc $in, 0, $cc)>,
2824 OutPatFrag<(ops node:$in),
2825 (RLWINM (i32not (CNTLZW $in)), 27, 31, 31)>,
2826 OutPatFrag<(ops node:$in),
2827 (RLDICL (i64not (CNTLZD $in)), 58, 63)> >;
2829 defm : ExtSetCCPat<SETLT,
2830 PatFrag<(ops node:$in, node:$cc),
2831 (setcc $in, 0, $cc)>,
2832 OutPatFrag<(ops node:$in),
2833 (RLWINM $in, 1, 31, 31)>,
2834 OutPatFrag<(ops node:$in),
2835 (RLDICL $in, 1, 63)> >;
2837 defm : ExtSetCCPat<SETGE,
2838 PatFrag<(ops node:$in, node:$cc),
2839 (setcc $in, 0, $cc)>,
2840 OutPatFrag<(ops node:$in),
2841 (RLWINM (i32not $in), 1, 31, 31)>,
2842 OutPatFrag<(ops node:$in),
2843 (RLDICL (i64not $in), 1, 63)> >;
2845 defm : ExtSetCCPat<SETGT,
2846 PatFrag<(ops node:$in, node:$cc),
2847 (setcc $in, 0, $cc)>,
2848 OutPatFrag<(ops node:$in),
2849 (RLWINM (ANDC (NEG $in), $in), 1, 31, 31)>,
2850 OutPatFrag<(ops node:$in),
2851 (RLDICL (ANDC8 (NEG8 $in), $in), 1, 63)> >;
2853 defm : ExtSetCCPat<SETLE,
2854 PatFrag<(ops node:$in, node:$cc),
2855 (setcc $in, 0, $cc)>,
2856 OutPatFrag<(ops node:$in),
2857 (RLWINM (ORC $in, (NEG $in)), 1, 31, 31)>,
2858 OutPatFrag<(ops node:$in),
2859 (RLDICL (ORC8 $in, (NEG8 $in)), 1, 63)> >;
2861 defm : ExtSetCCPat<SETLT,
2862 PatFrag<(ops node:$in, node:$cc),
2863 (setcc $in, -1, $cc)>,
2864 OutPatFrag<(ops node:$in),
2865 (RLWINM (AND $in, (ADDI $in, 1)), 1, 31, 31)>,
2866 OutPatFrag<(ops node:$in),
2867 (RLDICL (AND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
2869 defm : ExtSetCCPat<SETGE,
2870 PatFrag<(ops node:$in, node:$cc),
2871 (setcc $in, -1, $cc)>,
2872 OutPatFrag<(ops node:$in),
2873 (RLWINM (NAND $in, (ADDI $in, 1)), 1, 31, 31)>,
2874 OutPatFrag<(ops node:$in),
2875 (RLDICL (NAND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
2877 defm : ExtSetCCPat<SETGT,
2878 PatFrag<(ops node:$in, node:$cc),
2879 (setcc $in, -1, $cc)>,
2880 OutPatFrag<(ops node:$in),
2881 (RLWINM (i32not $in), 1, 31, 31)>,
2882 OutPatFrag<(ops node:$in),
2883 (RLDICL (i64not $in), 1, 63)> >;
2885 defm : ExtSetCCPat<SETLE,
2886 PatFrag<(ops node:$in, node:$cc),
2887 (setcc $in, -1, $cc)>,
2888 OutPatFrag<(ops node:$in),
2889 (RLWINM $in, 1, 31, 31)>,
2890 OutPatFrag<(ops node:$in),
2891 (RLDICL $in, 1, 63)> >;
2894 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULT)),
2895 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
2896 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLT)),
2897 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;
2898 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGT)),
2899 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;
2900 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGT)),
2901 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;
2902 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETEQ)),
2903 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;
2904 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETEQ)),
2905 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;
2907 // For non-equality comparisons, the default code would materialize the
2908 // constant, then compare against it, like this:
2910 // ori r2, r2, 22136
2913 // Since we are just comparing for equality, we can emit this instead:
2914 // xoris r0,r3,0x1234
2915 // cmplwi cr0,r0,0x5678
2918 def : Pat<(i1 (setcc i32:$s1, imm:$imm, SETEQ)),
2919 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
2920 (LO16 imm:$imm)), sub_eq)>;
2922 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGE)),
2923 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
2924 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGE)),
2925 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;
2926 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULE)),
2927 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;
2928 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLE)),
2929 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;
2930 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETNE)),
2931 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;
2932 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETNE)),
2933 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;
2935 defm : CRNotPat<(i1 (setcc i32:$s1, imm:$imm, SETNE)),
2936 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
2937 (LO16 imm:$imm)), sub_eq)>;
2939 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETULT)),
2940 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>;
2941 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETLT)),
2942 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>;
2943 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETUGT)),
2944 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>;
2945 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETGT)),
2946 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>;
2947 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETEQ)),
2948 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>;
2950 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETUGE)),
2951 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>;
2952 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETGE)),
2953 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>;
2954 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETULE)),
2955 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>;
2956 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETLE)),
2957 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>;
2958 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETNE)),
2959 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>;
2962 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULT)),
2963 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>;
2964 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLT)),
2965 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>;
2966 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGT)),
2967 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>;
2968 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGT)),
2969 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>;
2970 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETEQ)),
2971 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>;
2972 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETEQ)),
2973 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>;
2975 // For non-equality comparisons, the default code would materialize the
2976 // constant, then compare against it, like this:
2978 // ori r2, r2, 22136
2981 // Since we are just comparing for equality, we can emit this instead:
2982 // xoris r0,r3,0x1234
2983 // cmpldi cr0,r0,0x5678
2986 def : Pat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETEQ)),
2987 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
2988 (LO16 imm:$imm)), sub_eq)>;
2990 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGE)),
2991 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>;
2992 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGE)),
2993 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>;
2994 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULE)),
2995 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>;
2996 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLE)),
2997 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>;
2998 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETNE)),
2999 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>;
3000 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETNE)),
3001 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>;
3003 defm : CRNotPat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)),
3004 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
3005 (LO16 imm:$imm)), sub_eq)>;
3007 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETULT)),
3008 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>;
3009 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETLT)),
3010 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>;
3011 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETUGT)),
3012 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;
3013 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETGT)),
3014 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
3015 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETEQ)),
3016 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
3018 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETUGE)),
3019 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>;
3020 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETGE)),
3021 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>;
3022 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETULE)),
3023 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;
3024 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETLE)),
3025 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
3026 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETNE)),
3027 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
3030 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOLT)),
3031 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3032 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETLT)),
3033 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3034 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOGT)),
3035 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3036 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETGT)),
3037 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3038 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOEQ)),
3039 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3040 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETEQ)),
3041 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3042 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETUO)),
3043 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>;
3045 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUGE)),
3046 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3047 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETGE)),
3048 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3049 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETULE)),
3050 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3051 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETLE)),
3052 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3053 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUNE)),
3054 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3055 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETNE)),
3056 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3057 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETO)),
3058 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>;
3061 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOLT)),
3062 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3063 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETLT)),
3064 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3065 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOGT)),
3066 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3067 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETGT)),
3068 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3069 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOEQ)),
3070 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3071 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETEQ)),
3072 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3073 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETUO)),
3074 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
3076 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUGE)),
3077 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3078 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETGE)),
3079 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3080 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETULE)),
3081 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3082 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETLE)),
3083 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3084 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUNE)),
3085 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3086 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETNE)),
3087 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3088 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETO)),
3089 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
3091 // match select on i1 variables:
3092 def : Pat<(i1 (select i1:$cond, i1:$tval, i1:$fval)),
3093 (CROR (CRAND $cond , $tval),
3094 (CRAND (crnot $cond), $fval))>;
3096 // match selectcc on i1 variables:
3097 // select (lhs == rhs), tval, fval is:
3098 // ((lhs == rhs) & tval) | (!(lhs == rhs) & fval)
3099 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLT)),
3100 (CROR (CRAND (CRANDC $rhs, $lhs), $tval),
3101 (CRAND (CRORC $lhs, $rhs), $fval))>;
3102 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLE)),
3103 (CROR (CRAND (CRORC $rhs, $lhs), $tval),
3104 (CRAND (CRANDC $lhs, $rhs), $fval))>;
3105 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETEQ)),
3106 (CROR (CRAND (CREQV $lhs, $rhs), $tval),
3107 (CRAND (CRXOR $lhs, $rhs), $fval))>;
3108 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGE)),
3109 (CROR (CRAND (CRORC $lhs, $rhs), $tval),
3110 (CRAND (CRANDC $rhs, $lhs), $fval))>;
3111 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGT)),
3112 (CROR (CRAND (CRANDC $lhs, $rhs), $tval),
3113 (CRAND (CRORC $rhs, $lhs), $fval))>;
3114 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETNE)),
3115 (CROR (CRAND (CREQV $lhs, $rhs), $fval),
3116 (CRAND (CRXOR $lhs, $rhs), $tval))>;
3118 // match selectcc on i1 variables with non-i1 output.
3119 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLT)),
3120 (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3121 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLE)),
3122 (SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>;
3123 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETEQ)),
3124 (SELECT_I4 (CREQV $lhs, $rhs), $tval, $fval)>;
3125 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGE)),
3126 (SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>;
3127 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGT)),
3128 (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3129 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETNE)),
3130 (SELECT_I4 (CRXOR $lhs, $rhs), $tval, $fval)>;
3132 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLT)),
3133 (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3134 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLE)),
3135 (SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>;
3136 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETEQ)),
3137 (SELECT_I8 (CREQV $lhs, $rhs), $tval, $fval)>;
3138 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGE)),
3139 (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>;
3140 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGT)),
3141 (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3142 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETNE)),
3143 (SELECT_I8 (CRXOR $lhs, $rhs), $tval, $fval)>;
3145 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)),
3146 (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3147 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)),
3148 (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>;
3149 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)),
3150 (SELECT_F4 (CREQV $lhs, $rhs), $tval, $fval)>;
3151 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)),
3152 (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>;
3153 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)),
3154 (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3155 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)),
3156 (SELECT_F4 (CRXOR $lhs, $rhs), $tval, $fval)>;
3158 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)),
3159 (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3160 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)),
3161 (SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>;
3162 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)),
3163 (SELECT_F8 (CREQV $lhs, $rhs), $tval, $fval)>;
3164 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)),
3165 (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>;
3166 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)),
3167 (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3168 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)),
3169 (SELECT_F8 (CRXOR $lhs, $rhs), $tval, $fval)>;
3171 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLT)),
3172 (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>;
3173 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLE)),
3174 (SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>;
3175 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETEQ)),
3176 (SELECT_VRRC (CREQV $lhs, $rhs), $tval, $fval)>;
3177 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGE)),
3178 (SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>;
3179 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGT)),
3180 (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>;
3181 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETNE)),
3182 (SELECT_VRRC (CRXOR $lhs, $rhs), $tval, $fval)>;
3184 let usesCustomInserter = 1 in {
3185 def ANDIo_1_EQ_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
3187 [(set i1:$dst, (trunc (not i32:$in)))]>;
3188 def ANDIo_1_GT_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
3190 [(set i1:$dst, (trunc i32:$in))]>;
3192 def ANDIo_1_EQ_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in),
3194 [(set i1:$dst, (trunc (not i64:$in)))]>;
3195 def ANDIo_1_GT_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in),
3197 [(set i1:$dst, (trunc i64:$in))]>;
3200 def : Pat<(i1 (not (trunc i32:$in))),
3201 (ANDIo_1_EQ_BIT $in)>;
3202 def : Pat<(i1 (not (trunc i64:$in))),
3203 (ANDIo_1_EQ_BIT8 $in)>;
3205 //===----------------------------------------------------------------------===//
3206 // PowerPC Instructions used for assembler/disassembler only
3209 // FIXME: For B=0 or B > 8, the registers following RT are used.
3210 // WARNING: Do not add patterns for this instruction without fixing this.
3211 def LSWI : XForm_base_r3xo<31, 597, (outs gprc:$RT), (ins gprc:$A, u5imm:$B),
3212 "lswi $RT, $A, $B", IIC_LdStLoad, []>;
3214 // FIXME: For B=0 or B > 8, the registers following RT are used.
3215 // WARNING: Do not add patterns for this instruction without fixing this.
3216 def STSWI : XForm_base_r3xo<31, 725, (outs), (ins gprc:$RT, gprc:$A, u5imm:$B),
3217 "stswi $RT, $A, $B", IIC_LdStLoad, []>;
3219 def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins),
3220 "isync", IIC_SprISYNC, []>;
3222 def ICBI : XForm_1a<31, 982, (outs), (ins memrr:$src),
3223 "icbi $src", IIC_LdStICBI, []>;
3225 // We used to have EIEIO as value but E[0-9A-Z] is a reserved name
3226 def EnforceIEIO : XForm_24_eieio<31, 854, (outs), (ins),
3227 "eieio", IIC_LdStLoad, []>;
3229 def WAIT : XForm_24_sync<31, 62, (outs), (ins i32imm:$L),
3230 "wait $L", IIC_LdStLoad, []>;
3232 def MBAR : XForm_mbar<31, 854, (outs), (ins u5imm:$MO),
3233 "mbar $MO", IIC_LdStLoad>, Requires<[IsBookE]>;
3235 def MTSR: XForm_sr<31, 210, (outs), (ins gprc:$RS, u4imm:$SR),
3236 "mtsr $SR, $RS", IIC_SprMTSR>;
3238 def MFSR: XForm_sr<31, 595, (outs gprc:$RS), (ins u4imm:$SR),
3239 "mfsr $RS, $SR", IIC_SprMFSR>;
3241 def MTSRIN: XForm_srin<31, 242, (outs), (ins gprc:$RS, gprc:$RB),
3242 "mtsrin $RS, $RB", IIC_SprMTSR>;
3244 def MFSRIN: XForm_srin<31, 659, (outs gprc:$RS), (ins gprc:$RB),
3245 "mfsrin $RS, $RB", IIC_SprMFSR>;
3247 def MTMSR: XForm_mtmsr<31, 146, (outs), (ins gprc:$RS, i32imm:$L),
3248 "mtmsr $RS, $L", IIC_SprMTMSR>;
3250 def WRTEE: XForm_mtmsr<31, 131, (outs), (ins gprc:$RS),
3251 "wrtee $RS", IIC_SprMTMSR>, Requires<[IsBookE]> {
3255 def WRTEEI: I<31, (outs), (ins i1imm:$E), "wrteei $E", IIC_SprMTMSR>,
3256 Requires<[IsBookE]> {
3260 let Inst{21-30} = 163;
3263 def DCCCI : XForm_tlb<454, (outs), (ins gprc:$A, gprc:$B),
3264 "dccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>;
3265 def ICCCI : XForm_tlb<966, (outs), (ins gprc:$A, gprc:$B),
3266 "iccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>;
3268 def : InstAlias<"dci 0", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>;
3269 def : InstAlias<"dccci", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>;
3270 def : InstAlias<"ici 0", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>;
3271 def : InstAlias<"iccci", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>;
3273 def MFMSR : XForm_rs<31, 83, (outs gprc:$RT), (ins),
3274 "mfmsr $RT", IIC_SprMFMSR, []>;
3276 def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, i32imm:$L),
3277 "mtmsrd $RS, $L", IIC_SprMTMSRD>;
3279 def MCRFS : XLForm_3<63, 64, (outs crrc:$BF), (ins crrc:$BFA),
3280 "mcrfs $BF, $BFA", IIC_BrMCR>;
3282 def MTFSFI : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W),
3283 "mtfsfi $BF, $U, $W", IIC_IntMFFS>;
3285 def MTFSFIo : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W),
3286 "mtfsfi. $BF, $U, $W", IIC_IntMFFS>, isDOT;
3288 def : InstAlias<"mtfsfi $BF, $U", (MTFSFI crrc:$BF, i32imm:$U, 0)>;
3289 def : InstAlias<"mtfsfi. $BF, $U", (MTFSFIo crrc:$BF, i32imm:$U, 0)>;
3291 def MTFSF : XFLForm_1<63, 711, (outs),
3292 (ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W),
3293 "mtfsf $FLM, $FRB, $L, $W", IIC_IntMFFS, []>;
3294 def MTFSFo : XFLForm_1<63, 711, (outs),
3295 (ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W),
3296 "mtfsf. $FLM, $FRB, $L, $W", IIC_IntMFFS, []>, isDOT;
3298 def : InstAlias<"mtfsf $FLM, $FRB", (MTFSF i32imm:$FLM, f8rc:$FRB, 0, 0)>;
3299 def : InstAlias<"mtfsf. $FLM, $FRB", (MTFSFo i32imm:$FLM, f8rc:$FRB, 0, 0)>;
3301 def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB),
3302 "slbie $RB", IIC_SprSLBIE, []>;
3304 def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RS, gprc:$RB),
3305 "slbmte $RS, $RB", IIC_SprSLBMTE, []>;
3307 def SLBMFEE : XForm_26<31, 915, (outs gprc:$RT), (ins gprc:$RB),
3308 "slbmfee $RT, $RB", IIC_SprSLBMFEE, []>;
3310 def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", IIC_SprSLBIA, []>;
3312 def TLBIA : XForm_0<31, 370, (outs), (ins),
3313 "tlbia", IIC_SprTLBIA, []>;
3315 def TLBSYNC : XForm_0<31, 566, (outs), (ins),
3316 "tlbsync", IIC_SprTLBSYNC, []>;
3318 def TLBIEL : XForm_16b<31, 274, (outs), (ins gprc:$RB),
3319 "tlbiel $RB", IIC_SprTLBIEL, []>;
3321 def TLBLD : XForm_16b<31, 978, (outs), (ins gprc:$RB),
3322 "tlbld $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>;
3323 def TLBLI : XForm_16b<31, 1010, (outs), (ins gprc:$RB),
3324 "tlbli $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>;
3326 def TLBIE : XForm_26<31, 306, (outs), (ins gprc:$RS, gprc:$RB),
3327 "tlbie $RB,$RS", IIC_SprTLBIE, []>;
3329 def TLBSX : XForm_tlb<914, (outs), (ins gprc:$A, gprc:$B), "tlbsx $A, $B",
3330 IIC_LdStLoad>, Requires<[IsBookE]>;
3332 def TLBIVAX : XForm_tlb<786, (outs), (ins gprc:$A, gprc:$B), "tlbivax $A, $B",
3333 IIC_LdStLoad>, Requires<[IsBookE]>;
3335 def TLBRE : XForm_24_eieio<31, 946, (outs), (ins),
3336 "tlbre", IIC_LdStLoad, []>, Requires<[IsBookE]>;
3338 def TLBWE : XForm_24_eieio<31, 978, (outs), (ins),
3339 "tlbwe", IIC_LdStLoad, []>, Requires<[IsBookE]>;
3341 def TLBRE2 : XForm_tlbws<31, 946, (outs gprc:$RS), (ins gprc:$A, i1imm:$WS),
3342 "tlbre $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>;
3344 def TLBWE2 : XForm_tlbws<31, 978, (outs), (ins gprc:$RS, gprc:$A, i1imm:$WS),
3345 "tlbwe $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>;
3347 def TLBSX2 : XForm_base_r3xo<31, 914, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3348 "tlbsx $RST, $A, $B", IIC_LdStLoad, []>,
3349 Requires<[IsPPC4xx]>;
3350 def TLBSX2D : XForm_base_r3xo<31, 914, (outs),
3351 (ins gprc:$RST, gprc:$A, gprc:$B),
3352 "tlbsx. $RST, $A, $B", IIC_LdStLoad, []>,
3353 Requires<[IsPPC4xx]>, isDOT;
3355 def RFID : XForm_0<19, 18, (outs), (ins), "rfid", IIC_IntRFID, []>;
3357 def RFI : XForm_0<19, 50, (outs), (ins), "rfi", IIC_SprRFI, []>,
3358 Requires<[IsBookE]>;
3359 def RFCI : XForm_0<19, 51, (outs), (ins), "rfci", IIC_BrB, []>,
3360 Requires<[IsBookE]>;
3362 def RFDI : XForm_0<19, 39, (outs), (ins), "rfdi", IIC_BrB, []>,
3364 def RFMCI : XForm_0<19, 38, (outs), (ins), "rfmci", IIC_BrB, []>,
3367 def MFDCR : XFXForm_1<31, 323, (outs gprc:$RT), (ins i32imm:$SPR),
3368 "mfdcr $RT, $SPR", IIC_SprMFSPR>, Requires<[IsPPC4xx]>;
3369 def MTDCR : XFXForm_1<31, 451, (outs), (ins gprc:$RT, i32imm:$SPR),
3370 "mtdcr $SPR, $RT", IIC_SprMTSPR>, Requires<[IsPPC4xx]>;
3372 def ATTN : XForm_attn<0, 256, (outs), (ins), "attn", IIC_BrB>;
3374 def LBZCIX : XForm_base_r3xo<31, 853, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3375 "lbzcix $RST, $A, $B", IIC_LdStLoad, []>;
3376 def LHZCIX : XForm_base_r3xo<31, 821, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3377 "lhzcix $RST, $A, $B", IIC_LdStLoad, []>;
3378 def LWZCIX : XForm_base_r3xo<31, 789, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3379 "lwzcix $RST, $A, $B", IIC_LdStLoad, []>;
3380 def LDCIX : XForm_base_r3xo<31, 885, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3381 "ldcix $RST, $A, $B", IIC_LdStLoad, []>;
3383 def STBCIX : XForm_base_r3xo<31, 981, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3384 "stbcix $RST, $A, $B", IIC_LdStLoad, []>;
3385 def STHCIX : XForm_base_r3xo<31, 949, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3386 "sthcix $RST, $A, $B", IIC_LdStLoad, []>;
3387 def STWCIX : XForm_base_r3xo<31, 917, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3388 "stwcix $RST, $A, $B", IIC_LdStLoad, []>;
3389 def STDCIX : XForm_base_r3xo<31, 1013, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3390 "stdcix $RST, $A, $B", IIC_LdStLoad, []>;
3392 //===----------------------------------------------------------------------===//
3393 // PowerPC Assembler Instruction Aliases
3396 // Pseudo-instructions for alternate assembly syntax (never used by codegen).
3397 // These are aliases that require C++ handling to convert to the target
3398 // instruction, while InstAliases can be handled directly by tblgen.
3399 class PPCAsmPseudo<string asm, dag iops>
3401 let Namespace = "PPC";
3402 bit PPC64 = 0; // Default value, override with isPPC64
3404 let OutOperandList = (outs);
3405 let InOperandList = iops;
3407 let AsmString = asm;
3408 let isAsmParserOnly = 1;
3412 def : InstAlias<"sc", (SC 0)>;
3414 def : InstAlias<"sync", (SYNC 0)>, Requires<[HasSYNC]>;
3415 def : InstAlias<"msync", (SYNC 0)>, Requires<[HasSYNC]>;
3416 def : InstAlias<"lwsync", (SYNC 1)>, Requires<[HasSYNC]>;
3417 def : InstAlias<"ptesync", (SYNC 2)>, Requires<[HasSYNC]>;
3419 def : InstAlias<"wait", (WAIT 0)>;
3420 def : InstAlias<"waitrsv", (WAIT 1)>;
3421 def : InstAlias<"waitimpl", (WAIT 2)>;
3423 def : InstAlias<"mbar", (MBAR 0)>, Requires<[IsBookE]>;
3425 def : InstAlias<"crset $bx", (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
3426 def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
3427 def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
3428 def : InstAlias<"crnot $bx, $by", (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
3430 def : InstAlias<"mtxer $Rx", (MTSPR 1, gprc:$Rx)>;
3431 def : InstAlias<"mfxer $Rx", (MFSPR gprc:$Rx, 1)>;
3433 def : InstAlias<"mfrtcu $Rx", (MFSPR gprc:$Rx, 4)>;
3434 def : InstAlias<"mfrtcl $Rx", (MFSPR gprc:$Rx, 5)>;
3436 def : InstAlias<"mtdscr $Rx", (MTSPR 17, gprc:$Rx)>;
3437 def : InstAlias<"mfdscr $Rx", (MFSPR gprc:$Rx, 17)>;
3439 def : InstAlias<"mtdsisr $Rx", (MTSPR 18, gprc:$Rx)>;
3440 def : InstAlias<"mfdsisr $Rx", (MFSPR gprc:$Rx, 18)>;
3442 def : InstAlias<"mtdar $Rx", (MTSPR 19, gprc:$Rx)>;
3443 def : InstAlias<"mfdar $Rx", (MFSPR gprc:$Rx, 19)>;
3445 def : InstAlias<"mtdec $Rx", (MTSPR 22, gprc:$Rx)>;
3446 def : InstAlias<"mfdec $Rx", (MFSPR gprc:$Rx, 22)>;
3448 def : InstAlias<"mtsdr1 $Rx", (MTSPR 25, gprc:$Rx)>;
3449 def : InstAlias<"mfsdr1 $Rx", (MFSPR gprc:$Rx, 25)>;
3451 def : InstAlias<"mtsrr0 $Rx", (MTSPR 26, gprc:$Rx)>;
3452 def : InstAlias<"mfsrr0 $Rx", (MFSPR gprc:$Rx, 26)>;
3454 def : InstAlias<"mtsrr1 $Rx", (MTSPR 27, gprc:$Rx)>;
3455 def : InstAlias<"mfsrr1 $Rx", (MFSPR gprc:$Rx, 27)>;
3457 def : InstAlias<"mtsrr2 $Rx", (MTSPR 990, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3458 def : InstAlias<"mfsrr2 $Rx", (MFSPR gprc:$Rx, 990)>, Requires<[IsPPC4xx]>;
3460 def : InstAlias<"mtsrr3 $Rx", (MTSPR 991, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3461 def : InstAlias<"mfsrr3 $Rx", (MFSPR gprc:$Rx, 991)>, Requires<[IsPPC4xx]>;
3463 def : InstAlias<"mtcfar $Rx", (MTSPR 28, gprc:$Rx)>;
3464 def : InstAlias<"mfcfar $Rx", (MFSPR gprc:$Rx, 28)>;
3466 def : InstAlias<"mtamr $Rx", (MTSPR 29, gprc:$Rx)>;
3467 def : InstAlias<"mfamr $Rx", (MFSPR gprc:$Rx, 29)>;
3469 def : InstAlias<"mtpid $Rx", (MTSPR 48, gprc:$Rx)>, Requires<[IsBookE]>;
3470 def : InstAlias<"mfpid $Rx", (MFSPR gprc:$Rx, 48)>, Requires<[IsBookE]>;
3472 def : InstAlias<"mftb $Rx", (MFTB gprc:$Rx, 268)>;
3473 def : InstAlias<"mftbl $Rx", (MFTB gprc:$Rx, 268)>;
3474 def : InstAlias<"mftbu $Rx", (MFTB gprc:$Rx, 269)>;
3476 def : InstAlias<"mttbl $Rx", (MTSPR 284, gprc:$Rx)>;
3477 def : InstAlias<"mttbu $Rx", (MTSPR 285, gprc:$Rx)>;
3479 def : InstAlias<"mftblo $Rx", (MFSPR gprc:$Rx, 989)>, Requires<[IsPPC4xx]>;
3480 def : InstAlias<"mttblo $Rx", (MTSPR 989, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3481 def : InstAlias<"mftbhi $Rx", (MFSPR gprc:$Rx, 988)>, Requires<[IsPPC4xx]>;
3482 def : InstAlias<"mttbhi $Rx", (MTSPR 988, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3484 def : InstAlias<"xnop", (XORI R0, R0, 0)>;
3486 def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3487 def : InstAlias<"mr. $rA, $rB", (OR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3489 def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3490 def : InstAlias<"not. $rA, $rB", (NOR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3492 def : InstAlias<"mtcr $rA", (MTCRF8 255, g8rc:$rA)>;
3494 foreach BATR = 0-3 in {
3495 def : InstAlias<"mtdbatu "#BATR#", $Rx",
3496 (MTSPR !add(BATR, !add(BATR, 536)), gprc:$Rx)>,
3497 Requires<[IsPPC6xx]>;
3498 def : InstAlias<"mfdbatu $Rx, "#BATR,
3499 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 536)))>,
3500 Requires<[IsPPC6xx]>;
3501 def : InstAlias<"mtdbatl "#BATR#", $Rx",
3502 (MTSPR !add(BATR, !add(BATR, 537)), gprc:$Rx)>,
3503 Requires<[IsPPC6xx]>;
3504 def : InstAlias<"mfdbatl $Rx, "#BATR,
3505 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 537)))>,
3506 Requires<[IsPPC6xx]>;
3507 def : InstAlias<"mtibatu "#BATR#", $Rx",
3508 (MTSPR !add(BATR, !add(BATR, 528)), gprc:$Rx)>,
3509 Requires<[IsPPC6xx]>;
3510 def : InstAlias<"mfibatu $Rx, "#BATR,
3511 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 528)))>,
3512 Requires<[IsPPC6xx]>;
3513 def : InstAlias<"mtibatl "#BATR#", $Rx",
3514 (MTSPR !add(BATR, !add(BATR, 529)), gprc:$Rx)>,
3515 Requires<[IsPPC6xx]>;
3516 def : InstAlias<"mfibatl $Rx, "#BATR,
3517 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 529)))>,
3518 Requires<[IsPPC6xx]>;
3521 foreach BR = 0-7 in {
3522 def : InstAlias<"mfbr"#BR#" $Rx",
3523 (MFDCR gprc:$Rx, !add(BR, 0x80))>,
3524 Requires<[IsPPC4xx]>;
3525 def : InstAlias<"mtbr"#BR#" $Rx",
3526 (MTDCR gprc:$Rx, !add(BR, 0x80))>,
3527 Requires<[IsPPC4xx]>;
3530 def : InstAlias<"mtdccr $Rx", (MTSPR 1018, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3531 def : InstAlias<"mfdccr $Rx", (MFSPR gprc:$Rx, 1018)>, Requires<[IsPPC4xx]>;
3533 def : InstAlias<"mticcr $Rx", (MTSPR 1019, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3534 def : InstAlias<"mficcr $Rx", (MFSPR gprc:$Rx, 1019)>, Requires<[IsPPC4xx]>;
3536 def : InstAlias<"mtdear $Rx", (MTSPR 981, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3537 def : InstAlias<"mfdear $Rx", (MFSPR gprc:$Rx, 981)>, Requires<[IsPPC4xx]>;
3539 def : InstAlias<"mtesr $Rx", (MTSPR 980, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3540 def : InstAlias<"mfesr $Rx", (MFSPR gprc:$Rx, 980)>, Requires<[IsPPC4xx]>;
3542 def : InstAlias<"mfspefscr $Rx", (MFSPR gprc:$Rx, 512)>;
3543 def : InstAlias<"mtspefscr $Rx", (MTSPR 512, gprc:$Rx)>;
3545 def : InstAlias<"mttcr $Rx", (MTSPR 986, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3546 def : InstAlias<"mftcr $Rx", (MFSPR gprc:$Rx, 986)>, Requires<[IsPPC4xx]>;
3548 def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>;
3550 def SUBI : PPCAsmPseudo<"subi $rA, $rB, $imm",
3551 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3552 def SUBIS : PPCAsmPseudo<"subis $rA, $rB, $imm",
3553 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3554 def SUBIC : PPCAsmPseudo<"subic $rA, $rB, $imm",
3555 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3556 def SUBICo : PPCAsmPseudo<"subic. $rA, $rB, $imm",
3557 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3559 def : InstAlias<"sub $rA, $rB, $rC", (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3560 def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3561 def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3562 def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3564 def : InstAlias<"mtmsrd $RS", (MTMSRD gprc:$RS, 0)>;
3565 def : InstAlias<"mtmsr $RS", (MTMSR gprc:$RS, 0)>;
3567 def : InstAlias<"mfasr $RT", (MFSPR gprc:$RT, 280)>;
3568 def : InstAlias<"mtasr $RT", (MTSPR 280, gprc:$RT)>;
3570 foreach SPRG = 0-3 in {
3571 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 272))>;
3572 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 272))>;
3573 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>;
3574 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>;
3576 foreach SPRG = 4-7 in {
3577 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 256))>,
3578 Requires<[IsBookE]>;
3579 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 256))>,
3580 Requires<[IsBookE]>;
3581 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>,
3582 Requires<[IsBookE]>;
3583 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>,
3584 Requires<[IsBookE]>;
3587 def : InstAlias<"mtasr $RS", (MTSPR 280, gprc:$RS)>;
3589 def : InstAlias<"mfdec $RT", (MFSPR gprc:$RT, 22)>;
3590 def : InstAlias<"mtdec $RT", (MTSPR 22, gprc:$RT)>;
3592 def : InstAlias<"mfpvr $RT", (MFSPR gprc:$RT, 287)>;
3594 def : InstAlias<"mfsdr1 $RT", (MFSPR gprc:$RT, 25)>;
3595 def : InstAlias<"mtsdr1 $RT", (MTSPR 25, gprc:$RT)>;
3597 def : InstAlias<"mfsrr0 $RT", (MFSPR gprc:$RT, 26)>;
3598 def : InstAlias<"mfsrr1 $RT", (MFSPR gprc:$RT, 27)>;
3599 def : InstAlias<"mtsrr0 $RT", (MTSPR 26, gprc:$RT)>;
3600 def : InstAlias<"mtsrr1 $RT", (MTSPR 27, gprc:$RT)>;
3602 def : InstAlias<"tlbie $RB", (TLBIE R0, gprc:$RB)>;
3604 def : InstAlias<"tlbrehi $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 0)>,
3605 Requires<[IsPPC4xx]>;
3606 def : InstAlias<"tlbrelo $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 1)>,
3607 Requires<[IsPPC4xx]>;
3608 def : InstAlias<"tlbwehi $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 0)>,
3609 Requires<[IsPPC4xx]>;
3610 def : InstAlias<"tlbwelo $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 1)>,
3611 Requires<[IsPPC4xx]>;
3613 def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b",
3614 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3615 def EXTLWIo : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b",
3616 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3617 def EXTRWI : PPCAsmPseudo<"extrwi $rA, $rS, $n, $b",
3618 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3619 def EXTRWIo : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b",
3620 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3621 def INSLWI : PPCAsmPseudo<"inslwi $rA, $rS, $n, $b",
3622 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3623 def INSLWIo : PPCAsmPseudo<"inslwi. $rA, $rS, $n, $b",
3624 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3625 def INSRWI : PPCAsmPseudo<"insrwi $rA, $rS, $n, $b",
3626 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3627 def INSRWIo : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b",
3628 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3629 def ROTRWI : PPCAsmPseudo<"rotrwi $rA, $rS, $n",
3630 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3631 def ROTRWIo : PPCAsmPseudo<"rotrwi. $rA, $rS, $n",
3632 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3633 def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n",
3634 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3635 def SLWIo : PPCAsmPseudo<"slwi. $rA, $rS, $n",
3636 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3637 def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n",
3638 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3639 def SRWIo : PPCAsmPseudo<"srwi. $rA, $rS, $n",
3640 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3641 def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n",
3642 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3643 def CLRRWIo : PPCAsmPseudo<"clrrwi. $rA, $rS, $n",
3644 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3645 def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n",
3646 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
3647 def CLRLSLWIo : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n",
3648 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
3650 def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
3651 def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
3652 def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
3653 def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNMo gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
3654 def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
3655 def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
3657 def : InstAlias<"cntlz $rA, $rS", (CNTLZW gprc:$rA, gprc:$rS)>;
3658 def : InstAlias<"cntlz. $rA, $rS", (CNTLZWo gprc:$rA, gprc:$rS)>;
3660 def EXTLDI : PPCAsmPseudo<"extldi $rA, $rS, $n, $b",
3661 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3662 def EXTLDIo : PPCAsmPseudo<"extldi. $rA, $rS, $n, $b",
3663 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3664 def EXTRDI : PPCAsmPseudo<"extrdi $rA, $rS, $n, $b",
3665 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3666 def EXTRDIo : PPCAsmPseudo<"extrdi. $rA, $rS, $n, $b",
3667 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3668 def INSRDI : PPCAsmPseudo<"insrdi $rA, $rS, $n, $b",
3669 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3670 def INSRDIo : PPCAsmPseudo<"insrdi. $rA, $rS, $n, $b",
3671 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3672 def ROTRDI : PPCAsmPseudo<"rotrdi $rA, $rS, $n",
3673 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3674 def ROTRDIo : PPCAsmPseudo<"rotrdi. $rA, $rS, $n",
3675 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3676 def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n",
3677 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3678 def SLDIo : PPCAsmPseudo<"sldi. $rA, $rS, $n",
3679 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3680 def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n",
3681 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3682 def SRDIo : PPCAsmPseudo<"srdi. $rA, $rS, $n",
3683 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3684 def CLRRDI : PPCAsmPseudo<"clrrdi $rA, $rS, $n",
3685 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3686 def CLRRDIo : PPCAsmPseudo<"clrrdi. $rA, $rS, $n",
3687 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3688 def CLRLSLDI : PPCAsmPseudo<"clrlsldi $rA, $rS, $b, $n",
3689 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
3690 def CLRLSLDIo : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n",
3691 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
3693 def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
3694 def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
3695 def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
3696 def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCLo g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
3697 def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
3698 def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
3700 // These generic branch instruction forms are used for the assembler parser only.
3701 // Defs and Uses are conservative, since we don't know the BO value.
3702 let PPC970_Unit = 7 in {
3703 let Defs = [CTR], Uses = [CTR, RM] in {
3704 def gBC : BForm_3<16, 0, 0, (outs),
3705 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
3706 "bc $bo, $bi, $dst">;
3707 def gBCA : BForm_3<16, 1, 0, (outs),
3708 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
3709 "bca $bo, $bi, $dst">;
3711 let Defs = [LR, CTR], Uses = [CTR, RM] in {
3712 def gBCL : BForm_3<16, 0, 1, (outs),
3713 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
3714 "bcl $bo, $bi, $dst">;
3715 def gBCLA : BForm_3<16, 1, 1, (outs),
3716 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
3717 "bcla $bo, $bi, $dst">;
3719 let Defs = [CTR], Uses = [CTR, LR, RM] in
3720 def gBCLR : XLForm_2<19, 16, 0, (outs),
3721 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3722 "bclr $bo, $bi, $bh", IIC_BrB, []>;
3723 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
3724 def gBCLRL : XLForm_2<19, 16, 1, (outs),
3725 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3726 "bclrl $bo, $bi, $bh", IIC_BrB, []>;
3727 let Defs = [CTR], Uses = [CTR, LR, RM] in
3728 def gBCCTR : XLForm_2<19, 528, 0, (outs),
3729 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3730 "bcctr $bo, $bi, $bh", IIC_BrB, []>;
3731 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
3732 def gBCCTRL : XLForm_2<19, 528, 1, (outs),
3733 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3734 "bcctrl $bo, $bi, $bh", IIC_BrB, []>;
3736 def : InstAlias<"bclr $bo, $bi", (gBCLR u5imm:$bo, crbitrc:$bi, 0)>;
3737 def : InstAlias<"bclrl $bo, $bi", (gBCLRL u5imm:$bo, crbitrc:$bi, 0)>;
3738 def : InstAlias<"bcctr $bo, $bi", (gBCCTR u5imm:$bo, crbitrc:$bi, 0)>;
3739 def : InstAlias<"bcctrl $bo, $bi", (gBCCTRL u5imm:$bo, crbitrc:$bi, 0)>;
3741 multiclass BranchSimpleMnemonic1<string name, string pm, int bo> {
3742 def : InstAlias<"b"#name#pm#" $bi, $dst", (gBC bo, crbitrc:$bi, condbrtarget:$dst)>;
3743 def : InstAlias<"b"#name#"a"#pm#" $bi, $dst", (gBCA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
3744 def : InstAlias<"b"#name#"lr"#pm#" $bi", (gBCLR bo, crbitrc:$bi, 0)>;
3745 def : InstAlias<"b"#name#"l"#pm#" $bi, $dst", (gBCL bo, crbitrc:$bi, condbrtarget:$dst)>;
3746 def : InstAlias<"b"#name#"la"#pm#" $bi, $dst", (gBCLA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
3747 def : InstAlias<"b"#name#"lrl"#pm#" $bi", (gBCLRL bo, crbitrc:$bi, 0)>;
3749 multiclass BranchSimpleMnemonic2<string name, string pm, int bo>
3750 : BranchSimpleMnemonic1<name, pm, bo> {
3751 def : InstAlias<"b"#name#"ctr"#pm#" $bi", (gBCCTR bo, crbitrc:$bi, 0)>;
3752 def : InstAlias<"b"#name#"ctrl"#pm#" $bi", (gBCCTRL bo, crbitrc:$bi, 0)>;
3754 defm : BranchSimpleMnemonic2<"t", "", 12>;
3755 defm : BranchSimpleMnemonic2<"f", "", 4>;
3756 defm : BranchSimpleMnemonic2<"t", "-", 14>;
3757 defm : BranchSimpleMnemonic2<"f", "-", 6>;
3758 defm : BranchSimpleMnemonic2<"t", "+", 15>;
3759 defm : BranchSimpleMnemonic2<"f", "+", 7>;
3760 defm : BranchSimpleMnemonic1<"dnzt", "", 8>;
3761 defm : BranchSimpleMnemonic1<"dnzf", "", 0>;
3762 defm : BranchSimpleMnemonic1<"dzt", "", 10>;
3763 defm : BranchSimpleMnemonic1<"dzf", "", 2>;
3765 multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> {
3766 def : InstAlias<"b"#name#pm#" $cc, $dst",
3767 (BCC bibo, crrc:$cc, condbrtarget:$dst)>;
3768 def : InstAlias<"b"#name#pm#" $dst",
3769 (BCC bibo, CR0, condbrtarget:$dst)>;
3771 def : InstAlias<"b"#name#"a"#pm#" $cc, $dst",
3772 (BCCA bibo, crrc:$cc, abscondbrtarget:$dst)>;
3773 def : InstAlias<"b"#name#"a"#pm#" $dst",
3774 (BCCA bibo, CR0, abscondbrtarget:$dst)>;
3776 def : InstAlias<"b"#name#"lr"#pm#" $cc",
3777 (BCCLR bibo, crrc:$cc)>;
3778 def : InstAlias<"b"#name#"lr"#pm,
3781 def : InstAlias<"b"#name#"ctr"#pm#" $cc",
3782 (BCCCTR bibo, crrc:$cc)>;
3783 def : InstAlias<"b"#name#"ctr"#pm,
3784 (BCCCTR bibo, CR0)>;
3786 def : InstAlias<"b"#name#"l"#pm#" $cc, $dst",
3787 (BCCL bibo, crrc:$cc, condbrtarget:$dst)>;
3788 def : InstAlias<"b"#name#"l"#pm#" $dst",
3789 (BCCL bibo, CR0, condbrtarget:$dst)>;
3791 def : InstAlias<"b"#name#"la"#pm#" $cc, $dst",
3792 (BCCLA bibo, crrc:$cc, abscondbrtarget:$dst)>;
3793 def : InstAlias<"b"#name#"la"#pm#" $dst",
3794 (BCCLA bibo, CR0, abscondbrtarget:$dst)>;
3796 def : InstAlias<"b"#name#"lrl"#pm#" $cc",
3797 (BCCLRL bibo, crrc:$cc)>;
3798 def : InstAlias<"b"#name#"lrl"#pm,
3799 (BCCLRL bibo, CR0)>;
3801 def : InstAlias<"b"#name#"ctrl"#pm#" $cc",
3802 (BCCCTRL bibo, crrc:$cc)>;
3803 def : InstAlias<"b"#name#"ctrl"#pm,
3804 (BCCCTRL bibo, CR0)>;
3806 multiclass BranchExtendedMnemonic<string name, int bibo> {
3807 defm : BranchExtendedMnemonicPM<name, "", bibo>;
3808 defm : BranchExtendedMnemonicPM<name, "-", !add(bibo, 2)>;
3809 defm : BranchExtendedMnemonicPM<name, "+", !add(bibo, 3)>;
3811 defm : BranchExtendedMnemonic<"lt", 12>;
3812 defm : BranchExtendedMnemonic<"gt", 44>;
3813 defm : BranchExtendedMnemonic<"eq", 76>;
3814 defm : BranchExtendedMnemonic<"un", 108>;
3815 defm : BranchExtendedMnemonic<"so", 108>;
3816 defm : BranchExtendedMnemonic<"ge", 4>;
3817 defm : BranchExtendedMnemonic<"nl", 4>;
3818 defm : BranchExtendedMnemonic<"le", 36>;
3819 defm : BranchExtendedMnemonic<"ng", 36>;
3820 defm : BranchExtendedMnemonic<"ne", 68>;
3821 defm : BranchExtendedMnemonic<"nu", 100>;
3822 defm : BranchExtendedMnemonic<"ns", 100>;
3824 def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>;
3825 def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>;
3826 def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>;
3827 def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>;
3828 def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm64:$imm)>;
3829 def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>;
3830 def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm64:$imm)>;
3831 def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>;
3833 def : InstAlias<"cmpi $bf, 0, $rA, $imm", (CMPWI crrc:$bf, gprc:$rA, s16imm:$imm)>;
3834 def : InstAlias<"cmp $bf, 0, $rA, $rB", (CMPW crrc:$bf, gprc:$rA, gprc:$rB)>;
3835 def : InstAlias<"cmpli $bf, 0, $rA, $imm", (CMPLWI crrc:$bf, gprc:$rA, u16imm:$imm)>;
3836 def : InstAlias<"cmpl $bf, 0, $rA, $rB", (CMPLW crrc:$bf, gprc:$rA, gprc:$rB)>;
3837 def : InstAlias<"cmpi $bf, 1, $rA, $imm", (CMPDI crrc:$bf, g8rc:$rA, s16imm64:$imm)>;
3838 def : InstAlias<"cmp $bf, 1, $rA, $rB", (CMPD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
3839 def : InstAlias<"cmpli $bf, 1, $rA, $imm", (CMPLDI crrc:$bf, g8rc:$rA, u16imm64:$imm)>;
3840 def : InstAlias<"cmpl $bf, 1, $rA, $rB", (CMPLD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
3842 multiclass TrapExtendedMnemonic<string name, int to> {
3843 def : InstAlias<"td"#name#"i $rA, $imm", (TDI to, g8rc:$rA, s16imm:$imm)>;
3844 def : InstAlias<"td"#name#" $rA, $rB", (TD to, g8rc:$rA, g8rc:$rB)>;
3845 def : InstAlias<"tw"#name#"i $rA, $imm", (TWI to, gprc:$rA, s16imm:$imm)>;
3846 def : InstAlias<"tw"#name#" $rA, $rB", (TW to, gprc:$rA, gprc:$rB)>;
3848 defm : TrapExtendedMnemonic<"lt", 16>;
3849 defm : TrapExtendedMnemonic<"le", 20>;
3850 defm : TrapExtendedMnemonic<"eq", 4>;
3851 defm : TrapExtendedMnemonic<"ge", 12>;
3852 defm : TrapExtendedMnemonic<"gt", 8>;
3853 defm : TrapExtendedMnemonic<"nl", 12>;
3854 defm : TrapExtendedMnemonic<"ne", 24>;
3855 defm : TrapExtendedMnemonic<"ng", 20>;
3856 defm : TrapExtendedMnemonic<"llt", 2>;
3857 defm : TrapExtendedMnemonic<"lle", 6>;
3858 defm : TrapExtendedMnemonic<"lge", 5>;
3859 defm : TrapExtendedMnemonic<"lgt", 1>;
3860 defm : TrapExtendedMnemonic<"lnl", 5>;
3861 defm : TrapExtendedMnemonic<"lng", 6>;
3862 defm : TrapExtendedMnemonic<"u", 31>;
3865 def : Pat<(atomic_load_8 iaddr:$src), (LBZ memri:$src)>;
3866 def : Pat<(atomic_load_16 iaddr:$src), (LHZ memri:$src)>;
3867 def : Pat<(atomic_load_32 iaddr:$src), (LWZ memri:$src)>;
3868 def : Pat<(atomic_load_8 xaddr:$src), (LBZX memrr:$src)>;
3869 def : Pat<(atomic_load_16 xaddr:$src), (LHZX memrr:$src)>;
3870 def : Pat<(atomic_load_32 xaddr:$src), (LWZX memrr:$src)>;
3873 def : Pat<(atomic_store_8 iaddr:$ptr, i32:$val), (STB gprc:$val, memri:$ptr)>;
3874 def : Pat<(atomic_store_16 iaddr:$ptr, i32:$val), (STH gprc:$val, memri:$ptr)>;
3875 def : Pat<(atomic_store_32 iaddr:$ptr, i32:$val), (STW gprc:$val, memri:$ptr)>;
3876 def : Pat<(atomic_store_8 xaddr:$ptr, i32:$val), (STBX gprc:$val, memrr:$ptr)>;
3877 def : Pat<(atomic_store_16 xaddr:$ptr, i32:$val), (STHX gprc:$val, memrr:$ptr)>;
3878 def : Pat<(atomic_store_32 xaddr:$ptr, i32:$val), (STWX gprc:$val, memrr:$ptr)>;