1 //===- PowerPCInstrInfo.td - The PowerPC Instruction Set -----*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PowerPCInstrFormats.td"
17 let isTerminator = 1, isReturn = 1 in
18 def BLR : XLForm_2_ext<"blr", 19, 16, 20, 31, 1, 0, 0>;
20 class II<dag OL, string asmstr> {
22 string AsmString = asmstr;
25 def u5imm : Operand<i8> {
26 let PrintMethod = "printU5ImmOperand";
28 def u16imm : Operand<i16> {
29 let PrintMethod = "printU16ImmOperand";
33 // Pseudo-instructions:
34 def PHI : Pseudo<"PHI">; // PHI node...
35 def ADJCALLSTACKDOWN : Pseudo<"ADJCALLSTACKDOWN">;
36 def ADJCALLSTACKUP : Pseudo<"ADJCALLSTACKUP">;
38 def MovePCtoLR : Pseudo<"MovePCtoLR">;
39 def IMPLICIT_DEF : Pseudo<"IMPLICIT_DEF">;
41 def LA : DForm_2<"la", 14, 0, 0>;
42 def LOADHiAddr : DForm_2_r0<"addis", 15, 0, 0>;
44 def ADDI : DForm_2<"addi", 14, 0, 0>;
45 def ADDIS : DForm_2<"addis", 15, 0, 0>;
46 def SUBI : DForm_2<"subi", 14, 0, 0>;
47 def LI : DForm_2_r0<"li", 14, 0, 0>;
48 def LIS : DForm_2_r0<"lis", 15, 0, 0>;
49 def ADDIC : DForm_2<"addic", 12, 0, 0>;
50 def ADD : XOForm_1<"add", 31, 266, 0, 0, 0, 0>;
51 def ADDC : XOForm_1<"addc", 31, 10, 0, 0, 0, 0>;
52 def ADDE : XOForm_1<"adde", 31, 138, 0, 0, 0, 0>;
53 def ADDZE : XOForm_3<"addze", 31, 202, 0, 0, 0, 0>;
54 def ANDIo : DForm_4<28, 0, 0,
55 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
56 "andi. $dst, $src1, $src2">;
58 let isBranch = 1, isTerminator = 1 in {
59 def COND_BRANCH : Pseudo<"COND_BRANCH">;
60 def B : IForm<"b", 18, 0, 0, 0, 0>;
61 // FIXME: 4*CR# needs to be added to the BI field!
62 // This will only work for CR0 as it stands now
63 def BLT : BForm_ext<"blt", 16, 0, 0, 12, 0, 0, 0>;
64 def BLE : BForm_ext<"ble", 16, 0, 0, 4, 1, 0, 0>;
65 def BEQ : BForm_ext<"beq", 16, 0, 0, 12, 2, 0, 0>;
66 def BGE : BForm_ext<"bge", 16, 0, 0, 4, 0, 0, 0>;
67 def BGT : BForm_ext<"bgt", 16, 0, 0, 12, 1, 0, 0>;
68 def BNE : BForm_ext<"bne", 16, 0, 0, 4, 2, 0, 0>;
71 let isBranch = 1, isTerminator = 1, isCall = 1,
72 // All calls clobber the non-callee saved registers...
73 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
74 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
76 CR0,CR1,CR5,CR6,CR7] in {
77 // Convenient aliases for call instructions
78 def CALLpcrel : IForm<"bl", 18, 0, 1, 0, 0>;
79 def CALLindirect : XLForm_2_ext<"bctrl", 19, 528, 20, 31, 1, 0, 0>;
82 def CMPI : DForm_5<"cmpi", 11, 0, 0>;
83 def CMPWI : DForm_5_ext<"cmpwi", 11, 0, 0>;
84 def CMPDI : DForm_5_ext<"cmpdi", 11, 1, 0>;
85 def CMP : XForm_16<"cmp", 31, 0, 0, 0>;
86 def CMPW : XForm_16_ext<"cmpw", 31, 0, 0, 0>;
87 def CMPD : XForm_16_ext<"cmpd", 31, 0, 1, 0>;
88 def CMPLI : DForm_6<10, 0, 0,
89 (ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2),
90 "cmpli $dst, $size, $src1, $src2">;
91 def CMPLWI : DForm_6_ext<10, 0, 0,
92 (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
93 "cmplwi $dst, $src1, $src2">;
94 def CMPLDI : DForm_6_ext<10, 1, 0,
95 (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
96 "cmpldi $dst, $src1, $src2">;
97 def CMPL : XForm_16<"cmpl", 31, 32, 0, 0>;
98 def CMPLW : XForm_16_ext<"cmplw", 31, 32, 0, 0>;
99 def CMPLD : XForm_16_ext<"cmpld", 31, 32, 1, 0>;
100 def DIVW : XOForm_1<"divw", 31, 491, 0, 0, 0, 0>;
101 def DIVWU : XOForm_1<"divwu", 31, 459, 0, 0, 0, 0>;
102 def FADD : AForm_2<"fadd", 63, 21, 0, 0, 0>;
103 def FADDS : AForm_2<"fadds", 59, 21, 0, 0, 0>;
104 def FSUB : AForm_2<"fsub", 63, 20, 0, 0, 0>;
105 def FSUBS : AForm_2<"fsubs", 59, 20, 0, 0, 0>;
106 def FMUL : AForm_3<"fmul", 63, 25, 0, 0, 0>;
107 def FMULS : AForm_3<"fmuls", 59, 25, 0, 0, 0>;
108 def FDIV : AForm_2<"fdiv", 63, 18, 0, 0, 0>;
109 def FDIVS : AForm_2<"fdivs", 59, 18, 0, 0, 0>;
110 def FSEL : AForm_1<"fsel", 63, 23, 0, 0, 0>;
111 def FCMPU : XForm_17<"fcmpu", 63, 0, 0, 0>;
112 def LBZ : DForm_1<"lbz", 35, 0, 0>;
113 def LHA : DForm_1<"lha", 42, 0, 0>;
114 def LHZ : DForm_1<"lhz", 40, 0, 0>;
115 def LWZ : DForm_1<"lwz", 32, 0, 0>;
116 def LWA : DSForm_1<"lwa", 58, 2, 1, 0>;
117 def LD : DSForm_2<"ld", 58, 0, 1, 0>;
118 def LMW : DForm_1<"lmw", 46, 0, 0>;
119 def STMW : DForm_3<"stmw", 47, 0, 0>;
120 def LFS : DForm_8<"lfs", 48, 0, 0>;
121 def LFD : DForm_8<"lfd", 50, 0, 0>;
122 def MFLR : XFXForm_1_ext<"", 31, 399, 8, 0, 0>,
123 II<(ops GPRC:$reg), "mflr $reg">;
124 def MFCTR : XFXForm_1_ext<"mfctr", 31, 399, 9, 0, 0>;
125 def MTLR : XFXForm_7_ext<"mtlr", 31, 467, 8, 0, 0>;
126 def MTCTR : XFXForm_7_ext<"mtctr", 31, 467, 9, 0, 0>;
127 def MULLD : XOForm_1<"mulld", 31, 233, 0, 0, 1, 0>;
128 def MULLW : XOForm_1<"mullw", 31, 235, 0, 0, 0, 0>;
129 def MULHWU : XOForm_2<"mulhwu", 31, 11, 0, 0, 0>;
130 def NEG : XOForm_3<"neg", 31, 104, 0, 0, 0, 0>;
131 def NOP : DForm_4_zero<"nop", 24, 0, 0, (ops), "nop">;
132 def ORI : DForm_4<24, 0, 0,
133 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
134 "ori $dst, $src1, $src2">;
135 def ORIS : DForm_4<25, 0, 0,
136 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
137 "oris $dst, $src1, $src2">;
138 def RLDICL : MDForm_1<"rldicl", 30, 0, 0, 1, 0>;
139 def RLDICR : MDForm_1<"rldicr", 30, 1, 0, 1, 0>;
140 def RLWINM : MForm_2<"rlwinm", 21, 0, 0, 0>;
141 def RLWNM : MForm_1<"rlwnm", 23, 0, 0, 0>;
142 def RLWIMI : MForm_2<"rlwimi", 20, 0, 0, 0>;
143 def SRADI : XSForm_1<"sradi", 31, 413, 0, 1, 0>;
144 def SRWI : MForm_2<"srwi", 21, 0, 0, 0>;
145 def STB : DForm_3<"stb", 38, 0, 0>;
146 def STBU : DForm_3<"stbu", 39, 0, 0>;
147 def STH : DForm_3<"sth", 44, 0, 0>;
148 def STHU : DForm_3<"sthu", 45, 0, 0>;
149 def STW : DForm_3<"stw", 36, 0, 0>;
150 def STWU : DForm_3<"stwu", 37, 0, 0>;
151 def STD : DSForm_2<"std", 62, 0, 1, 0>;
152 def STDU : DSForm_2<"stdu", 62, 1, 1, 0>;
153 def STFS : DForm_9<"stfs", 52, 0, 0>;
154 def STFD : DForm_9<"stfd", 54, 0, 0>;
155 def SUBFIC : DForm_2<"subfic", 8, 0, 0>;
156 def SUB : XOForm_1_rev<"sub", 31, 40, 0, 0, 0, 0>;
157 def SUBF : XOForm_1<"subf", 31, 40, 0, 0, 0, 0>;
158 def SUBC : XOForm_1_rev<"subc", 31, 8, 0, 0, 0, 0>;
159 def SUBFC : XOForm_1<"subfc", 31, 8, 0, 0, 0, 0>;
160 def SUBFE : XOForm_1<"subfe", 31, 136, 0, 0, 0, 0>;
161 def SUBFZE : XOForm_3<"subfze", 31, 200, 0, 0, 0, 0>;
162 def XORI : DForm_4<26, 0, 0,
163 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
164 "xori $dst, $src1, $src2">;
165 def XORIS : DForm_4<27, 0, 0,
166 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
167 "xoris $dst, $src1, $src2">;
168 def MULLI : DForm_2<"mulli", 7, 0, 0>;
171 def LBZX : XForm_1<31, 87, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
172 "lbzx $dst, $base, $index">;
173 def LHAX : XForm_1<31, 343, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
174 "lhax $dst, $base, $index">;
175 def LHZX : XForm_1<31, 279, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
176 "lhzx $dst, $base, $index">;
177 def LWAX : XForm_1<31, 341, 1, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
178 "lwax $dst, $base, $index">;
179 def LWZX : XForm_1<31, 23, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
180 "lwzx $dst, $base, $index">;
181 def LDX : XForm_1<31, 21, 1, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
182 "ldx $dst, $base, $index">;
183 def MFCR : XForm_5<31, 19, 0, 0, (ops GPRC:$dst), "mfcr $dst">;
184 def AND : XForm_6<31, 28, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
185 "and $rA, $rS, $rB">;
186 def ANDC : XForm_6<31, 60, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
187 "andc $rA, $rS, $rB">;
188 def EQV : XForm_6<31, 284, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
189 "eqv $rA, $rS, $rB">;
190 def NAND : XForm_6<31, 476, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
191 "nand $rA, $rS, $rB">;
192 def NOR : XForm_6<31, 124, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
193 "nor $rA, $rS, $rB">;
194 def OR : XForm_6<31, 444, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
196 def ORo : XForm_6<31, 444, 1, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
197 "or. $rA, $rS, $rB">;
198 def ORC : XForm_6<31, 412, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
199 "orc $rA, $rS, $rB">;
200 def SLD : XForm_6<31, 27, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
201 "sld $rA, $rS, $rB">;
202 def SLW : XForm_6<31, 24, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
203 "slw $rA, $rS, $rB">;
204 def SRD : XForm_6<31, 539, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
205 "srd $rA, $rS, $rB">;
206 def SRW : XForm_6<31, 536, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
207 "srw $rA, $rS, $rB">;
208 def SRAD : XForm_6<31, 794, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
209 "srad $rA, $rS, $rB">;
210 def SRAW : XForm_6<31, 792, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
211 "sraw $rA, $rS, $rB">;
212 def XOR : XForm_6<31, 316, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
213 "xor $rA, $rS, $rB">;
214 def STBX : XForm_8<31, 215, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
215 "stbx $rS, $rA, $rB">;
216 def STHX : XForm_8<31, 407, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
217 "sthx $rS, $rA, $rB">;
218 def STWX : XForm_8<31, 151, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
219 "stwx $rS, $rA, $rB">;
220 def STWUX : XForm_8<31, 183, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
221 "stwux $rS, $rA, $rB">;
222 def STDX : XForm_8<31, 149, 1, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
223 "stdx $rS, $rA, $rB">;
224 def STDUX : XForm_8<31, 181, 1, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
225 "stdux $rS, $rA, $rB">;
226 def SRAWI : XForm_10<31, 824, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
227 "srawi $rA, $rS, $SH">;
228 def CNTLZW : XForm_11<31, 26, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS),
230 def EXTSB : XForm_11<31, 954, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS),
232 def EXTSH : XForm_11<31, 922, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS),
234 def LFSX : XForm_25<31, 535, 0, 0, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
235 "lfsx $dst, $base, $index">;
236 def LFDX : XForm_25<31, 599, 0, 0, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
237 "lfdx $dst, $base, $index">;
238 def FMR : XForm_26<63, 72, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
240 def FNEG : XForm_26<63, 80, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
242 def FRSP : XForm_26<63, 12, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
244 def FCTIWZ : XForm_26<63, 15, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
245 "fctiwz $frD, $frB">;
246 def STFSX : XForm_28<31, 663, 0, 0, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
247 "stfsx $frS, $rA, $rB">;
248 def STFDX : XForm_28<31, 727, 0, 0, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
249 "stfdx $frS, $rA, $rB">;
250 def CRAND : XLForm_1<19, 257, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B),
252 def CRANDC : XLForm_1<19, 129, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B),
253 "crandc $D, $A, $B">;
254 def CRNOR : XLForm_1<19, 33, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B),
256 def CROR : XLForm_1<19, 449, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B),