1 //===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPCShiftOp : SDTypeProfile<1, 2, [ // PPCshl, PPCsra, PPCsrl
24 SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32>
26 def SDT_PPCCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
28 def SDT_PPCvperm : SDTypeProfile<1, 3, [
29 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
32 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
33 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
36 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
37 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
40 def SDT_PPClbrx : SDTypeProfile<1, 3, [
41 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
43 def SDT_PPCstbrx : SDTypeProfile<0, 4, [
44 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
47 //===----------------------------------------------------------------------===//
48 // PowerPC specific DAG Nodes.
51 def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>;
52 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
53 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
54 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx, [SDNPHasChain]>;
56 def PPCfsel : SDNode<"PPCISD::FSEL",
57 // Type constraint for fsel.
58 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
59 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
61 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
62 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
63 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
64 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
66 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
68 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
69 // amounts. These nodes are generated by the multi-precision shift code.
70 def PPCsrl : SDNode<"PPCISD::SRL" , SDT_PPCShiftOp>;
71 def PPCsra : SDNode<"PPCISD::SRA" , SDT_PPCShiftOp>;
72 def PPCshl : SDNode<"PPCISD::SHL" , SDT_PPCShiftOp>;
74 def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>;
75 def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore, [SDNPHasChain]>;
77 // These are target-independent nodes, but have target-specific formats.
78 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeq,
79 [SDNPHasChain, SDNPOutFlag]>;
80 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeq,
81 [SDNPHasChain, SDNPOutFlag]>;
83 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
84 def PPCcall_Macho : SDNode<"PPCISD::CALL_Macho", SDT_PPCCall,
85 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
86 def PPCcall_ELF : SDNode<"PPCISD::CALL_ELF", SDT_PPCCall,
87 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
88 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
89 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
90 def PPCbctrl_Macho : SDNode<"PPCISD::BCTRL_Macho", SDTRet,
91 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
93 def PPCbctrl_ELF : SDNode<"PPCISD::BCTRL_ELF", SDTRet,
94 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
96 def retflag : SDNode<"PPCISD::RET_FLAG", SDTRet,
97 [SDNPHasChain, SDNPOptInFlag]>;
99 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
100 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutFlag]>;
102 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
103 [SDNPHasChain, SDNPOptInFlag]>;
105 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx, [SDNPHasChain]>;
106 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx, [SDNPHasChain]>;
108 // Instructions to support dynamic alloca.
109 def SDTDynOp : SDTypeProfile<1, 2, []>;
110 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
112 //===----------------------------------------------------------------------===//
113 // PowerPC specific transformation functions and pattern fragments.
116 def SHL32 : SDNodeXForm<imm, [{
117 // Transformation function: 31 - imm
118 return getI32Imm(31 - N->getValue());
121 def SRL32 : SDNodeXForm<imm, [{
122 // Transformation function: 32 - imm
123 return N->getValue() ? getI32Imm(32 - N->getValue()) : getI32Imm(0);
126 def LO16 : SDNodeXForm<imm, [{
127 // Transformation function: get the low 16 bits.
128 return getI32Imm((unsigned short)N->getValue());
131 def HI16 : SDNodeXForm<imm, [{
132 // Transformation function: shift the immediate value down into the low bits.
133 return getI32Imm((unsigned)N->getValue() >> 16);
136 def HA16 : SDNodeXForm<imm, [{
137 // Transformation function: shift the immediate value down into the low bits.
138 signed int Val = N->getValue();
139 return getI32Imm((Val - (signed short)Val) >> 16);
141 def MB : SDNodeXForm<imm, [{
142 // Transformation function: get the start bit of a mask
144 (void)isRunOfOnes((unsigned)N->getValue(), mb, me);
145 return getI32Imm(mb);
148 def ME : SDNodeXForm<imm, [{
149 // Transformation function: get the end bit of a mask
151 (void)isRunOfOnes((unsigned)N->getValue(), mb, me);
152 return getI32Imm(me);
154 def maskimm32 : PatLeaf<(imm), [{
155 // maskImm predicate - True if immediate is a run of ones.
157 if (N->getValueType(0) == MVT::i32)
158 return isRunOfOnes((unsigned)N->getValue(), mb, me);
163 def immSExt16 : PatLeaf<(imm), [{
164 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
165 // field. Used by instructions like 'addi'.
166 if (N->getValueType(0) == MVT::i32)
167 return (int32_t)N->getValue() == (short)N->getValue();
169 return (int64_t)N->getValue() == (short)N->getValue();
171 def immZExt16 : PatLeaf<(imm), [{
172 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
173 // field. Used by instructions like 'ori'.
174 return (uint64_t)N->getValue() == (unsigned short)N->getValue();
177 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
178 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
179 // identical in 32-bit mode, but in 64-bit mode, they return true if the
180 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
182 def imm16ShiftedZExt : PatLeaf<(imm), [{
183 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
184 // immediate are set. Used by instructions like 'xoris'.
185 return (N->getValue() & ~uint64_t(0xFFFF0000)) == 0;
188 def imm16ShiftedSExt : PatLeaf<(imm), [{
189 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
190 // immediate are set. Used by instructions like 'addis'. Identical to
191 // imm16ShiftedZExt in 32-bit mode.
192 if (N->getValue() & 0xFFFF) return false;
193 if (N->getValueType(0) == MVT::i32)
195 // For 64-bit, make sure it is sext right.
196 return N->getValue() == (uint64_t)(int)N->getValue();
200 //===----------------------------------------------------------------------===//
201 // PowerPC Flag Definitions.
203 class isPPC64 { bit PPC64 = 1; }
205 list<Register> Defs = [CR0];
209 class RegConstraint<string C> {
210 string Constraints = C;
212 class NoEncode<string E> {
213 string DisableEncoding = E;
217 //===----------------------------------------------------------------------===//
218 // PowerPC Operand Definitions.
220 def s5imm : Operand<i32> {
221 let PrintMethod = "printS5ImmOperand";
223 def u5imm : Operand<i32> {
224 let PrintMethod = "printU5ImmOperand";
226 def u6imm : Operand<i32> {
227 let PrintMethod = "printU6ImmOperand";
229 def s16imm : Operand<i32> {
230 let PrintMethod = "printS16ImmOperand";
232 def u16imm : Operand<i32> {
233 let PrintMethod = "printU16ImmOperand";
235 def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing.
236 let PrintMethod = "printS16X4ImmOperand";
238 def target : Operand<OtherVT> {
239 let PrintMethod = "printBranchOperand";
241 def calltarget : Operand<iPTR> {
242 let PrintMethod = "printCallOperand";
244 def aaddr : Operand<iPTR> {
245 let PrintMethod = "printAbsAddrOperand";
247 def piclabel: Operand<iPTR> {
248 let PrintMethod = "printPICLabel";
250 def symbolHi: Operand<i32> {
251 let PrintMethod = "printSymbolHi";
253 def symbolLo: Operand<i32> {
254 let PrintMethod = "printSymbolLo";
256 def crbitm: Operand<i8> {
257 let PrintMethod = "printcrbitm";
260 def memri : Operand<iPTR> {
261 let PrintMethod = "printMemRegImm";
262 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg);
264 def memrr : Operand<iPTR> {
265 let PrintMethod = "printMemRegReg";
266 let MIOperandInfo = (ops ptr_rc, ptr_rc);
268 def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits.
269 let PrintMethod = "printMemRegImmShifted";
270 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg);
273 // PowerPC Predicate operand. 20 = (0<<5)|20 = always, CR0 is a dummy reg
274 // that doesn't matter.
275 def pred : PredicateOperand<OtherVT, (ops imm, CRRC),
276 (ops (i32 20), CR0)> {
277 let PrintMethod = "printPredicateOperand";
280 // Define PowerPC specific addressing mode.
281 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
282 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
283 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
284 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std"
286 /// This is just the offset part of iaddr, used for preinc.
287 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
289 //===----------------------------------------------------------------------===//
290 // PowerPC Instruction Predicate Definitions.
291 def FPContractions : Predicate<"!NoExcessFPPrecision">;
294 //===----------------------------------------------------------------------===//
295 // PowerPC Instruction Definitions.
297 // Pseudo-instructions:
299 let hasCtrlDep = 1 in {
300 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt),
301 "${:comment} ADJCALLSTACKDOWN",
302 [(callseq_start imm:$amt)]>, Imp<[R1],[R1]>;
303 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt),
304 "${:comment} ADJCALLSTACKUP",
305 [(callseq_end imm:$amt)]>, Imp<[R1],[R1]>;
307 def UPDATE_VRSAVE : Pseudo<(outs GPRC:$rD), (ins GPRC:$rS),
308 "UPDATE_VRSAVE $rD, $rS", []>;
311 def DYNALLOC : Pseudo<(outs GPRC:$result), (ins GPRC:$negsize, memri:$fpsi),
312 "${:comment} DYNALLOC $result, $negsize, $fpsi",
314 (PPCdynalloc GPRC:$negsize, iaddr:$fpsi))]>,
317 def IMPLICIT_DEF_GPRC: Pseudo<(outs GPRC:$rD), (ins),
318 "${:comment}IMPLICIT_DEF_GPRC $rD",
319 [(set GPRC:$rD, (undef))]>;
320 def IMPLICIT_DEF_F8 : Pseudo<(outs F8RC:$rD), (ins),
321 "${:comment} IMPLICIT_DEF_F8 $rD",
322 [(set F8RC:$rD, (undef))]>;
323 def IMPLICIT_DEF_F4 : Pseudo<(outs F4RC:$rD), (ins),
324 "${:comment} IMPLICIT_DEF_F4 $rD",
325 [(set F4RC:$rD, (undef))]>;
327 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
328 // scheduler into a branch sequence.
329 let usesCustomDAGSchedInserter = 1, // Expanded by the scheduler.
330 PPC970_Single = 1 in {
331 def SELECT_CC_I4 : Pseudo<(outs GPRC:$dst), (ins CRRC:$cond, GPRC:$T, GPRC:$F,
332 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
334 def SELECT_CC_I8 : Pseudo<(outs G8RC:$dst), (ins CRRC:$cond, G8RC:$T, G8RC:$F,
335 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
337 def SELECT_CC_F4 : Pseudo<(outs F4RC:$dst), (ins CRRC:$cond, F4RC:$T, F4RC:$F,
338 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
340 def SELECT_CC_F8 : Pseudo<(outs F8RC:$dst), (ins CRRC:$cond, F8RC:$T, F8RC:$F,
341 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
343 def SELECT_CC_VRRC: Pseudo<(outs VRRC:$dst), (ins CRRC:$cond, VRRC:$T, VRRC:$F,
344 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
348 let isTerminator = 1, isBarrier = 1, noResults = 1, PPC970_Unit = 7 in {
350 def BLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$p),
351 "b${p:cc}lr ${p:reg}", BrB,
353 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>;
359 def MovePCtoLR : Pseudo<(outs), (ins piclabel:$label), "bl $label", []>,
362 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1,
363 noResults = 1, PPC970_Unit = 7 in {
364 let isBarrier = 1 in {
365 def B : IForm<18, 0, 0, (outs), (ins target:$dst),
370 // BCC represents an arbitrary conditional branch on a predicate.
371 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
372 // a two-value operand where a dag node expects two operands. :(
373 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, target:$dst),
374 "b${cond:cc} ${cond:reg}, $dst"
375 /*[(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]*/>;
379 let isCall = 1, noResults = 1, PPC970_Unit = 7,
380 // All calls clobber the non-callee saved registers...
381 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
382 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
383 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
385 CR0,CR1,CR5,CR6,CR7] in {
386 // Convenient aliases for call instructions
387 def BL_Macho : IForm<18, 0, 1,
388 (outs), (ins calltarget:$func, variable_ops),
389 "bl $func", BrB, []>; // See Pat patterns below.
390 def BLA_Macho : IForm<18, 1, 1,
391 (outs), (ins aaddr:$func, variable_ops),
392 "bla $func", BrB, [(PPCcall_Macho (i32 imm:$func))]>;
393 def BCTRL_Macho : XLForm_2_ext<19, 528, 20, 0, 1,
394 (outs), (ins variable_ops),
400 let isCall = 1, noResults = 1, PPC970_Unit = 7,
401 // All calls clobber the non-callee saved registers...
402 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
403 F0,F1,F2,F3,F4,F5,F6,F7,F8,
404 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
406 CR0,CR1,CR5,CR6,CR7] in {
407 // Convenient aliases for call instructions
408 def BL_ELF : IForm<18, 0, 1,
409 (outs), (ins calltarget:$func, variable_ops),
410 "bl $func", BrB, []>; // See Pat patterns below.
411 def BLA_ELF : IForm<18, 1, 1,
412 (outs), (ins aaddr:$func, variable_ops),
414 [(PPCcall_ELF (i32 imm:$func))]>;
415 def BCTRL_ELF : XLForm_2_ext<19, 528, 20, 0, 1,
416 (outs), (ins variable_ops),
421 // DCB* instructions.
422 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst),
423 "dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
424 PPC970_DGroup_Single;
425 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst),
426 "dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
427 PPC970_DGroup_Single;
428 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst),
429 "dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
430 PPC970_DGroup_Single;
431 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst),
432 "dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
433 PPC970_DGroup_Single;
434 def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst),
435 "dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
436 PPC970_DGroup_Single;
437 def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst),
438 "dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
439 PPC970_DGroup_Single;
440 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst),
441 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
442 PPC970_DGroup_Single;
443 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst),
444 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
445 PPC970_DGroup_Single;
447 //===----------------------------------------------------------------------===//
448 // PPC32 Load Instructions.
451 // Unindexed (r+i) Loads.
452 let isLoad = 1, PPC970_Unit = 2 in {
453 def LBZ : DForm_1<34, (outs GPRC:$rD), (ins memri:$src),
454 "lbz $rD, $src", LdStGeneral,
455 [(set GPRC:$rD, (zextloadi8 iaddr:$src))]>;
456 def LHA : DForm_1<42, (outs GPRC:$rD), (ins memri:$src),
457 "lha $rD, $src", LdStLHA,
458 [(set GPRC:$rD, (sextloadi16 iaddr:$src))]>,
459 PPC970_DGroup_Cracked;
460 def LHZ : DForm_1<40, (outs GPRC:$rD), (ins memri:$src),
461 "lhz $rD, $src", LdStGeneral,
462 [(set GPRC:$rD, (zextloadi16 iaddr:$src))]>;
463 def LWZ : DForm_1<32, (outs GPRC:$rD), (ins memri:$src),
464 "lwz $rD, $src", LdStGeneral,
465 [(set GPRC:$rD, (load iaddr:$src))]>;
467 def LFS : DForm_1<48, (outs F4RC:$rD), (ins memri:$src),
468 "lfs $rD, $src", LdStLFDU,
469 [(set F4RC:$rD, (load iaddr:$src))]>;
470 def LFD : DForm_1<50, (outs F8RC:$rD), (ins memri:$src),
471 "lfd $rD, $src", LdStLFD,
472 [(set F8RC:$rD, (load iaddr:$src))]>;
475 // Unindexed (r+i) Loads with Update (preinc).
476 def LBZU : DForm_1<35, (outs GPRC:$rD), (ins ptr_rc:$ea_result, memri:$addr),
477 "lbzu $rD, $addr", LdStGeneral,
478 []>, RegConstraint<"$addr.reg = $ea_result">,
479 NoEncode<"$ea_result">;
481 def LHAU : DForm_1<43, (outs GPRC:$rD), (ins ptr_rc:$ea_result, memri:$addr),
482 "lhau $rD, $addr", LdStGeneral,
483 []>, RegConstraint<"$addr.reg = $ea_result">,
484 NoEncode<"$ea_result">;
486 def LHZU : DForm_1<41, (outs GPRC:$rD), (ins ptr_rc:$ea_result, memri:$addr),
487 "lhzu $rD, $addr", LdStGeneral,
488 []>, RegConstraint<"$addr.reg = $ea_result">,
489 NoEncode<"$ea_result">;
491 def LWZU : DForm_1<33, (outs GPRC:$rD), (ins ptr_rc:$ea_result, memri:$addr),
492 "lwzu $rD, $addr", LdStGeneral,
493 []>, RegConstraint<"$addr.reg = $ea_result">,
494 NoEncode<"$ea_result">;
496 def LFSU : DForm_1<49, (outs F4RC:$rD), (ins ptr_rc:$ea_result, memri:$addr),
497 "lfs $rD, $addr", LdStLFDU,
498 []>, RegConstraint<"$addr.reg = $ea_result">,
499 NoEncode<"$ea_result">;
501 def LFDU : DForm_1<51, (outs F8RC:$rD), (ins ptr_rc:$ea_result, memri:$addr),
502 "lfd $rD, $addr", LdStLFD,
503 []>, RegConstraint<"$addr.reg = $ea_result">,
504 NoEncode<"$ea_result">;
507 // Indexed (r+r) Loads.
509 let isLoad = 1, PPC970_Unit = 2 in {
510 def LBZX : XForm_1<31, 87, (outs GPRC:$rD), (ins memrr:$src),
511 "lbzx $rD, $src", LdStGeneral,
512 [(set GPRC:$rD, (zextloadi8 xaddr:$src))]>;
513 def LHAX : XForm_1<31, 343, (outs GPRC:$rD), (ins memrr:$src),
514 "lhax $rD, $src", LdStLHA,
515 [(set GPRC:$rD, (sextloadi16 xaddr:$src))]>,
516 PPC970_DGroup_Cracked;
517 def LHZX : XForm_1<31, 279, (outs GPRC:$rD), (ins memrr:$src),
518 "lhzx $rD, $src", LdStGeneral,
519 [(set GPRC:$rD, (zextloadi16 xaddr:$src))]>;
520 def LWZX : XForm_1<31, 23, (outs GPRC:$rD), (ins memrr:$src),
521 "lwzx $rD, $src", LdStGeneral,
522 [(set GPRC:$rD, (load xaddr:$src))]>;
525 def LHBRX : XForm_1<31, 790, (outs GPRC:$rD), (ins memrr:$src),
526 "lhbrx $rD, $src", LdStGeneral,
527 [(set GPRC:$rD, (PPClbrx xoaddr:$src, srcvalue:$sv, i16))]>;
528 def LWBRX : XForm_1<31, 534, (outs GPRC:$rD), (ins memrr:$src),
529 "lwbrx $rD, $src", LdStGeneral,
530 [(set GPRC:$rD, (PPClbrx xoaddr:$src, srcvalue:$sv, i32))]>;
532 def LFSX : XForm_25<31, 535, (outs F4RC:$frD), (ins memrr:$src),
533 "lfsx $frD, $src", LdStLFDU,
534 [(set F4RC:$frD, (load xaddr:$src))]>;
535 def LFDX : XForm_25<31, 599, (outs F8RC:$frD), (ins memrr:$src),
536 "lfdx $frD, $src", LdStLFDU,
537 [(set F8RC:$frD, (load xaddr:$src))]>;
540 //===----------------------------------------------------------------------===//
541 // PPC32 Store Instructions.
544 // Unindexed (r+i) Stores.
545 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
546 def STB : DForm_1<38, (outs), (ins GPRC:$rS, memri:$src),
547 "stb $rS, $src", LdStGeneral,
548 [(truncstorei8 GPRC:$rS, iaddr:$src)]>;
549 def STH : DForm_1<44, (outs), (ins GPRC:$rS, memri:$src),
550 "sth $rS, $src", LdStGeneral,
551 [(truncstorei16 GPRC:$rS, iaddr:$src)]>;
552 def STW : DForm_1<36, (outs), (ins GPRC:$rS, memri:$src),
553 "stw $rS, $src", LdStGeneral,
554 [(store GPRC:$rS, iaddr:$src)]>;
555 def STFS : DForm_1<52, (outs), (ins F4RC:$rS, memri:$dst),
556 "stfs $rS, $dst", LdStUX,
557 [(store F4RC:$rS, iaddr:$dst)]>;
558 def STFD : DForm_1<54, (outs), (ins F8RC:$rS, memri:$dst),
559 "stfd $rS, $dst", LdStUX,
560 [(store F8RC:$rS, iaddr:$dst)]>;
563 // Unindexed (r+i) Stores with Update (preinc).
564 let isStore = 1, PPC970_Unit = 2 in {
565 def STBU : DForm_1<39, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
566 symbolLo:$ptroff, ptr_rc:$ptrreg),
567 "stbu $rS, $ptroff($ptrreg)", LdStGeneral,
568 [(set ptr_rc:$ea_res,
569 (pre_truncsti8 GPRC:$rS, ptr_rc:$ptrreg,
570 iaddroff:$ptroff))]>,
571 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
572 def STHU : DForm_1<45, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
573 symbolLo:$ptroff, ptr_rc:$ptrreg),
574 "sthu $rS, $ptroff($ptrreg)", LdStGeneral,
575 [(set ptr_rc:$ea_res,
576 (pre_truncsti16 GPRC:$rS, ptr_rc:$ptrreg,
577 iaddroff:$ptroff))]>,
578 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
579 def STWU : DForm_1<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
580 symbolLo:$ptroff, ptr_rc:$ptrreg),
581 "stwu $rS, $ptroff($ptrreg)", LdStGeneral,
582 [(set ptr_rc:$ea_res, (pre_store GPRC:$rS, ptr_rc:$ptrreg,
583 iaddroff:$ptroff))]>,
584 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
585 def STFSU : DForm_1<37, (outs ptr_rc:$ea_res), (ins F4RC:$rS,
586 symbolLo:$ptroff, ptr_rc:$ptrreg),
587 "stfsu $rS, $ptroff($ptrreg)", LdStGeneral,
588 [(set ptr_rc:$ea_res, (pre_store F4RC:$rS, ptr_rc:$ptrreg,
589 iaddroff:$ptroff))]>,
590 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
591 def STFDU : DForm_1<37, (outs ptr_rc:$ea_res), (ins F8RC:$rS,
592 symbolLo:$ptroff, ptr_rc:$ptrreg),
593 "stfdu $rS, $ptroff($ptrreg)", LdStGeneral,
594 [(set ptr_rc:$ea_res, (pre_store F8RC:$rS, ptr_rc:$ptrreg,
595 iaddroff:$ptroff))]>,
596 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
600 // Indexed (r+r) Stores.
602 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
603 def STBX : XForm_8<31, 215, (outs), (ins GPRC:$rS, memrr:$dst),
604 "stbx $rS, $dst", LdStGeneral,
605 [(truncstorei8 GPRC:$rS, xaddr:$dst)]>,
606 PPC970_DGroup_Cracked;
607 def STHX : XForm_8<31, 407, (outs), (ins GPRC:$rS, memrr:$dst),
608 "sthx $rS, $dst", LdStGeneral,
609 [(truncstorei16 GPRC:$rS, xaddr:$dst)]>,
610 PPC970_DGroup_Cracked;
611 def STWX : XForm_8<31, 151, (outs), (ins GPRC:$rS, memrr:$dst),
612 "stwx $rS, $dst", LdStGeneral,
613 [(store GPRC:$rS, xaddr:$dst)]>,
614 PPC970_DGroup_Cracked;
615 def STWUX : XForm_8<31, 183, (outs), (ins GPRC:$rS, GPRC:$rA, GPRC:$rB),
616 "stwux $rS, $rA, $rB", LdStGeneral,
618 def STHBRX: XForm_8<31, 918, (outs), (ins GPRC:$rS, memrr:$dst),
619 "sthbrx $rS, $dst", LdStGeneral,
620 [(PPCstbrx GPRC:$rS, xoaddr:$dst, srcvalue:$dummy, i16)]>,
621 PPC970_DGroup_Cracked;
622 def STWBRX: XForm_8<31, 662, (outs), (ins GPRC:$rS, memrr:$dst),
623 "stwbrx $rS, $dst", LdStGeneral,
624 [(PPCstbrx GPRC:$rS, xoaddr:$dst, srcvalue:$dummy, i32)]>,
625 PPC970_DGroup_Cracked;
627 def STFIWX: XForm_28<31, 983, (outs), (ins F8RC:$frS, memrr:$dst),
628 "stfiwx $frS, $dst", LdStUX,
629 [(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>;
630 def STFSX : XForm_28<31, 663, (outs), (ins F4RC:$frS, memrr:$dst),
631 "stfsx $frS, $dst", LdStUX,
632 [(store F4RC:$frS, xaddr:$dst)]>;
633 def STFDX : XForm_28<31, 727, (outs), (ins F8RC:$frS, memrr:$dst),
634 "stfdx $frS, $dst", LdStUX,
635 [(store F8RC:$frS, xaddr:$dst)]>;
639 //===----------------------------------------------------------------------===//
640 // PPC32 Arithmetic Instructions.
643 let PPC970_Unit = 1 in { // FXU Operations.
644 def ADDI : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
645 "addi $rD, $rA, $imm", IntGeneral,
646 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
647 def ADDIC : DForm_2<12, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
648 "addic $rD, $rA, $imm", IntGeneral,
649 [(set GPRC:$rD, (addc GPRC:$rA, immSExt16:$imm))]>,
650 PPC970_DGroup_Cracked;
651 def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
652 "addic. $rD, $rA, $imm", IntGeneral,
654 def ADDIS : DForm_2<15, (outs GPRC:$rD), (ins GPRC:$rA, symbolHi:$imm),
655 "addis $rD, $rA, $imm", IntGeneral,
656 [(set GPRC:$rD, (add GPRC:$rA, imm16ShiftedSExt:$imm))]>;
657 def LA : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, symbolLo:$sym),
658 "la $rD, $sym($rA)", IntGeneral,
659 [(set GPRC:$rD, (add GPRC:$rA,
660 (PPClo tglobaladdr:$sym, 0)))]>;
661 def MULLI : DForm_2< 7, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
662 "mulli $rD, $rA, $imm", IntMulLI,
663 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
664 def SUBFIC : DForm_2< 8, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
665 "subfic $rD, $rA, $imm", IntGeneral,
666 [(set GPRC:$rD, (subc immSExt16:$imm, GPRC:$rA))]>;
667 def LI : DForm_2_r0<14, (outs GPRC:$rD), (ins symbolLo:$imm),
668 "li $rD, $imm", IntGeneral,
669 [(set GPRC:$rD, immSExt16:$imm)]>;
670 def LIS : DForm_2_r0<15, (outs GPRC:$rD), (ins symbolHi:$imm),
671 "lis $rD, $imm", IntGeneral,
672 [(set GPRC:$rD, imm16ShiftedSExt:$imm)]>;
675 let PPC970_Unit = 1 in { // FXU Operations.
676 def ANDIo : DForm_4<28, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
677 "andi. $dst, $src1, $src2", IntGeneral,
678 [(set GPRC:$dst, (and GPRC:$src1, immZExt16:$src2))]>,
680 def ANDISo : DForm_4<29, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
681 "andis. $dst, $src1, $src2", IntGeneral,
682 [(set GPRC:$dst, (and GPRC:$src1,imm16ShiftedZExt:$src2))]>,
684 def ORI : DForm_4<24, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
685 "ori $dst, $src1, $src2", IntGeneral,
686 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
687 def ORIS : DForm_4<25, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
688 "oris $dst, $src1, $src2", IntGeneral,
689 [(set GPRC:$dst, (or GPRC:$src1, imm16ShiftedZExt:$src2))]>;
690 def XORI : DForm_4<26, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
691 "xori $dst, $src1, $src2", IntGeneral,
692 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
693 def XORIS : DForm_4<27, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
694 "xoris $dst, $src1, $src2", IntGeneral,
695 [(set GPRC:$dst, (xor GPRC:$src1,imm16ShiftedZExt:$src2))]>;
696 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IntGeneral,
698 def CMPWI : DForm_5_ext<11, (outs), (ins CRRC:$crD, GPRC:$rA, s16imm:$imm),
699 "cmpwi $crD, $rA, $imm", IntCompare>;
700 def CMPLWI : DForm_6_ext<10, (outs), (ins CRRC:$dst, GPRC:$src1, u16imm:$src2),
701 "cmplwi $dst, $src1, $src2", IntCompare>;
705 let PPC970_Unit = 1 in { // FXU Operations.
706 def NAND : XForm_6<31, 476, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
707 "nand $rA, $rS, $rB", IntGeneral,
708 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
709 def AND : XForm_6<31, 28, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
710 "and $rA, $rS, $rB", IntGeneral,
711 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
712 def ANDC : XForm_6<31, 60, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
713 "andc $rA, $rS, $rB", IntGeneral,
714 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
715 def OR : XForm_6<31, 444, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
716 "or $rA, $rS, $rB", IntGeneral,
717 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
718 def NOR : XForm_6<31, 124, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
719 "nor $rA, $rS, $rB", IntGeneral,
720 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
721 def ORC : XForm_6<31, 412, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
722 "orc $rA, $rS, $rB", IntGeneral,
723 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
724 def EQV : XForm_6<31, 284, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
725 "eqv $rA, $rS, $rB", IntGeneral,
726 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
727 def XOR : XForm_6<31, 316, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
728 "xor $rA, $rS, $rB", IntGeneral,
729 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
730 def SLW : XForm_6<31, 24, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
731 "slw $rA, $rS, $rB", IntGeneral,
732 [(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>;
733 def SRW : XForm_6<31, 536, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
734 "srw $rA, $rS, $rB", IntGeneral,
735 [(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>;
736 def SRAW : XForm_6<31, 792, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
737 "sraw $rA, $rS, $rB", IntShift,
738 [(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>;
741 let PPC970_Unit = 1 in { // FXU Operations.
742 def SRAWI : XForm_10<31, 824, (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH),
743 "srawi $rA, $rS, $SH", IntShift,
744 [(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>;
745 def CNTLZW : XForm_11<31, 26, (outs GPRC:$rA), (ins GPRC:$rS),
746 "cntlzw $rA, $rS", IntGeneral,
747 [(set GPRC:$rA, (ctlz GPRC:$rS))]>;
748 def EXTSB : XForm_11<31, 954, (outs GPRC:$rA), (ins GPRC:$rS),
749 "extsb $rA, $rS", IntGeneral,
750 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
751 def EXTSH : XForm_11<31, 922, (outs GPRC:$rA), (ins GPRC:$rS),
752 "extsh $rA, $rS", IntGeneral,
753 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
755 def CMPW : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
756 "cmpw $crD, $rA, $rB", IntCompare>;
757 def CMPLW : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
758 "cmplw $crD, $rA, $rB", IntCompare>;
760 let PPC970_Unit = 3 in { // FPU Operations.
761 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
762 // "fcmpo $crD, $fA, $fB", FPCompare>;
763 def FCMPUS : XForm_17<63, 0, (outs CRRC:$crD), (ins F4RC:$fA, F4RC:$fB),
764 "fcmpu $crD, $fA, $fB", FPCompare>;
765 def FCMPUD : XForm_17<63, 0, (outs CRRC:$crD), (ins F8RC:$fA, F8RC:$fB),
766 "fcmpu $crD, $fA, $fB", FPCompare>;
768 def FCTIWZ : XForm_26<63, 15, (outs F8RC:$frD), (ins F8RC:$frB),
769 "fctiwz $frD, $frB", FPGeneral,
770 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>;
771 def FRSP : XForm_26<63, 12, (outs F4RC:$frD), (ins F8RC:$frB),
772 "frsp $frD, $frB", FPGeneral,
773 [(set F4RC:$frD, (fround F8RC:$frB))]>;
774 def FSQRT : XForm_26<63, 22, (outs F8RC:$frD), (ins F8RC:$frB),
775 "fsqrt $frD, $frB", FPSqrt,
776 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>;
777 def FSQRTS : XForm_26<59, 22, (outs F4RC:$frD), (ins F4RC:$frB),
778 "fsqrts $frD, $frB", FPSqrt,
779 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>;
782 /// FMR is split into 3 versions, one for 4/8 byte FP, and one for extending.
784 /// Note that these are defined as pseudo-ops on the PPC970 because they are
785 /// often coalesced away and we don't want the dispatch group builder to think
786 /// that they will fill slots (which could cause the load of a LSU reject to
787 /// sneak into a d-group with a store).
788 def FMRS : XForm_26<63, 72, (outs F4RC:$frD), (ins F4RC:$frB),
789 "fmr $frD, $frB", FPGeneral,
790 []>, // (set F4RC:$frD, F4RC:$frB)
792 def FMRD : XForm_26<63, 72, (outs F8RC:$frD), (ins F8RC:$frB),
793 "fmr $frD, $frB", FPGeneral,
794 []>, // (set F8RC:$frD, F8RC:$frB)
796 def FMRSD : XForm_26<63, 72, (outs F8RC:$frD), (ins F4RC:$frB),
797 "fmr $frD, $frB", FPGeneral,
798 [(set F8RC:$frD, (fextend F4RC:$frB))]>,
801 let PPC970_Unit = 3 in { // FPU Operations.
802 // These are artificially split into two different forms, for 4/8 byte FP.
803 def FABSS : XForm_26<63, 264, (outs F4RC:$frD), (ins F4RC:$frB),
804 "fabs $frD, $frB", FPGeneral,
805 [(set F4RC:$frD, (fabs F4RC:$frB))]>;
806 def FABSD : XForm_26<63, 264, (outs F8RC:$frD), (ins F8RC:$frB),
807 "fabs $frD, $frB", FPGeneral,
808 [(set F8RC:$frD, (fabs F8RC:$frB))]>;
809 def FNABSS : XForm_26<63, 136, (outs F4RC:$frD), (ins F4RC:$frB),
810 "fnabs $frD, $frB", FPGeneral,
811 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>;
812 def FNABSD : XForm_26<63, 136, (outs F8RC:$frD), (ins F8RC:$frB),
813 "fnabs $frD, $frB", FPGeneral,
814 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>;
815 def FNEGS : XForm_26<63, 40, (outs F4RC:$frD), (ins F4RC:$frB),
816 "fneg $frD, $frB", FPGeneral,
817 [(set F4RC:$frD, (fneg F4RC:$frB))]>;
818 def FNEGD : XForm_26<63, 40, (outs F8RC:$frD), (ins F8RC:$frB),
819 "fneg $frD, $frB", FPGeneral,
820 [(set F8RC:$frD, (fneg F8RC:$frB))]>;
824 // XL-Form instructions. condition register logical ops.
826 def MCRF : XLForm_3<19, 0, (outs CRRC:$BF), (ins CRRC:$BFA),
827 "mcrf $BF, $BFA", BrMCR>,
828 PPC970_DGroup_First, PPC970_Unit_CRU;
830 def CREQV : XLForm_1<19, 289, (outs CRRC:$CRD), (ins CRRC:$CRA, CRRC:$CRB),
831 "creqv $CRD, $CRA, $CRB", BrCR,
834 def SETCR : XLForm_1_ext<19, 289, (outs CRRC:$dst), (ins),
835 "creqv $dst, $dst, $dst", BrCR,
838 // XFX-Form instructions. Instructions that deal with SPRs.
840 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs GPRC:$rT), (ins),
841 "mfctr $rT", SprMFSPR>,
842 PPC970_DGroup_First, PPC970_Unit_FXU;
843 let Pattern = [(PPCmtctr GPRC:$rS)] in {
844 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins GPRC:$rS),
845 "mtctr $rS", SprMTSPR>,
846 PPC970_DGroup_First, PPC970_Unit_FXU;
849 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins GPRC:$rS),
850 "mtlr $rS", SprMTSPR>,
851 PPC970_DGroup_First, PPC970_Unit_FXU;
852 def MFLR : XFXForm_1_ext<31, 339, 8, (outs GPRC:$rT), (ins),
853 "mflr $rT", SprMFSPR>,
854 PPC970_DGroup_First, PPC970_Unit_FXU;
856 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like
857 // a GPR on the PPC970. As such, copies in and out have the same performance
858 // characteristics as an OR instruction.
859 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins GPRC:$rS),
860 "mtspr 256, $rS", IntGeneral>,
861 PPC970_DGroup_Single, PPC970_Unit_FXU;
862 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs GPRC:$rT), (ins),
863 "mfspr $rT, 256", IntGeneral>,
864 PPC970_DGroup_First, PPC970_Unit_FXU;
866 def MTCRF : XFXForm_5<31, 144, (outs), (ins crbitm:$FXM, GPRC:$rS),
867 "mtcrf $FXM, $rS", BrMCRX>,
868 PPC970_MicroCode, PPC970_Unit_CRU;
869 def MFCR : XFXForm_3<31, 19, (outs GPRC:$rT), (ins), "mfcr $rT", SprMFCR>,
870 PPC970_MicroCode, PPC970_Unit_CRU;
871 def MFOCRF: XFXForm_5a<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM),
872 "mfcr $rT, $FXM", SprMFCR>,
873 PPC970_DGroup_First, PPC970_Unit_CRU;
875 let PPC970_Unit = 1 in { // FXU Operations.
877 // XO-Form instructions. Arithmetic instructions that can set overflow bit
879 def ADD4 : XOForm_1<31, 266, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
880 "add $rT, $rA, $rB", IntGeneral,
881 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
882 def ADDC : XOForm_1<31, 10, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
883 "addc $rT, $rA, $rB", IntGeneral,
884 [(set GPRC:$rT, (addc GPRC:$rA, GPRC:$rB))]>,
885 PPC970_DGroup_Cracked;
886 def ADDE : XOForm_1<31, 138, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
887 "adde $rT, $rA, $rB", IntGeneral,
888 [(set GPRC:$rT, (adde GPRC:$rA, GPRC:$rB))]>;
889 def DIVW : XOForm_1<31, 491, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
890 "divw $rT, $rA, $rB", IntDivW,
891 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>,
892 PPC970_DGroup_First, PPC970_DGroup_Cracked;
893 def DIVWU : XOForm_1<31, 459, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
894 "divwu $rT, $rA, $rB", IntDivW,
895 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>,
896 PPC970_DGroup_First, PPC970_DGroup_Cracked;
897 def MULHW : XOForm_1<31, 75, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
898 "mulhw $rT, $rA, $rB", IntMulHW,
899 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
900 def MULHWU : XOForm_1<31, 11, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
901 "mulhwu $rT, $rA, $rB", IntMulHWU,
902 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
903 def MULLW : XOForm_1<31, 235, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
904 "mullw $rT, $rA, $rB", IntMulHW,
905 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
906 def SUBF : XOForm_1<31, 40, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
907 "subf $rT, $rA, $rB", IntGeneral,
908 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
909 def SUBFC : XOForm_1<31, 8, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
910 "subfc $rT, $rA, $rB", IntGeneral,
911 [(set GPRC:$rT, (subc GPRC:$rB, GPRC:$rA))]>,
912 PPC970_DGroup_Cracked;
913 def SUBFE : XOForm_1<31, 136, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
914 "subfe $rT, $rA, $rB", IntGeneral,
915 [(set GPRC:$rT, (sube GPRC:$rB, GPRC:$rA))]>;
916 def ADDME : XOForm_3<31, 234, 0, (outs GPRC:$rT), (ins GPRC:$rA),
917 "addme $rT, $rA", IntGeneral,
918 [(set GPRC:$rT, (adde GPRC:$rA, immAllOnes))]>;
919 def ADDZE : XOForm_3<31, 202, 0, (outs GPRC:$rT), (ins GPRC:$rA),
920 "addze $rT, $rA", IntGeneral,
921 [(set GPRC:$rT, (adde GPRC:$rA, 0))]>;
922 def NEG : XOForm_3<31, 104, 0, (outs GPRC:$rT), (ins GPRC:$rA),
923 "neg $rT, $rA", IntGeneral,
924 [(set GPRC:$rT, (ineg GPRC:$rA))]>;
925 def SUBFME : XOForm_3<31, 232, 0, (outs GPRC:$rT), (ins GPRC:$rA),
926 "subfme $rT, $rA", IntGeneral,
927 [(set GPRC:$rT, (sube immAllOnes, GPRC:$rA))]>;
928 def SUBFZE : XOForm_3<31, 200, 0, (outs GPRC:$rT), (ins GPRC:$rA),
929 "subfze $rT, $rA", IntGeneral,
930 [(set GPRC:$rT, (sube 0, GPRC:$rA))]>;
933 // A-Form instructions. Most of the instructions executed in the FPU are of
936 let PPC970_Unit = 3 in { // FPU Operations.
937 def FMADD : AForm_1<63, 29,
938 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
939 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused,
940 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC),
942 Requires<[FPContractions]>;
943 def FMADDS : AForm_1<59, 29,
944 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
945 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
946 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
948 Requires<[FPContractions]>;
949 def FMSUB : AForm_1<63, 28,
950 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
951 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused,
952 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC),
954 Requires<[FPContractions]>;
955 def FMSUBS : AForm_1<59, 28,
956 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
957 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
958 [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC),
960 Requires<[FPContractions]>;
961 def FNMADD : AForm_1<63, 31,
962 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
963 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused,
964 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC),
966 Requires<[FPContractions]>;
967 def FNMADDS : AForm_1<59, 31,
968 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
969 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
970 [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC),
972 Requires<[FPContractions]>;
973 def FNMSUB : AForm_1<63, 30,
974 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
975 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused,
976 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC),
978 Requires<[FPContractions]>;
979 def FNMSUBS : AForm_1<59, 30,
980 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
981 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
982 [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC),
984 Requires<[FPContractions]>;
985 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
986 // having 4 of these, force the comparison to always be an 8-byte double (code
987 // should use an FMRSD if the input comparison value really wants to be a float)
988 // and 4/8 byte forms for the result and operand type..
989 def FSELD : AForm_1<63, 23,
990 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
991 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
992 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>;
993 def FSELS : AForm_1<63, 23,
994 (outs F4RC:$FRT), (ins F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
995 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
996 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>;
997 def FADD : AForm_2<63, 21,
998 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
999 "fadd $FRT, $FRA, $FRB", FPGeneral,
1000 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>;
1001 def FADDS : AForm_2<59, 21,
1002 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1003 "fadds $FRT, $FRA, $FRB", FPGeneral,
1004 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>;
1005 def FDIV : AForm_2<63, 18,
1006 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1007 "fdiv $FRT, $FRA, $FRB", FPDivD,
1008 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>;
1009 def FDIVS : AForm_2<59, 18,
1010 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1011 "fdivs $FRT, $FRA, $FRB", FPDivS,
1012 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>;
1013 def FMUL : AForm_3<63, 25,
1014 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1015 "fmul $FRT, $FRA, $FRB", FPFused,
1016 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>;
1017 def FMULS : AForm_3<59, 25,
1018 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1019 "fmuls $FRT, $FRA, $FRB", FPGeneral,
1020 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>;
1021 def FSUB : AForm_2<63, 20,
1022 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1023 "fsub $FRT, $FRA, $FRB", FPGeneral,
1024 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>;
1025 def FSUBS : AForm_2<59, 20,
1026 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1027 "fsubs $FRT, $FRA, $FRB", FPGeneral,
1028 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>;
1031 let PPC970_Unit = 1 in { // FXU Operations.
1032 // M-Form instructions. rotate and mask instructions.
1034 let isCommutable = 1 in {
1035 // RLWIMI can be commuted if the rotate amount is zero.
1036 def RLWIMI : MForm_2<20,
1037 (outs GPRC:$rA), (ins GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
1038 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate,
1039 []>, PPC970_DGroup_Cracked, RegConstraint<"$rSi = $rA">,
1042 def RLWINM : MForm_2<21,
1043 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1044 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
1046 def RLWINMo : MForm_2<21,
1047 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1048 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
1049 []>, isDOT, PPC970_DGroup_Cracked;
1050 def RLWNM : MForm_2<23,
1051 (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
1052 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral,
1057 //===----------------------------------------------------------------------===//
1058 // DWARF Pseudo Instructions
1061 def DWARF_LOC : Pseudo<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file),
1062 "${:comment} .loc $file, $line, $col",
1063 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
1066 //===----------------------------------------------------------------------===//
1067 // PowerPC Instruction Patterns
1070 // Arbitrary immediate support. Implement in terms of LIS/ORI.
1071 def : Pat<(i32 imm:$imm),
1072 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
1074 // Implement the 'not' operation with the NOR instruction.
1075 def NOT : Pat<(not GPRC:$in),
1076 (NOR GPRC:$in, GPRC:$in)>;
1078 // ADD an arbitrary immediate.
1079 def : Pat<(add GPRC:$in, imm:$imm),
1080 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
1081 // OR an arbitrary immediate.
1082 def : Pat<(or GPRC:$in, imm:$imm),
1083 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1084 // XOR an arbitrary immediate.
1085 def : Pat<(xor GPRC:$in, imm:$imm),
1086 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1088 def : Pat<(sub immSExt16:$imm, GPRC:$in),
1089 (SUBFIC GPRC:$in, imm:$imm)>;
1092 def : Pat<(shl GPRC:$in, (i32 imm:$imm)),
1093 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>;
1094 def : Pat<(srl GPRC:$in, (i32 imm:$imm)),
1095 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>;
1098 def : Pat<(rotl GPRC:$in, GPRC:$sh),
1099 (RLWNM GPRC:$in, GPRC:$sh, 0, 31)>;
1100 def : Pat<(rotl GPRC:$in, (i32 imm:$imm)),
1101 (RLWINM GPRC:$in, imm:$imm, 0, 31)>;
1104 def : Pat<(and (rotl GPRC:$in, GPRC:$sh), maskimm32:$imm),
1105 (RLWNM GPRC:$in, GPRC:$sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
1108 def : Pat<(PPCcall_Macho (i32 tglobaladdr:$dst)),
1109 (BL_Macho tglobaladdr:$dst)>;
1110 def : Pat<(PPCcall_Macho (i32 texternalsym:$dst)),
1111 (BL_Macho texternalsym:$dst)>;
1112 def : Pat<(PPCcall_ELF (i32 tglobaladdr:$dst)),
1113 (BL_ELF tglobaladdr:$dst)>;
1114 def : Pat<(PPCcall_ELF (i32 texternalsym:$dst)),
1115 (BL_ELF texternalsym:$dst)>;
1117 // Hi and Lo for Darwin Global Addresses.
1118 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
1119 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
1120 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
1121 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
1122 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
1123 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
1124 def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)),
1125 (ADDIS GPRC:$in, tglobaladdr:$g)>;
1126 def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)),
1127 (ADDIS GPRC:$in, tconstpool:$g)>;
1128 def : Pat<(add GPRC:$in, (PPChi tjumptable:$g, 0)),
1129 (ADDIS GPRC:$in, tjumptable:$g)>;
1131 // Fused negative multiply subtract, alternate pattern
1132 def : Pat<(fsub F8RC:$B, (fmul F8RC:$A, F8RC:$C)),
1133 (FNMSUB F8RC:$A, F8RC:$C, F8RC:$B)>,
1134 Requires<[FPContractions]>;
1135 def : Pat<(fsub F4RC:$B, (fmul F4RC:$A, F4RC:$C)),
1136 (FNMSUBS F4RC:$A, F4RC:$C, F4RC:$B)>,
1137 Requires<[FPContractions]>;
1139 // Standard shifts. These are represented separately from the real shifts above
1140 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
1142 def : Pat<(sra GPRC:$rS, GPRC:$rB),
1143 (SRAW GPRC:$rS, GPRC:$rB)>;
1144 def : Pat<(srl GPRC:$rS, GPRC:$rB),
1145 (SRW GPRC:$rS, GPRC:$rB)>;
1146 def : Pat<(shl GPRC:$rS, GPRC:$rB),
1147 (SLW GPRC:$rS, GPRC:$rB)>;
1149 def : Pat<(zextloadi1 iaddr:$src),
1151 def : Pat<(zextloadi1 xaddr:$src),
1153 def : Pat<(extloadi1 iaddr:$src),
1155 def : Pat<(extloadi1 xaddr:$src),
1157 def : Pat<(extloadi8 iaddr:$src),
1159 def : Pat<(extloadi8 xaddr:$src),
1161 def : Pat<(extloadi16 iaddr:$src),
1163 def : Pat<(extloadi16 xaddr:$src),
1165 def : Pat<(extloadf32 iaddr:$src),
1166 (FMRSD (LFS iaddr:$src))>;
1167 def : Pat<(extloadf32 xaddr:$src),
1168 (FMRSD (LFSX xaddr:$src))>;
1170 include "PPCInstrAltivec.td"
1171 include "PPCInstr64Bit.td"