1 //===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPCShiftOp : SDTypeProfile<1, 2, [ // PPCshl, PPCsra, PPCsrl
24 SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32>
26 def SDT_PPCCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
28 def SDT_PPCvperm : SDTypeProfile<1, 3, [
29 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
32 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
33 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
36 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
37 SDTCisVT<1, i32>, SDTCisVT<2, OtherVT>
40 //===----------------------------------------------------------------------===//
41 // PowerPC specific DAG Nodes.
44 def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>;
45 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
46 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
47 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx, [SDNPHasChain]>;
49 def PPCfsel : SDNode<"PPCISD::FSEL",
50 // Type constraint for fsel.
51 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
52 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
54 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
55 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
56 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
57 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
59 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
61 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
62 // amounts. These nodes are generated by the multi-precision shift code.
63 def PPCsrl : SDNode<"PPCISD::SRL" , SDT_PPCShiftOp>;
64 def PPCsra : SDNode<"PPCISD::SRA" , SDT_PPCShiftOp>;
65 def PPCshl : SDNode<"PPCISD::SHL" , SDT_PPCShiftOp>;
67 def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>;
68 def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore, [SDNPHasChain]>;
70 // These are target-independent nodes, but have target-specific formats.
71 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeq,[SDNPHasChain]>;
72 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeq,[SDNPHasChain]>;
74 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>;
75 def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall,
76 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
77 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
78 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
79 def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTRet,
80 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
82 def retflag : SDNode<"PPCISD::RET_FLAG", SDTRet,
83 [SDNPHasChain, SDNPOptInFlag]>;
85 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
86 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutFlag]>;
88 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
89 [SDNPHasChain, SDNPOptInFlag]>;
91 //===----------------------------------------------------------------------===//
92 // PowerPC specific transformation functions and pattern fragments.
95 def SHL32 : SDNodeXForm<imm, [{
96 // Transformation function: 31 - imm
97 return getI32Imm(31 - N->getValue());
100 def SHL64 : SDNodeXForm<imm, [{
101 // Transformation function: 63 - imm
102 return getI32Imm(63 - N->getValue());
105 def SRL32 : SDNodeXForm<imm, [{
106 // Transformation function: 32 - imm
107 return N->getValue() ? getI32Imm(32 - N->getValue()) : getI32Imm(0);
110 def SRL64 : SDNodeXForm<imm, [{
111 // Transformation function: 64 - imm
112 return N->getValue() ? getI32Imm(64 - N->getValue()) : getI32Imm(0);
115 def LO16 : SDNodeXForm<imm, [{
116 // Transformation function: get the low 16 bits.
117 return getI32Imm((unsigned short)N->getValue());
120 def HI16 : SDNodeXForm<imm, [{
121 // Transformation function: shift the immediate value down into the low bits.
122 return getI32Imm((unsigned)N->getValue() >> 16);
125 def HA16 : SDNodeXForm<imm, [{
126 // Transformation function: shift the immediate value down into the low bits.
127 signed int Val = N->getValue();
128 return getI32Imm((Val - (signed short)Val) >> 16);
132 def immSExt16 : PatLeaf<(imm), [{
133 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
134 // field. Used by instructions like 'addi'.
135 return (int)N->getValue() == (short)N->getValue();
137 def immZExt16 : PatLeaf<(imm), [{
138 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
139 // field. Used by instructions like 'ori'.
140 return (unsigned)N->getValue() == (unsigned short)N->getValue();
143 def imm16Shifted : PatLeaf<(imm), [{
144 // imm16Shifted predicate - True if only bits in the top 16-bits of the
145 // immediate are set. Used by instructions like 'addis'.
146 if (N->getValue() & 0xFFFF) return false;
147 if (N->getValueType(0) == MVT::i32)
149 // For 64-bit, make sure it is sext right.
150 return N->getValue() == (uint64_t)(int)N->getValue();
154 //===----------------------------------------------------------------------===//
155 // PowerPC Flag Definitions.
157 class isPPC64 { bit PPC64 = 1; }
158 class isVMX { bit VMX = 1; }
160 list<Register> Defs = [CR0];
166 //===----------------------------------------------------------------------===//
167 // PowerPC Operand Definitions.
169 def s5imm : Operand<i32> {
170 let PrintMethod = "printS5ImmOperand";
172 def u5imm : Operand<i32> {
173 let PrintMethod = "printU5ImmOperand";
175 def u6imm : Operand<i32> {
176 let PrintMethod = "printU6ImmOperand";
178 def s16imm : Operand<i32> {
179 let PrintMethod = "printS16ImmOperand";
181 def u16imm : Operand<i32> {
182 let PrintMethod = "printU16ImmOperand";
184 def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing.
185 let PrintMethod = "printS16X4ImmOperand";
187 def target : Operand<OtherVT> {
188 let PrintMethod = "printBranchOperand";
190 def calltarget : Operand<iPTR> {
191 let PrintMethod = "printCallOperand";
193 def aaddr : Operand<iPTR> {
194 let PrintMethod = "printAbsAddrOperand";
196 def piclabel: Operand<iPTR> {
197 let PrintMethod = "printPICLabel";
199 def symbolHi: Operand<i32> {
200 let PrintMethod = "printSymbolHi";
202 def symbolLo: Operand<i32> {
203 let PrintMethod = "printSymbolLo";
205 def crbitm: Operand<i8> {
206 let PrintMethod = "printcrbitm";
209 def memri : Operand<iPTR> {
210 let PrintMethod = "printMemRegImm";
211 let NumMIOperands = 2;
212 let MIOperandInfo = (ops i32imm, ptr_rc);
214 def memrr : Operand<iPTR> {
215 let PrintMethod = "printMemRegReg";
216 let NumMIOperands = 2;
217 let MIOperandInfo = (ops ptr_rc, ptr_rc);
219 def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits.
220 let PrintMethod = "printMemRegImmShifted";
221 let NumMIOperands = 2;
222 let MIOperandInfo = (ops i32imm, ptr_rc);
225 // Define PowerPC specific addressing mode.
226 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", []>;
227 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", []>;
228 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[]>;
229 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", []>; // "std"
231 //===----------------------------------------------------------------------===//
232 // PowerPC Instruction Predicate Definitions.
233 def FPContractions : Predicate<"!NoExcessFPPrecision">;
235 //===----------------------------------------------------------------------===//
236 // PowerPC Instruction Definitions.
238 // Pseudo-instructions:
240 let hasCtrlDep = 1 in {
241 def ADJCALLSTACKDOWN : Pseudo<(ops u16imm:$amt),
242 "; ADJCALLSTACKDOWN",
243 [(callseq_start imm:$amt)]>;
244 def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt),
246 [(callseq_end imm:$amt)]>;
248 def UPDATE_VRSAVE : Pseudo<(ops GPRC:$rD, GPRC:$rS),
249 "UPDATE_VRSAVE $rD, $rS", []>;
251 def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC",
252 [(set GPRC:$rD, (undef))]>;
253 def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "; $rD = IMPLICIT_DEF_F8",
254 [(set F8RC:$rD, (undef))]>;
255 def IMPLICIT_DEF_F4 : Pseudo<(ops F4RC:$rD), "; $rD = IMPLICIT_DEF_F4",
256 [(set F4RC:$rD, (undef))]>;
258 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
259 // scheduler into a branch sequence.
260 let usesCustomDAGSchedInserter = 1, // Expanded by the scheduler.
261 PPC970_Single = 1 in {
262 def SELECT_CC_Int : Pseudo<(ops GPRC:$dst, CRRC:$cond, GPRC:$T, GPRC:$F,
263 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
264 def SELECT_CC_F4 : Pseudo<(ops F4RC:$dst, CRRC:$cond, F4RC:$T, F4RC:$F,
265 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
266 def SELECT_CC_F8 : Pseudo<(ops F8RC:$dst, CRRC:$cond, F8RC:$T, F8RC:$F,
267 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
268 def SELECT_CC_VRRC: Pseudo<(ops VRRC:$dst, CRRC:$cond, VRRC:$T, VRRC:$F,
269 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
272 let isTerminator = 1, noResults = 1, PPC970_Unit = 7 in {
274 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr", BrB, [(retflag)]>;
275 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr", BrB, []>;
279 def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label", []>,
282 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1,
283 noResults = 1, PPC970_Unit = 7 in {
284 def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm:$opc, target:$dst),
285 "; COND_BRANCH $crS, $opc, $dst",
286 [(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]>;
287 def B : IForm<18, 0, 0, (ops target:$dst),
291 def BLT : BForm<16, 0, 0, 12, 0, (ops CRRC:$crS, target:$block),
292 "blt $crS, $block", BrB>;
293 def BLE : BForm<16, 0, 0, 4, 1, (ops CRRC:$crS, target:$block),
294 "ble $crS, $block", BrB>;
295 def BEQ : BForm<16, 0, 0, 12, 2, (ops CRRC:$crS, target:$block),
296 "beq $crS, $block", BrB>;
297 def BGE : BForm<16, 0, 0, 4, 0, (ops CRRC:$crS, target:$block),
298 "bge $crS, $block", BrB>;
299 def BGT : BForm<16, 0, 0, 12, 1, (ops CRRC:$crS, target:$block),
300 "bgt $crS, $block", BrB>;
301 def BNE : BForm<16, 0, 0, 4, 2, (ops CRRC:$crS, target:$block),
302 "bne $crS, $block", BrB>;
303 def BUN : BForm<16, 0, 0, 12, 3, (ops CRRC:$crS, target:$block),
304 "bun $crS, $block", BrB>;
305 def BNU : BForm<16, 0, 0, 4, 3, (ops CRRC:$crS, target:$block),
306 "bnu $crS, $block", BrB>;
309 let isCall = 1, noResults = 1, PPC970_Unit = 7,
310 // All calls clobber the non-callee saved registers...
311 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
312 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
313 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
315 CR0,CR1,CR5,CR6,CR7] in {
316 // Convenient aliases for call instructions
317 def BL : IForm<18, 0, 1, (ops calltarget:$func, variable_ops),
318 "bl $func", BrB, []>; // See Pat patterns below.
319 def BLA : IForm<18, 1, 1, (ops aaddr:$func, variable_ops),
320 "bla $func", BrB, [(PPCcall imm:$func)]>;
321 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (ops variable_ops), "bctrl", BrB,
325 // DCB* instructions.
326 def DCBZ : DCB_Form<1014, 0, (ops memrr:$dst),
327 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
328 PPC970_DGroup_Single;
329 def DCBZL : DCB_Form<1014, 1, (ops memrr:$dst),
330 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
331 PPC970_DGroup_Single;
333 // D-Form instructions. Most instructions that perform an operation on a
334 // register and an immediate are of this type.
336 let isLoad = 1, PPC970_Unit = 2 in {
337 def LBZ : DForm_1<34, (ops GPRC:$rD, memri:$src),
338 "lbz $rD, $src", LdStGeneral,
339 [(set GPRC:$rD, (zextload iaddr:$src, i8))]>;
340 def LHA : DForm_1<42, (ops GPRC:$rD, memri:$src),
341 "lha $rD, $src", LdStLHA,
342 [(set GPRC:$rD, (sextload iaddr:$src, i16))]>,
343 PPC970_DGroup_Cracked;
344 def LHZ : DForm_1<40, (ops GPRC:$rD, memri:$src),
345 "lhz $rD, $src", LdStGeneral,
346 [(set GPRC:$rD, (zextload iaddr:$src, i16))]>;
347 def LWZ : DForm_1<32, (ops GPRC:$rD, memri:$src),
348 "lwz $rD, $src", LdStGeneral,
349 [(set GPRC:$rD, (load iaddr:$src))]>;
350 def LWZU : DForm_1<35, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
351 "lwzu $rD, $disp($rA)", LdStGeneral,
354 let PPC970_Unit = 1 in { // FXU Operations.
355 def ADDI : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
356 "addi $rD, $rA, $imm", IntGeneral,
357 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
358 def ADDIC : DForm_2<12, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
359 "addic $rD, $rA, $imm", IntGeneral,
360 [(set GPRC:$rD, (addc GPRC:$rA, immSExt16:$imm))]>,
361 PPC970_DGroup_Cracked;
362 def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
363 "addic. $rD, $rA, $imm", IntGeneral,
365 def ADDIS : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$imm),
366 "addis $rD, $rA, $imm", IntGeneral,
367 [(set GPRC:$rD, (add GPRC:$rA, imm16Shifted:$imm))]>;
368 def LA : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym),
369 "la $rD, $sym($rA)", IntGeneral,
370 [(set GPRC:$rD, (add GPRC:$rA,
371 (PPClo tglobaladdr:$sym, 0)))]>;
372 def MULLI : DForm_2< 7, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
373 "mulli $rD, $rA, $imm", IntMulLI,
374 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
375 def SUBFIC : DForm_2< 8, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
376 "subfic $rD, $rA, $imm", IntGeneral,
377 [(set GPRC:$rD, (subc immSExt16:$imm, GPRC:$rA))]>;
378 def LI : DForm_2_r0<14, (ops GPRC:$rD, symbolLo:$imm),
379 "li $rD, $imm", IntGeneral,
380 [(set GPRC:$rD, immSExt16:$imm)]>;
381 def LIS : DForm_2_r0<15, (ops GPRC:$rD, symbolHi:$imm),
382 "lis $rD, $imm", IntGeneral,
383 [(set GPRC:$rD, imm16Shifted:$imm)]>;
385 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
386 def STB : DForm_3<38, (ops GPRC:$rS, memri:$src),
387 "stb $rS, $src", LdStGeneral,
388 [(truncstore GPRC:$rS, iaddr:$src, i8)]>;
389 def STH : DForm_3<44, (ops GPRC:$rS, memri:$src),
390 "sth $rS, $src", LdStGeneral,
391 [(truncstore GPRC:$rS, iaddr:$src, i16)]>;
392 def STW : DForm_3<36, (ops GPRC:$rS, memri:$src),
393 "stw $rS, $src", LdStGeneral,
394 [(store GPRC:$rS, iaddr:$src)]>;
395 def STWU : DForm_3<37, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
396 "stwu $rS, $disp($rA)", LdStGeneral,
399 let PPC970_Unit = 1 in { // FXU Operations.
400 def ANDIo : DForm_4<28, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
401 "andi. $dst, $src1, $src2", IntGeneral,
402 [(set GPRC:$dst, (and GPRC:$src1, immZExt16:$src2))]>,
404 def ANDISo : DForm_4<29, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
405 "andis. $dst, $src1, $src2", IntGeneral,
406 [(set GPRC:$dst, (and GPRC:$src1, imm16Shifted:$src2))]>,
408 def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
409 "ori $dst, $src1, $src2", IntGeneral,
410 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
411 def ORIS : DForm_4<25, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
412 "oris $dst, $src1, $src2", IntGeneral,
413 [(set GPRC:$dst, (or GPRC:$src1, imm16Shifted:$src2))]>;
414 def XORI : DForm_4<26, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
415 "xori $dst, $src1, $src2", IntGeneral,
416 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
417 def XORIS : DForm_4<27, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
418 "xoris $dst, $src1, $src2", IntGeneral,
419 [(set GPRC:$dst, (xor GPRC:$src1, imm16Shifted:$src2))]>;
420 def NOP : DForm_4_zero<24, (ops), "nop", IntGeneral,
422 def CMPI : DForm_5<11, (ops CRRC:$crD, i1imm:$L, GPRC:$rA, s16imm:$imm),
423 "cmpi $crD, $L, $rA, $imm", IntCompare>;
424 def CMPWI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
425 "cmpwi $crD, $rA, $imm", IntCompare>;
426 def CMPLI : DForm_6<10, (ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2),
427 "cmpli $dst, $size, $src1, $src2", IntCompare>;
428 def CMPLWI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
429 "cmplwi $dst, $src1, $src2", IntCompare>;
431 let isLoad = 1, PPC970_Unit = 2 in {
432 def LFS : DForm_8<48, (ops F4RC:$rD, memri:$src),
433 "lfs $rD, $src", LdStLFDU,
434 [(set F4RC:$rD, (load iaddr:$src))]>;
435 def LFD : DForm_8<50, (ops F8RC:$rD, memri:$src),
436 "lfd $rD, $src", LdStLFD,
437 [(set F8RC:$rD, (load iaddr:$src))]>;
439 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
440 def STFS : DForm_9<52, (ops F4RC:$rS, memri:$dst),
441 "stfs $rS, $dst", LdStUX,
442 [(store F4RC:$rS, iaddr:$dst)]>;
443 def STFD : DForm_9<54, (ops F8RC:$rS, memri:$dst),
444 "stfd $rS, $dst", LdStUX,
445 [(store F8RC:$rS, iaddr:$dst)]>;
448 // X-Form instructions. Most instructions that perform an operation on a
449 // register and another register are of this type.
451 let isLoad = 1, PPC970_Unit = 2 in {
452 def LBZX : XForm_1<31, 87, (ops GPRC:$rD, memrr:$src),
453 "lbzx $rD, $src", LdStGeneral,
454 [(set GPRC:$rD, (zextload xaddr:$src, i8))]>;
455 def LHAX : XForm_1<31, 343, (ops GPRC:$rD, memrr:$src),
456 "lhax $rD, $src", LdStLHA,
457 [(set GPRC:$rD, (sextload xaddr:$src, i16))]>,
458 PPC970_DGroup_Cracked;
459 def LHZX : XForm_1<31, 279, (ops GPRC:$rD, memrr:$src),
460 "lhzx $rD, $src", LdStGeneral,
461 [(set GPRC:$rD, (zextload xaddr:$src, i16))]>;
462 def LWZX : XForm_1<31, 23, (ops GPRC:$rD, memrr:$src),
463 "lwzx $rD, $src", LdStGeneral,
464 [(set GPRC:$rD, (load xaddr:$src))]>;
467 let PPC970_Unit = 1 in { // FXU Operations.
468 def NAND : XForm_6<31, 476, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
469 "nand $rA, $rS, $rB", IntGeneral,
470 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
471 def AND : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
472 "and $rA, $rS, $rB", IntGeneral,
473 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
474 def ANDo : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
475 "and. $rA, $rS, $rB", IntGeneral,
477 def ANDC : XForm_6<31, 60, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
478 "andc $rA, $rS, $rB", IntGeneral,
479 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
480 def OR4 : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
481 "or $rA, $rS, $rB", IntGeneral,
482 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
483 def NOR : XForm_6<31, 124, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
484 "nor $rA, $rS, $rB", IntGeneral,
485 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
486 def ORo : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
487 "or. $rA, $rS, $rB", IntGeneral,
489 def ORC : XForm_6<31, 412, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
490 "orc $rA, $rS, $rB", IntGeneral,
491 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
492 def EQV : XForm_6<31, 284, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
493 "eqv $rA, $rS, $rB", IntGeneral,
494 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
495 def XOR : XForm_6<31, 316, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
496 "xor $rA, $rS, $rB", IntGeneral,
497 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
498 def SLW : XForm_6<31, 24, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
499 "slw $rA, $rS, $rB", IntGeneral,
500 [(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>;
501 def SRW : XForm_6<31, 536, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
502 "srw $rA, $rS, $rB", IntGeneral,
503 [(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>;
504 def SRAW : XForm_6<31, 792, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
505 "sraw $rA, $rS, $rB", IntShift,
506 [(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>;
508 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
509 def STBX : XForm_8<31, 215, (ops GPRC:$rS, memrr:$dst),
510 "stbx $rS, $dst", LdStGeneral,
511 [(truncstore GPRC:$rS, xaddr:$dst, i8)]>,
512 PPC970_DGroup_Cracked;
513 def STHX : XForm_8<31, 407, (ops GPRC:$rS, memrr:$dst),
514 "sthx $rS, $dst", LdStGeneral,
515 [(truncstore GPRC:$rS, xaddr:$dst, i16)]>,
516 PPC970_DGroup_Cracked;
517 def STWX : XForm_8<31, 151, (ops GPRC:$rS, memrr:$dst),
518 "stwx $rS, $dst", LdStGeneral,
519 [(store GPRC:$rS, xaddr:$dst)]>,
520 PPC970_DGroup_Cracked;
521 def STWUX : XForm_8<31, 183, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
522 "stwux $rS, $rA, $rB", LdStGeneral,
525 let PPC970_Unit = 1 in { // FXU Operations.
526 def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
527 "srawi $rA, $rS, $SH", IntShift,
528 [(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>;
529 def CNTLZW : XForm_11<31, 26, (ops GPRC:$rA, GPRC:$rS),
530 "cntlzw $rA, $rS", IntGeneral,
531 [(set GPRC:$rA, (ctlz GPRC:$rS))]>;
532 def EXTSB : XForm_11<31, 954, (ops GPRC:$rA, GPRC:$rS),
533 "extsb $rA, $rS", IntGeneral,
534 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
535 def EXTSH : XForm_11<31, 922, (ops GPRC:$rA, GPRC:$rS),
536 "extsh $rA, $rS", IntGeneral,
537 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
539 def CMP : XForm_16<31, 0, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
540 "cmp $crD, $long, $rA, $rB", IntCompare>;
541 def CMPL : XForm_16<31, 32, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
542 "cmpl $crD, $long, $rA, $rB", IntCompare>;
543 def CMPW : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
544 "cmpw $crD, $rA, $rB", IntCompare>;
545 def CMPLW : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
546 "cmplw $crD, $rA, $rB", IntCompare>;
548 let PPC970_Unit = 3 in { // FPU Operations.
549 //def FCMPO : XForm_17<63, 32, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
550 // "fcmpo $crD, $fA, $fB", FPCompare>;
551 def FCMPUS : XForm_17<63, 0, (ops CRRC:$crD, F4RC:$fA, F4RC:$fB),
552 "fcmpu $crD, $fA, $fB", FPCompare>;
553 def FCMPUD : XForm_17<63, 0, (ops CRRC:$crD, F8RC:$fA, F8RC:$fB),
554 "fcmpu $crD, $fA, $fB", FPCompare>;
556 let isLoad = 1, PPC970_Unit = 2 in {
557 def LFSX : XForm_25<31, 535, (ops F4RC:$frD, memrr:$src),
558 "lfsx $frD, $src", LdStLFDU,
559 [(set F4RC:$frD, (load xaddr:$src))]>;
560 def LFDX : XForm_25<31, 599, (ops F8RC:$frD, memrr:$src),
561 "lfdx $frD, $src", LdStLFDU,
562 [(set F8RC:$frD, (load xaddr:$src))]>;
564 let PPC970_Unit = 3 in { // FPU Operations.
565 def FCTIWZ : XForm_26<63, 15, (ops F8RC:$frD, F8RC:$frB),
566 "fctiwz $frD, $frB", FPGeneral,
567 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>;
568 def FRSP : XForm_26<63, 12, (ops F4RC:$frD, F8RC:$frB),
569 "frsp $frD, $frB", FPGeneral,
570 [(set F4RC:$frD, (fround F8RC:$frB))]>;
571 def FSQRT : XForm_26<63, 22, (ops F8RC:$frD, F8RC:$frB),
572 "fsqrt $frD, $frB", FPSqrt,
573 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>;
574 def FSQRTS : XForm_26<59, 22, (ops F4RC:$frD, F4RC:$frB),
575 "fsqrts $frD, $frB", FPSqrt,
576 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>;
579 /// FMR is split into 3 versions, one for 4/8 byte FP, and one for extending.
581 /// Note that these are defined as pseudo-ops on the PPC970 because they are
582 /// often coalesced away and we don't want the dispatch group builder to think
583 /// that they will fill slots (which could cause the load of a LSU reject to
584 /// sneak into a d-group with a store).
585 def FMRS : XForm_26<63, 72, (ops F4RC:$frD, F4RC:$frB),
586 "fmr $frD, $frB", FPGeneral,
587 []>, // (set F4RC:$frD, F4RC:$frB)
589 def FMRD : XForm_26<63, 72, (ops F8RC:$frD, F8RC:$frB),
590 "fmr $frD, $frB", FPGeneral,
591 []>, // (set F8RC:$frD, F8RC:$frB)
593 def FMRSD : XForm_26<63, 72, (ops F8RC:$frD, F4RC:$frB),
594 "fmr $frD, $frB", FPGeneral,
595 [(set F8RC:$frD, (fextend F4RC:$frB))]>,
598 let PPC970_Unit = 3 in { // FPU Operations.
599 // These are artificially split into two different forms, for 4/8 byte FP.
600 def FABSS : XForm_26<63, 264, (ops F4RC:$frD, F4RC:$frB),
601 "fabs $frD, $frB", FPGeneral,
602 [(set F4RC:$frD, (fabs F4RC:$frB))]>;
603 def FABSD : XForm_26<63, 264, (ops F8RC:$frD, F8RC:$frB),
604 "fabs $frD, $frB", FPGeneral,
605 [(set F8RC:$frD, (fabs F8RC:$frB))]>;
606 def FNABSS : XForm_26<63, 136, (ops F4RC:$frD, F4RC:$frB),
607 "fnabs $frD, $frB", FPGeneral,
608 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>;
609 def FNABSD : XForm_26<63, 136, (ops F8RC:$frD, F8RC:$frB),
610 "fnabs $frD, $frB", FPGeneral,
611 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>;
612 def FNEGS : XForm_26<63, 40, (ops F4RC:$frD, F4RC:$frB),
613 "fneg $frD, $frB", FPGeneral,
614 [(set F4RC:$frD, (fneg F4RC:$frB))]>;
615 def FNEGD : XForm_26<63, 40, (ops F8RC:$frD, F8RC:$frB),
616 "fneg $frD, $frB", FPGeneral,
617 [(set F8RC:$frD, (fneg F8RC:$frB))]>;
620 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
621 def STFIWX: XForm_28<31, 983, (ops F8RC:$frS, memrr:$dst),
622 "stfiwx $frS, $dst", LdStUX,
623 [(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>;
624 def STFSX : XForm_28<31, 663, (ops F4RC:$frS, memrr:$dst),
625 "stfsx $frS, $dst", LdStUX,
626 [(store F4RC:$frS, xaddr:$dst)]>;
627 def STFDX : XForm_28<31, 727, (ops F8RC:$frS, memrr:$dst),
628 "stfdx $frS, $dst", LdStUX,
629 [(store F8RC:$frS, xaddr:$dst)]>;
632 // XL-Form instructions. condition register logical ops.
634 def MCRF : XLForm_3<19, 0, (ops CRRC:$BF, CRRC:$BFA),
635 "mcrf $BF, $BFA", BrMCR>,
636 PPC970_DGroup_First, PPC970_Unit_CRU;
638 // XFX-Form instructions. Instructions that deal with SPRs.
640 def MFCTR : XFXForm_1_ext<31, 339, 9, (ops GPRC:$rT), "mfctr $rT", SprMFSPR>,
641 PPC970_DGroup_First, PPC970_Unit_FXU;
642 let Pattern = [(PPCmtctr GPRC:$rS)] in {
643 def MTCTR : XFXForm_7_ext<31, 467, 9, (ops GPRC:$rS), "mtctr $rS", SprMTSPR>,
644 PPC970_DGroup_First, PPC970_Unit_FXU;
647 def MTLR : XFXForm_7_ext<31, 467, 8, (ops GPRC:$rS), "mtlr $rS", SprMTSPR>,
648 PPC970_DGroup_First, PPC970_Unit_FXU;
649 def MFLR : XFXForm_1_ext<31, 339, 8, (ops GPRC:$rT), "mflr $rT", SprMFSPR>,
650 PPC970_DGroup_First, PPC970_Unit_FXU;
652 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like
653 // a GPR on the PPC970. As such, copies in and out have the same performance
654 // characteristics as an OR instruction.
655 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (ops GPRC:$rS),
656 "mtspr 256, $rS", IntGeneral>,
657 PPC970_DGroup_Single, PPC970_Unit_FXU;
658 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (ops GPRC:$rT),
659 "mfspr $rT, 256", IntGeneral>,
660 PPC970_DGroup_First, PPC970_Unit_FXU;
662 def MTCRF : XFXForm_5<31, 144, (ops crbitm:$FXM, GPRC:$rS),
663 "mtcrf $FXM, $rS", BrMCRX>,
664 PPC970_MicroCode, PPC970_Unit_CRU;
665 def MFCR : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT", SprMFCR>,
666 PPC970_MicroCode, PPC970_Unit_CRU;
667 def MFOCRF: XFXForm_5a<31, 19, (ops GPRC:$rT, crbitm:$FXM),
668 "mfcr $rT, $FXM", SprMFCR>,
669 PPC970_DGroup_First, PPC970_Unit_CRU;
671 let PPC970_Unit = 1 in { // FXU Operations.
673 // XO-Form instructions. Arithmetic instructions that can set overflow bit
675 def ADD4 : XOForm_1<31, 266, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
676 "add $rT, $rA, $rB", IntGeneral,
677 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
678 def ADDC : XOForm_1<31, 10, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
679 "addc $rT, $rA, $rB", IntGeneral,
680 [(set GPRC:$rT, (addc GPRC:$rA, GPRC:$rB))]>,
681 PPC970_DGroup_Cracked;
682 def ADDE : XOForm_1<31, 138, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
683 "adde $rT, $rA, $rB", IntGeneral,
684 [(set GPRC:$rT, (adde GPRC:$rA, GPRC:$rB))]>;
685 def DIVW : XOForm_1<31, 491, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
686 "divw $rT, $rA, $rB", IntDivW,
687 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>,
688 PPC970_DGroup_First, PPC970_DGroup_Cracked;
689 def DIVWU : XOForm_1<31, 459, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
690 "divwu $rT, $rA, $rB", IntDivW,
691 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>,
692 PPC970_DGroup_First, PPC970_DGroup_Cracked;
693 def MULHW : XOForm_1<31, 75, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
694 "mulhw $rT, $rA, $rB", IntMulHW,
695 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
696 def MULHWU : XOForm_1<31, 11, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
697 "mulhwu $rT, $rA, $rB", IntMulHWU,
698 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
699 def MULLW : XOForm_1<31, 235, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
700 "mullw $rT, $rA, $rB", IntMulHW,
701 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
702 def SUBF : XOForm_1<31, 40, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
703 "subf $rT, $rA, $rB", IntGeneral,
704 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
705 def SUBFC : XOForm_1<31, 8, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
706 "subfc $rT, $rA, $rB", IntGeneral,
707 [(set GPRC:$rT, (subc GPRC:$rB, GPRC:$rA))]>,
708 PPC970_DGroup_Cracked;
709 def SUBFE : XOForm_1<31, 136, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
710 "subfe $rT, $rA, $rB", IntGeneral,
711 [(set GPRC:$rT, (sube GPRC:$rB, GPRC:$rA))]>;
712 def ADDME : XOForm_3<31, 234, 0, (ops GPRC:$rT, GPRC:$rA),
713 "addme $rT, $rA", IntGeneral,
714 [(set GPRC:$rT, (adde GPRC:$rA, immAllOnes))]>;
715 def ADDZE : XOForm_3<31, 202, 0, (ops GPRC:$rT, GPRC:$rA),
716 "addze $rT, $rA", IntGeneral,
717 [(set GPRC:$rT, (adde GPRC:$rA, 0))]>;
718 def NEG : XOForm_3<31, 104, 0, (ops GPRC:$rT, GPRC:$rA),
719 "neg $rT, $rA", IntGeneral,
720 [(set GPRC:$rT, (ineg GPRC:$rA))]>;
721 def SUBFME : XOForm_3<31, 232, 0, (ops GPRC:$rT, GPRC:$rA),
722 "subfme $rT, $rA", IntGeneral,
723 [(set GPRC:$rT, (sube immAllOnes, GPRC:$rA))]>;
724 def SUBFZE : XOForm_3<31, 200, 0, (ops GPRC:$rT, GPRC:$rA),
725 "subfze $rT, $rA", IntGeneral,
726 [(set GPRC:$rT, (sube 0, GPRC:$rA))]>;
729 // A-Form instructions. Most of the instructions executed in the FPU are of
732 let PPC970_Unit = 3 in { // FPU Operations.
733 def FMADD : AForm_1<63, 29,
734 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
735 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused,
736 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC),
738 Requires<[FPContractions]>;
739 def FMADDS : AForm_1<59, 29,
740 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
741 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
742 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
744 Requires<[FPContractions]>;
745 def FMSUB : AForm_1<63, 28,
746 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
747 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused,
748 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC),
750 Requires<[FPContractions]>;
751 def FMSUBS : AForm_1<59, 28,
752 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
753 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
754 [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC),
756 Requires<[FPContractions]>;
757 def FNMADD : AForm_1<63, 31,
758 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
759 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused,
760 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC),
762 Requires<[FPContractions]>;
763 def FNMADDS : AForm_1<59, 31,
764 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
765 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
766 [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC),
768 Requires<[FPContractions]>;
769 def FNMSUB : AForm_1<63, 30,
770 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
771 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused,
772 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC),
774 Requires<[FPContractions]>;
775 def FNMSUBS : AForm_1<59, 30,
776 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
777 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
778 [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC),
780 Requires<[FPContractions]>;
781 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
782 // having 4 of these, force the comparison to always be an 8-byte double (code
783 // should use an FMRSD if the input comparison value really wants to be a float)
784 // and 4/8 byte forms for the result and operand type..
785 def FSELD : AForm_1<63, 23,
786 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
787 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
788 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>;
789 def FSELS : AForm_1<63, 23,
790 (ops F4RC:$FRT, F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
791 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
792 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>;
793 def FADD : AForm_2<63, 21,
794 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
795 "fadd $FRT, $FRA, $FRB", FPGeneral,
796 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>;
797 def FADDS : AForm_2<59, 21,
798 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
799 "fadds $FRT, $FRA, $FRB", FPGeneral,
800 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>;
801 def FDIV : AForm_2<63, 18,
802 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
803 "fdiv $FRT, $FRA, $FRB", FPDivD,
804 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>;
805 def FDIVS : AForm_2<59, 18,
806 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
807 "fdivs $FRT, $FRA, $FRB", FPDivS,
808 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>;
809 def FMUL : AForm_3<63, 25,
810 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
811 "fmul $FRT, $FRA, $FRB", FPFused,
812 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>;
813 def FMULS : AForm_3<59, 25,
814 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
815 "fmuls $FRT, $FRA, $FRB", FPGeneral,
816 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>;
817 def FSUB : AForm_2<63, 20,
818 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
819 "fsub $FRT, $FRA, $FRB", FPGeneral,
820 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>;
821 def FSUBS : AForm_2<59, 20,
822 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
823 "fsubs $FRT, $FRA, $FRB", FPGeneral,
824 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>;
827 let PPC970_Unit = 1 in { // FXU Operations.
828 // M-Form instructions. rotate and mask instructions.
830 let isTwoAddress = 1, isCommutable = 1 in {
831 // RLWIMI can be commuted if the rotate amount is zero.
832 def RLWIMI : MForm_2<20,
833 (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
834 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate,
835 []>, PPC970_DGroup_Cracked;
837 def RLWINM : MForm_2<21,
838 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
839 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
841 def RLWINMo : MForm_2<21,
842 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
843 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
844 []>, isDOT, PPC970_DGroup_Cracked;
845 def RLWNM : MForm_2<23,
846 (ops GPRC:$rA, GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
847 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral,
852 //===----------------------------------------------------------------------===//
853 // DWARF Pseudo Instructions
856 def DWARF_LOC : Pseudo<(ops i32imm:$line, i32imm:$col, i32imm:$file),
857 "; .loc $file, $line, $col",
858 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
861 def DWARF_LABEL : Pseudo<(ops i32imm:$id),
863 [(dwarf_label (i32 imm:$id))]>;
865 //===----------------------------------------------------------------------===//
866 // PowerPC Instruction Patterns
869 // Arbitrary immediate support. Implement in terms of LIS/ORI.
870 def : Pat<(i32 imm:$imm),
871 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
873 // Implement the 'not' operation with the NOR instruction.
874 def NOT : Pat<(not GPRC:$in),
875 (NOR GPRC:$in, GPRC:$in)>;
877 // ADD an arbitrary immediate.
878 def : Pat<(add GPRC:$in, imm:$imm),
879 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
880 // OR an arbitrary immediate.
881 def : Pat<(or GPRC:$in, imm:$imm),
882 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
883 // XOR an arbitrary immediate.
884 def : Pat<(xor GPRC:$in, imm:$imm),
885 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
887 def : Pat<(sub immSExt16:$imm, GPRC:$in),
888 (SUBFIC GPRC:$in, imm:$imm)>;
890 // Return void support.
891 def : Pat<(ret), (BLR)>;
894 def : Pat<(shl GPRC:$in, (i32 imm:$imm)),
895 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>;
896 def : Pat<(srl GPRC:$in, (i32 imm:$imm)),
897 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>;
900 def : Pat<(rotl GPRC:$in, GPRC:$sh),
901 (RLWNM GPRC:$in, GPRC:$sh, 0, 31)>;
902 def : Pat<(rotl GPRC:$in, (i32 imm:$imm)),
903 (RLWINM GPRC:$in, imm:$imm, 0, 31)>;
906 def : Pat<(PPCcall tglobaladdr:$dst),
907 (BL tglobaladdr:$dst)>;
908 def : Pat<(PPCcall texternalsym:$dst),
909 (BL texternalsym:$dst)>;
911 // Hi and Lo for Darwin Global Addresses.
912 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
913 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
914 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
915 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
916 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
917 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
918 def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)),
919 (ADDIS GPRC:$in, tglobaladdr:$g)>;
920 def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)),
921 (ADDIS GPRC:$in, tconstpool:$g)>;
922 def : Pat<(add GPRC:$in, (PPChi tjumptable:$g, 0)),
923 (ADDIS GPRC:$in, tjumptable:$g)>;
925 // Fused negative multiply subtract, alternate pattern
926 def : Pat<(fsub F8RC:$B, (fmul F8RC:$A, F8RC:$C)),
927 (FNMSUB F8RC:$A, F8RC:$C, F8RC:$B)>,
928 Requires<[FPContractions]>;
929 def : Pat<(fsub F4RC:$B, (fmul F4RC:$A, F4RC:$C)),
930 (FNMSUBS F4RC:$A, F4RC:$C, F4RC:$B)>,
931 Requires<[FPContractions]>;
933 // Standard shifts. These are represented separately from the real shifts above
934 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
936 def : Pat<(sra GPRC:$rS, GPRC:$rB),
937 (SRAW GPRC:$rS, GPRC:$rB)>;
938 def : Pat<(srl GPRC:$rS, GPRC:$rB),
939 (SRW GPRC:$rS, GPRC:$rB)>;
940 def : Pat<(shl GPRC:$rS, GPRC:$rB),
941 (SLW GPRC:$rS, GPRC:$rB)>;
943 def : Pat<(zextload iaddr:$src, i1),
945 def : Pat<(zextload xaddr:$src, i1),
947 def : Pat<(extload iaddr:$src, i1),
949 def : Pat<(extload xaddr:$src, i1),
951 def : Pat<(extload iaddr:$src, i8),
953 def : Pat<(extload xaddr:$src, i8),
955 def : Pat<(extload iaddr:$src, i16),
957 def : Pat<(extload xaddr:$src, i16),
959 def : Pat<(extload iaddr:$src, f32),
960 (FMRSD (LFS iaddr:$src))>;
961 def : Pat<(extload xaddr:$src, f32),
962 (FMRSD (LFSX xaddr:$src))>;
964 include "PPCInstrAltivec.td"
965 include "PPCInstr64Bit.td"