1 //===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
24 def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
26 def SDT_PPCvperm : SDTypeProfile<1, 3, [
27 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
30 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
31 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
34 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
35 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
38 def SDT_PPClbrx : SDTypeProfile<1, 2, [
39 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
41 def SDT_PPCstbrx : SDTypeProfile<0, 3, [
42 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
45 def SDT_PPClarx : SDTypeProfile<1, 1, [
46 SDTCisInt<0>, SDTCisPtrTy<1>
48 def SDT_PPCstcx : SDTypeProfile<0, 2, [
49 SDTCisInt<0>, SDTCisPtrTy<1>
52 def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
53 SDTCisPtrTy<0>, SDTCisVT<1, i32>
57 //===----------------------------------------------------------------------===//
58 // PowerPC specific DAG Nodes.
61 def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>;
62 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
63 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
64 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
65 [SDNPHasChain, SDNPMayStore]>;
67 // Extract FPSCR (not modeled at the DAG level).
68 def PPCmffs : SDNode<"PPCISD::MFFS",
69 SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, []>;
71 // Perform FADD in round-to-zero mode.
72 def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>;
75 def PPCfsel : SDNode<"PPCISD::FSEL",
76 // Type constraint for fsel.
77 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
78 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
80 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
81 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
82 def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, [SDNPMayLoad]>;
83 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
84 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
86 def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>;
87 def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp,
89 def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>;
90 def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>;
91 def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>;
92 def PPCgetTlsAddr : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>;
93 def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>;
94 def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>;
95 def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>;
96 def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp,
98 def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>;
100 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
102 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
103 // amounts. These nodes are generated by the multi-precision shift code.
104 def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>;
105 def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>;
106 def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>;
108 def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>;
109 def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore,
110 [SDNPHasChain, SDNPMayStore]>;
112 // These are target-independent nodes, but have target-specific formats.
113 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
114 [SDNPHasChain, SDNPOutGlue]>;
115 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd,
116 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
118 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
119 def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall,
120 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
122 def PPCcall_nop : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall,
123 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
125 def PPCload : SDNode<"PPCISD::LOAD", SDTypeProfile<1, 1, []>,
126 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
127 def PPCload_toc : SDNode<"PPCISD::LOAD_TOC", SDTypeProfile<0, 1, []>,
128 [SDNPHasChain, SDNPSideEffect,
129 SDNPInGlue, SDNPOutGlue]>;
130 def PPCtoc_restore : SDNode<"PPCISD::TOC_RESTORE", SDTypeProfile<0, 0, []>,
131 [SDNPHasChain, SDNPSideEffect,
132 SDNPInGlue, SDNPOutGlue]>;
133 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
134 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
135 def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone,
136 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
139 def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone,
140 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
142 def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
143 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
145 def PPCeh_sjlj_setjmp : SDNode<"PPCISD::EH_SJLJ_SETJMP",
146 SDTypeProfile<1, 1, [SDTCisInt<0>,
148 [SDNPHasChain, SDNPSideEffect]>;
149 def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP",
150 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
151 [SDNPHasChain, SDNPSideEffect]>;
153 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
154 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>;
156 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
157 [SDNPHasChain, SDNPOptInGlue]>;
159 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
160 [SDNPHasChain, SDNPMayLoad]>;
161 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
162 [SDNPHasChain, SDNPMayStore]>;
164 // Instructions to set/unset CR bit 6 for SVR4 vararg calls
165 def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone,
166 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
167 def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone,
168 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
170 // Instructions to support atomic operations
171 def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx,
172 [SDNPHasChain, SDNPMayLoad]>;
173 def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx,
174 [SDNPHasChain, SDNPMayStore]>;
176 // Instructions to support medium and large code model
177 def PPCaddisTocHA : SDNode<"PPCISD::ADDIS_TOC_HA", SDTIntBinOp, []>;
178 def PPCldTocL : SDNode<"PPCISD::LD_TOC_L", SDTIntBinOp, [SDNPMayLoad]>;
179 def PPCaddiTocL : SDNode<"PPCISD::ADDI_TOC_L", SDTIntBinOp, []>;
182 // Instructions to support dynamic alloca.
183 def SDTDynOp : SDTypeProfile<1, 2, []>;
184 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
186 //===----------------------------------------------------------------------===//
187 // PowerPC specific transformation functions and pattern fragments.
190 def SHL32 : SDNodeXForm<imm, [{
191 // Transformation function: 31 - imm
192 return getI32Imm(31 - N->getZExtValue());
195 def SRL32 : SDNodeXForm<imm, [{
196 // Transformation function: 32 - imm
197 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0);
200 def LO16 : SDNodeXForm<imm, [{
201 // Transformation function: get the low 16 bits.
202 return getI32Imm((unsigned short)N->getZExtValue());
205 def HI16 : SDNodeXForm<imm, [{
206 // Transformation function: shift the immediate value down into the low bits.
207 return getI32Imm((unsigned)N->getZExtValue() >> 16);
210 def HA16 : SDNodeXForm<imm, [{
211 // Transformation function: shift the immediate value down into the low bits.
212 signed int Val = N->getZExtValue();
213 return getI32Imm((Val - (signed short)Val) >> 16);
215 def MB : SDNodeXForm<imm, [{
216 // Transformation function: get the start bit of a mask
218 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
219 return getI32Imm(mb);
222 def ME : SDNodeXForm<imm, [{
223 // Transformation function: get the end bit of a mask
225 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
226 return getI32Imm(me);
228 def maskimm32 : PatLeaf<(imm), [{
229 // maskImm predicate - True if immediate is a run of ones.
231 if (N->getValueType(0) == MVT::i32)
232 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
237 def immSExt16 : PatLeaf<(imm), [{
238 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
239 // field. Used by instructions like 'addi'.
240 if (N->getValueType(0) == MVT::i32)
241 return (int32_t)N->getZExtValue() == (short)N->getZExtValue();
243 return (int64_t)N->getZExtValue() == (short)N->getZExtValue();
245 def immZExt16 : PatLeaf<(imm), [{
246 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
247 // field. Used by instructions like 'ori'.
248 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
251 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
252 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
253 // identical in 32-bit mode, but in 64-bit mode, they return true if the
254 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
256 def imm16ShiftedZExt : PatLeaf<(imm), [{
257 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
258 // immediate are set. Used by instructions like 'xoris'.
259 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
262 def imm16ShiftedSExt : PatLeaf<(imm), [{
263 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
264 // immediate are set. Used by instructions like 'addis'. Identical to
265 // imm16ShiftedZExt in 32-bit mode.
266 if (N->getZExtValue() & 0xFFFF) return false;
267 if (N->getValueType(0) == MVT::i32)
269 // For 64-bit, make sure it is sext right.
270 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
273 // Some r+i load/store instructions (such as LD, STD, LDU, etc.) that require
274 // restricted memrix (offset/4) constants are alignment sensitive. If these
275 // offsets are hidden behind TOC entries than the values of the lower-order
276 // bits cannot be checked directly. As a result, we need to also incorporate
277 // an alignment check into the relevant patterns.
279 def aligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
280 return cast<LoadSDNode>(N)->getAlignment() >= 4;
282 def aligned4store : PatFrag<(ops node:$val, node:$ptr),
283 (store node:$val, node:$ptr), [{
284 return cast<StoreSDNode>(N)->getAlignment() >= 4;
286 def aligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
287 return cast<LoadSDNode>(N)->getAlignment() >= 4;
289 def aligned4pre_store : PatFrag<
290 (ops node:$val, node:$base, node:$offset),
291 (pre_store node:$val, node:$base, node:$offset), [{
292 return cast<StoreSDNode>(N)->getAlignment() >= 4;
295 def unaligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
296 return cast<LoadSDNode>(N)->getAlignment() < 4;
298 def unaligned4store : PatFrag<(ops node:$val, node:$ptr),
299 (store node:$val, node:$ptr), [{
300 return cast<StoreSDNode>(N)->getAlignment() < 4;
302 def unaligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
303 return cast<LoadSDNode>(N)->getAlignment() < 4;
306 //===----------------------------------------------------------------------===//
307 // PowerPC Flag Definitions.
309 class isPPC64 { bit PPC64 = 1; }
311 list<Register> Defs = [CR0];
315 class RegConstraint<string C> {
316 string Constraints = C;
318 class NoEncode<string E> {
319 string DisableEncoding = E;
323 //===----------------------------------------------------------------------===//
324 // PowerPC Operand Definitions.
326 def s5imm : Operand<i32> {
327 let PrintMethod = "printS5ImmOperand";
329 def u5imm : Operand<i32> {
330 let PrintMethod = "printU5ImmOperand";
332 def u6imm : Operand<i32> {
333 let PrintMethod = "printU6ImmOperand";
335 def s16imm : Operand<i32> {
336 let PrintMethod = "printS16ImmOperand";
338 def u16imm : Operand<i32> {
339 let PrintMethod = "printU16ImmOperand";
341 def directbrtarget : Operand<OtherVT> {
342 let PrintMethod = "printBranchOperand";
343 let EncoderMethod = "getDirectBrEncoding";
345 def condbrtarget : Operand<OtherVT> {
346 let PrintMethod = "printBranchOperand";
347 let EncoderMethod = "getCondBrEncoding";
349 def calltarget : Operand<iPTR> {
350 let EncoderMethod = "getDirectBrEncoding";
352 def aaddr : Operand<iPTR> {
353 let PrintMethod = "printAbsAddrOperand";
355 def symbolHi: Operand<i32> {
356 let PrintMethod = "printSymbolHi";
357 let EncoderMethod = "getHA16Encoding";
359 def symbolLo: Operand<i32> {
360 let PrintMethod = "printSymbolLo";
361 let EncoderMethod = "getLO16Encoding";
363 def crbitm: Operand<i8> {
364 let PrintMethod = "printcrbitm";
365 let EncoderMethod = "get_crbitm_encoding";
368 // A version of ptr_rc which excludes R0 (or X0 in 64-bit mode).
369 def ptr_rc_nor0 : PointerLikeRegClass<1>;
371 def dispRI : Operand<iPTR>;
372 def dispRIX : Operand<iPTR>;
374 def memri : Operand<iPTR> {
375 let PrintMethod = "printMemRegImm";
376 let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg);
377 let EncoderMethod = "getMemRIEncoding";
379 def memrr : Operand<iPTR> {
380 let PrintMethod = "printMemRegReg";
381 let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc:$offreg);
383 def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits.
384 let PrintMethod = "printMemRegImmShifted";
385 let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg);
386 let EncoderMethod = "getMemRIXEncoding";
389 // A single-register address. This is used with the SjLj
390 // pseudo-instructions.
391 def memr : Operand<iPTR> {
392 let MIOperandInfo = (ops ptr_rc:$ptrreg);
395 // PowerPC Predicate operand.
396 def pred : Operand<OtherVT> {
397 let PrintMethod = "printPredicateOperand";
398 let MIOperandInfo = (ops i32imm:$bibo, CRRC:$reg);
401 // Define PowerPC specific addressing mode.
402 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
403 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
404 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
405 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std"
407 // The address in a single register. This is used with the SjLj
408 // pseudo-instructions.
409 def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>;
411 /// This is just the offset part of iaddr, used for preinc.
412 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
414 //===----------------------------------------------------------------------===//
415 // PowerPC Instruction Predicate Definitions.
416 def In32BitMode : Predicate<"!PPCSubTarget.isPPC64()">;
417 def In64BitMode : Predicate<"PPCSubTarget.isPPC64()">;
418 def IsBookE : Predicate<"PPCSubTarget.isBookE()">;
420 //===----------------------------------------------------------------------===//
421 // PowerPC Instruction Definitions.
423 // Pseudo-instructions:
425 let hasCtrlDep = 1 in {
426 let Defs = [R1], Uses = [R1] in {
427 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt",
428 [(callseq_start timm:$amt)]>;
429 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt2",
430 [(callseq_end timm:$amt1, timm:$amt2)]>;
433 def UPDATE_VRSAVE : Pseudo<(outs GPRC:$rD), (ins GPRC:$rS),
434 "UPDATE_VRSAVE $rD, $rS", []>;
437 let Defs = [R1], Uses = [R1] in
438 def DYNALLOC : Pseudo<(outs GPRC:$result), (ins GPRC:$negsize, memri:$fpsi), "#DYNALLOC",
440 (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>;
442 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
443 // instruction selection into a branch sequence.
444 let usesCustomInserter = 1, // Expanded after instruction selection.
445 PPC970_Single = 1 in {
446 // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes
447 // because either operand might become the first operand in an isel, and
448 // that operand cannot be r0.
449 def SELECT_CC_I4 : Pseudo<(outs GPRC:$dst), (ins CRRC:$cond,
450 GPRC_NOR0:$T, GPRC_NOR0:$F,
451 i32imm:$BROPC), "#SELECT_CC_I4",
453 def SELECT_CC_I8 : Pseudo<(outs G8RC:$dst), (ins CRRC:$cond,
454 G8RC_NOX0:$T, G8RC_NOX0:$F,
455 i32imm:$BROPC), "#SELECT_CC_I8",
457 def SELECT_CC_F4 : Pseudo<(outs F4RC:$dst), (ins CRRC:$cond, F4RC:$T, F4RC:$F,
458 i32imm:$BROPC), "#SELECT_CC_F4",
460 def SELECT_CC_F8 : Pseudo<(outs F8RC:$dst), (ins CRRC:$cond, F8RC:$T, F8RC:$F,
461 i32imm:$BROPC), "#SELECT_CC_F8",
463 def SELECT_CC_VRRC: Pseudo<(outs VRRC:$dst), (ins CRRC:$cond, VRRC:$T, VRRC:$F,
464 i32imm:$BROPC), "#SELECT_CC_VRRC",
468 // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
469 // scavenge a register for it.
471 def SPILL_CR : Pseudo<(outs), (ins CRRC:$cond, memri:$F),
474 // RESTORE_CR - Indicate that we're restoring the CR register (previously
475 // spilled), so we'll need to scavenge a register for it.
477 def RESTORE_CR : Pseudo<(outs CRRC:$cond), (ins memri:$F),
480 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
481 let isReturn = 1, Uses = [LR, RM] in
482 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", BrB,
484 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in
485 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>;
489 def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>,
492 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
493 let isBarrier = 1 in {
494 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst),
499 // BCC represents an arbitrary conditional branch on a predicate.
500 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
501 // a two-value operand where a dag node expects two operands. :(
502 let isCodeGenOnly = 1 in
503 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst),
504 "b${cond:cc} ${cond:reg}, $dst"
505 /*[(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]*/>;
507 let Defs = [CTR], Uses = [CTR] in {
508 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
510 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
515 // The direct BCL used by the SjLj setjmp code.
516 let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7 in {
517 let Defs = [LR], Uses = [RM] in {
518 def BCL : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst),
523 let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
524 // Convenient aliases for call instructions
526 def BL : IForm<18, 0, 1, (outs), (ins calltarget:$func),
527 "bl $func", BrB, []>; // See Pat patterns below.
528 def BLA : IForm<18, 1, 1, (outs), (ins aaddr:$func),
529 "bla $func", BrB, [(PPCcall (i32 imm:$func))]>;
531 let Uses = [CTR, RM] in {
532 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
533 "bctrl", BrB, [(PPCbctrl)]>,
534 Requires<[In32BitMode]>;
538 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
539 def TCRETURNdi :Pseudo< (outs),
540 (ins calltarget:$dst, i32imm:$offset),
541 "#TC_RETURNd $dst $offset",
545 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
546 def TCRETURNai :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset),
547 "#TC_RETURNa $func $offset",
548 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
550 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
551 def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset),
552 "#TC_RETURNr $dst $offset",
556 let isCodeGenOnly = 1 in {
558 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
559 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in
560 def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
561 Requires<[In32BitMode]>;
565 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
566 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
567 def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
573 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
574 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
575 def TAILBA : IForm<18, 0, 0, (outs), (ins aaddr:$dst),
579 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
580 def EH_SjLj_SetJmp32 : Pseudo<(outs GPRC:$dst), (ins memr:$buf),
582 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
583 Requires<[In32BitMode]>;
584 let isTerminator = 1 in
585 def EH_SjLj_LongJmp32 : Pseudo<(outs), (ins memr:$buf),
586 "#EH_SJLJ_LONGJMP32",
587 [(PPCeh_sjlj_longjmp addr:$buf)]>,
588 Requires<[In32BitMode]>;
591 let isBranch = 1, isTerminator = 1 in {
592 def EH_SjLj_Setup : Pseudo<(outs), (ins directbrtarget:$dst),
593 "#EH_SjLj_Setup\t$dst", []>;
596 // DCB* instructions.
597 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst),
598 "dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
599 PPC970_DGroup_Single;
600 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst),
601 "dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
602 PPC970_DGroup_Single;
603 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst),
604 "dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
605 PPC970_DGroup_Single;
606 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst),
607 "dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
608 PPC970_DGroup_Single;
609 def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst),
610 "dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
611 PPC970_DGroup_Single;
612 def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst),
613 "dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
614 PPC970_DGroup_Single;
615 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst),
616 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
617 PPC970_DGroup_Single;
618 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst),
619 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
620 PPC970_DGroup_Single;
622 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
626 let usesCustomInserter = 1 in {
627 let Defs = [CR0] in {
628 def ATOMIC_LOAD_ADD_I8 : Pseudo<
629 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_ADD_I8",
630 [(set i32:$dst, (atomic_load_add_8 xoaddr:$ptr, i32:$incr))]>;
631 def ATOMIC_LOAD_SUB_I8 : Pseudo<
632 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_SUB_I8",
633 [(set i32:$dst, (atomic_load_sub_8 xoaddr:$ptr, i32:$incr))]>;
634 def ATOMIC_LOAD_AND_I8 : Pseudo<
635 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_AND_I8",
636 [(set i32:$dst, (atomic_load_and_8 xoaddr:$ptr, i32:$incr))]>;
637 def ATOMIC_LOAD_OR_I8 : Pseudo<
638 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_OR_I8",
639 [(set i32:$dst, (atomic_load_or_8 xoaddr:$ptr, i32:$incr))]>;
640 def ATOMIC_LOAD_XOR_I8 : Pseudo<
641 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "ATOMIC_LOAD_XOR_I8",
642 [(set i32:$dst, (atomic_load_xor_8 xoaddr:$ptr, i32:$incr))]>;
643 def ATOMIC_LOAD_NAND_I8 : Pseudo<
644 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_NAND_I8",
645 [(set i32:$dst, (atomic_load_nand_8 xoaddr:$ptr, i32:$incr))]>;
646 def ATOMIC_LOAD_ADD_I16 : Pseudo<
647 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_ADD_I16",
648 [(set i32:$dst, (atomic_load_add_16 xoaddr:$ptr, i32:$incr))]>;
649 def ATOMIC_LOAD_SUB_I16 : Pseudo<
650 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_SUB_I16",
651 [(set i32:$dst, (atomic_load_sub_16 xoaddr:$ptr, i32:$incr))]>;
652 def ATOMIC_LOAD_AND_I16 : Pseudo<
653 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_AND_I16",
654 [(set i32:$dst, (atomic_load_and_16 xoaddr:$ptr, i32:$incr))]>;
655 def ATOMIC_LOAD_OR_I16 : Pseudo<
656 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_OR_I16",
657 [(set i32:$dst, (atomic_load_or_16 xoaddr:$ptr, i32:$incr))]>;
658 def ATOMIC_LOAD_XOR_I16 : Pseudo<
659 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_XOR_I16",
660 [(set i32:$dst, (atomic_load_xor_16 xoaddr:$ptr, i32:$incr))]>;
661 def ATOMIC_LOAD_NAND_I16 : Pseudo<
662 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_NAND_I16",
663 [(set i32:$dst, (atomic_load_nand_16 xoaddr:$ptr, i32:$incr))]>;
664 def ATOMIC_LOAD_ADD_I32 : Pseudo<
665 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_ADD_I32",
666 [(set i32:$dst, (atomic_load_add_32 xoaddr:$ptr, i32:$incr))]>;
667 def ATOMIC_LOAD_SUB_I32 : Pseudo<
668 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_SUB_I32",
669 [(set i32:$dst, (atomic_load_sub_32 xoaddr:$ptr, i32:$incr))]>;
670 def ATOMIC_LOAD_AND_I32 : Pseudo<
671 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_AND_I32",
672 [(set i32:$dst, (atomic_load_and_32 xoaddr:$ptr, i32:$incr))]>;
673 def ATOMIC_LOAD_OR_I32 : Pseudo<
674 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_OR_I32",
675 [(set i32:$dst, (atomic_load_or_32 xoaddr:$ptr, i32:$incr))]>;
676 def ATOMIC_LOAD_XOR_I32 : Pseudo<
677 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_XOR_I32",
678 [(set i32:$dst, (atomic_load_xor_32 xoaddr:$ptr, i32:$incr))]>;
679 def ATOMIC_LOAD_NAND_I32 : Pseudo<
680 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_NAND_I32",
681 [(set i32:$dst, (atomic_load_nand_32 xoaddr:$ptr, i32:$incr))]>;
683 def ATOMIC_CMP_SWAP_I8 : Pseudo<
684 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "#ATOMIC_CMP_SWAP_I8",
685 [(set i32:$dst, (atomic_cmp_swap_8 xoaddr:$ptr, i32:$old, i32:$new))]>;
686 def ATOMIC_CMP_SWAP_I16 : Pseudo<
687 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new",
688 [(set i32:$dst, (atomic_cmp_swap_16 xoaddr:$ptr, i32:$old, i32:$new))]>;
689 def ATOMIC_CMP_SWAP_I32 : Pseudo<
690 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new",
691 [(set i32:$dst, (atomic_cmp_swap_32 xoaddr:$ptr, i32:$old, i32:$new))]>;
693 def ATOMIC_SWAP_I8 : Pseudo<
694 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "#ATOMIC_SWAP_i8",
695 [(set i32:$dst, (atomic_swap_8 xoaddr:$ptr, i32:$new))]>;
696 def ATOMIC_SWAP_I16 : Pseudo<
697 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "#ATOMIC_SWAP_I16",
698 [(set i32:$dst, (atomic_swap_16 xoaddr:$ptr, i32:$new))]>;
699 def ATOMIC_SWAP_I32 : Pseudo<
700 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "#ATOMIC_SWAP_I32",
701 [(set i32:$dst, (atomic_swap_32 xoaddr:$ptr, i32:$new))]>;
705 // Instructions to support atomic operations
706 def LWARX : XForm_1<31, 20, (outs GPRC:$rD), (ins memrr:$src),
707 "lwarx $rD, $src", LdStLWARX,
708 [(set i32:$rD, (PPClarx xoaddr:$src))]>;
711 def STWCX : XForm_1<31, 150, (outs), (ins GPRC:$rS, memrr:$dst),
712 "stwcx. $rS, $dst", LdStSTWCX,
713 [(PPCstcx i32:$rS, xoaddr:$dst)]>,
716 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
717 def TRAP : XForm_24<31, 4, (outs), (ins), "trap", LdStLoad, [(trap)]>;
719 //===----------------------------------------------------------------------===//
720 // PPC32 Load Instructions.
723 // Unindexed (r+i) Loads.
724 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
725 def LBZ : DForm_1<34, (outs GPRC:$rD), (ins memri:$src),
726 "lbz $rD, $src", LdStLoad,
727 [(set i32:$rD, (zextloadi8 iaddr:$src))]>;
728 def LHA : DForm_1<42, (outs GPRC:$rD), (ins memri:$src),
729 "lha $rD, $src", LdStLHA,
730 [(set i32:$rD, (sextloadi16 iaddr:$src))]>,
731 PPC970_DGroup_Cracked;
732 def LHZ : DForm_1<40, (outs GPRC:$rD), (ins memri:$src),
733 "lhz $rD, $src", LdStLoad,
734 [(set i32:$rD, (zextloadi16 iaddr:$src))]>;
735 def LWZ : DForm_1<32, (outs GPRC:$rD), (ins memri:$src),
736 "lwz $rD, $src", LdStLoad,
737 [(set i32:$rD, (load iaddr:$src))]>;
739 def LFS : DForm_1<48, (outs F4RC:$rD), (ins memri:$src),
740 "lfs $rD, $src", LdStLFD,
741 [(set f32:$rD, (load iaddr:$src))]>;
742 def LFD : DForm_1<50, (outs F8RC:$rD), (ins memri:$src),
743 "lfd $rD, $src", LdStLFD,
744 [(set f64:$rD, (load iaddr:$src))]>;
747 // Unindexed (r+i) Loads with Update (preinc).
749 def LBZU : DForm_1<35, (outs GPRC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
750 "lbzu $rD, $addr", LdStLoadUpd,
751 []>, RegConstraint<"$addr.reg = $ea_result">,
752 NoEncode<"$ea_result">;
754 def LHAU : DForm_1<43, (outs GPRC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
755 "lhau $rD, $addr", LdStLHAU,
756 []>, RegConstraint<"$addr.reg = $ea_result">,
757 NoEncode<"$ea_result">;
759 def LHZU : DForm_1<41, (outs GPRC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
760 "lhzu $rD, $addr", LdStLoadUpd,
761 []>, RegConstraint<"$addr.reg = $ea_result">,
762 NoEncode<"$ea_result">;
764 def LWZU : DForm_1<33, (outs GPRC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
765 "lwzu $rD, $addr", LdStLoadUpd,
766 []>, RegConstraint<"$addr.reg = $ea_result">,
767 NoEncode<"$ea_result">;
769 def LFSU : DForm_1<49, (outs F4RC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
770 "lfsu $rD, $addr", LdStLFDU,
771 []>, RegConstraint<"$addr.reg = $ea_result">,
772 NoEncode<"$ea_result">;
774 def LFDU : DForm_1<51, (outs F8RC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
775 "lfdu $rD, $addr", LdStLFDU,
776 []>, RegConstraint<"$addr.reg = $ea_result">,
777 NoEncode<"$ea_result">;
780 // Indexed (r+r) Loads with Update (preinc).
781 def LBZUX : XForm_1<31, 119, (outs GPRC:$rD, ptr_rc_nor0:$ea_result),
783 "lbzux $rD, $addr", LdStLoadUpd,
784 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
785 NoEncode<"$ea_result">;
787 def LHAUX : XForm_1<31, 375, (outs GPRC:$rD, ptr_rc_nor0:$ea_result),
789 "lhaux $rD, $addr", LdStLHAU,
790 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
791 NoEncode<"$ea_result">;
793 def LHZUX : XForm_1<31, 311, (outs GPRC:$rD, ptr_rc_nor0:$ea_result),
795 "lhzux $rD, $addr", LdStLoadUpd,
796 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
797 NoEncode<"$ea_result">;
799 def LWZUX : XForm_1<31, 55, (outs GPRC:$rD, ptr_rc_nor0:$ea_result),
801 "lwzux $rD, $addr", LdStLoadUpd,
802 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
803 NoEncode<"$ea_result">;
805 def LFSUX : XForm_1<31, 567, (outs F4RC:$rD, ptr_rc_nor0:$ea_result),
807 "lfsux $rD, $addr", LdStLFDU,
808 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
809 NoEncode<"$ea_result">;
811 def LFDUX : XForm_1<31, 631, (outs F8RC:$rD, ptr_rc_nor0:$ea_result),
813 "lfdux $rD, $addr", LdStLFDU,
814 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
815 NoEncode<"$ea_result">;
819 // Indexed (r+r) Loads.
821 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
822 def LBZX : XForm_1<31, 87, (outs GPRC:$rD), (ins memrr:$src),
823 "lbzx $rD, $src", LdStLoad,
824 [(set i32:$rD, (zextloadi8 xaddr:$src))]>;
825 def LHAX : XForm_1<31, 343, (outs GPRC:$rD), (ins memrr:$src),
826 "lhax $rD, $src", LdStLHA,
827 [(set i32:$rD, (sextloadi16 xaddr:$src))]>,
828 PPC970_DGroup_Cracked;
829 def LHZX : XForm_1<31, 279, (outs GPRC:$rD), (ins memrr:$src),
830 "lhzx $rD, $src", LdStLoad,
831 [(set i32:$rD, (zextloadi16 xaddr:$src))]>;
832 def LWZX : XForm_1<31, 23, (outs GPRC:$rD), (ins memrr:$src),
833 "lwzx $rD, $src", LdStLoad,
834 [(set i32:$rD, (load xaddr:$src))]>;
837 def LHBRX : XForm_1<31, 790, (outs GPRC:$rD), (ins memrr:$src),
838 "lhbrx $rD, $src", LdStLoad,
839 [(set i32:$rD, (PPClbrx xoaddr:$src, i16))]>;
840 def LWBRX : XForm_1<31, 534, (outs GPRC:$rD), (ins memrr:$src),
841 "lwbrx $rD, $src", LdStLoad,
842 [(set i32:$rD, (PPClbrx xoaddr:$src, i32))]>;
844 def LFSX : XForm_25<31, 535, (outs F4RC:$frD), (ins memrr:$src),
845 "lfsx $frD, $src", LdStLFD,
846 [(set f32:$frD, (load xaddr:$src))]>;
847 def LFDX : XForm_25<31, 599, (outs F8RC:$frD), (ins memrr:$src),
848 "lfdx $frD, $src", LdStLFD,
849 [(set f64:$frD, (load xaddr:$src))]>;
852 //===----------------------------------------------------------------------===//
853 // PPC32 Store Instructions.
856 // Unindexed (r+i) Stores.
857 let PPC970_Unit = 2 in {
858 def STB : DForm_1<38, (outs), (ins GPRC:$rS, memri:$src),
859 "stb $rS, $src", LdStStore,
860 [(truncstorei8 i32:$rS, iaddr:$src)]>;
861 def STH : DForm_1<44, (outs), (ins GPRC:$rS, memri:$src),
862 "sth $rS, $src", LdStStore,
863 [(truncstorei16 i32:$rS, iaddr:$src)]>;
864 def STW : DForm_1<36, (outs), (ins GPRC:$rS, memri:$src),
865 "stw $rS, $src", LdStStore,
866 [(store i32:$rS, iaddr:$src)]>;
867 def STFS : DForm_1<52, (outs), (ins F4RC:$rS, memri:$dst),
868 "stfs $rS, $dst", LdStSTFD,
869 [(store f32:$rS, iaddr:$dst)]>;
870 def STFD : DForm_1<54, (outs), (ins F8RC:$rS, memri:$dst),
871 "stfd $rS, $dst", LdStSTFD,
872 [(store f64:$rS, iaddr:$dst)]>;
875 // Unindexed (r+i) Stores with Update (preinc).
876 let PPC970_Unit = 2, mayStore = 1 in {
877 def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memri:$dst),
878 "stbu $rS, $dst", LdStStoreUpd, []>,
879 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
880 def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memri:$dst),
881 "sthu $rS, $dst", LdStStoreUpd, []>,
882 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
883 def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memri:$dst),
884 "stwu $rS, $dst", LdStStoreUpd, []>,
885 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
886 def STFSU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins F4RC:$rS, memri:$dst),
887 "stfsu $rS, $dst", LdStSTFDU, []>,
888 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
889 def STFDU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins F8RC:$rS, memri:$dst),
890 "stfdu $rS, $dst", LdStSTFDU, []>,
891 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
894 // Patterns to match the pre-inc stores. We can't put the patterns on
895 // the instruction definitions directly as ISel wants the address base
896 // and offset to be separate operands, not a single complex operand.
897 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
898 (STBU $rS, iaddroff:$ptroff, $ptrreg)>;
899 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
900 (STHU $rS, iaddroff:$ptroff, $ptrreg)>;
901 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
902 (STWU $rS, iaddroff:$ptroff, $ptrreg)>;
903 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
904 (STFSU $rS, iaddroff:$ptroff, $ptrreg)>;
905 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
906 (STFDU $rS, iaddroff:$ptroff, $ptrreg)>;
908 // Indexed (r+r) Stores.
909 let PPC970_Unit = 2 in {
910 def STBX : XForm_8<31, 215, (outs), (ins GPRC:$rS, memrr:$dst),
911 "stbx $rS, $dst", LdStStore,
912 [(truncstorei8 i32:$rS, xaddr:$dst)]>,
913 PPC970_DGroup_Cracked;
914 def STHX : XForm_8<31, 407, (outs), (ins GPRC:$rS, memrr:$dst),
915 "sthx $rS, $dst", LdStStore,
916 [(truncstorei16 i32:$rS, xaddr:$dst)]>,
917 PPC970_DGroup_Cracked;
918 def STWX : XForm_8<31, 151, (outs), (ins GPRC:$rS, memrr:$dst),
919 "stwx $rS, $dst", LdStStore,
920 [(store i32:$rS, xaddr:$dst)]>,
921 PPC970_DGroup_Cracked;
923 def STHBRX: XForm_8<31, 918, (outs), (ins GPRC:$rS, memrr:$dst),
924 "sthbrx $rS, $dst", LdStStore,
925 [(PPCstbrx i32:$rS, xoaddr:$dst, i16)]>,
926 PPC970_DGroup_Cracked;
927 def STWBRX: XForm_8<31, 662, (outs), (ins GPRC:$rS, memrr:$dst),
928 "stwbrx $rS, $dst", LdStStore,
929 [(PPCstbrx i32:$rS, xoaddr:$dst, i32)]>,
930 PPC970_DGroup_Cracked;
932 def STFIWX: XForm_28<31, 983, (outs), (ins F8RC:$frS, memrr:$dst),
933 "stfiwx $frS, $dst", LdStSTFD,
934 [(PPCstfiwx f64:$frS, xoaddr:$dst)]>;
936 def STFSX : XForm_28<31, 663, (outs), (ins F4RC:$frS, memrr:$dst),
937 "stfsx $frS, $dst", LdStSTFD,
938 [(store f32:$frS, xaddr:$dst)]>;
939 def STFDX : XForm_28<31, 727, (outs), (ins F8RC:$frS, memrr:$dst),
940 "stfdx $frS, $dst", LdStSTFD,
941 [(store f64:$frS, xaddr:$dst)]>;
944 // Indexed (r+r) Stores with Update (preinc).
945 let PPC970_Unit = 2, mayStore = 1 in {
946 def STBUX : XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memrr:$dst),
947 "stbux $rS, $dst", LdStStoreUpd, []>,
948 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
949 PPC970_DGroup_Cracked;
950 def STHUX : XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memrr:$dst),
951 "sthux $rS, $dst", LdStStoreUpd, []>,
952 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
953 PPC970_DGroup_Cracked;
954 def STWUX : XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memrr:$dst),
955 "stwux $rS, $dst", LdStStoreUpd, []>,
956 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
957 PPC970_DGroup_Cracked;
958 def STFSUX: XForm_8<31, 695, (outs ptr_rc_nor0:$ea_res), (ins F4RC:$rS, memrr:$dst),
959 "stfsux $rS, $dst", LdStSTFDU, []>,
960 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
961 PPC970_DGroup_Cracked;
962 def STFDUX: XForm_8<31, 759, (outs ptr_rc_nor0:$ea_res), (ins F8RC:$rS, memrr:$dst),
963 "stfdux $rS, $dst", LdStSTFDU, []>,
964 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
965 PPC970_DGroup_Cracked;
968 // Patterns to match the pre-inc stores. We can't put the patterns on
969 // the instruction definitions directly as ISel wants the address base
970 // and offset to be separate operands, not a single complex operand.
971 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
972 (STBUX $rS, $ptrreg, $ptroff)>;
973 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
974 (STHUX $rS, $ptrreg, $ptroff)>;
975 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
976 (STWUX $rS, $ptrreg, $ptroff)>;
977 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
978 (STFSUX $rS, $ptrreg, $ptroff)>;
979 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
980 (STFDUX $rS, $ptrreg, $ptroff)>;
982 def SYNC : XForm_24_sync<31, 598, (outs), (ins),
986 //===----------------------------------------------------------------------===//
987 // PPC32 Arithmetic Instructions.
990 let PPC970_Unit = 1 in { // FXU Operations.
991 def ADDI : DForm_2<14, (outs GPRC:$rD), (ins GPRC_NOR0:$rA, symbolLo:$imm),
992 "addi $rD, $rA, $imm", IntSimple,
993 [(set i32:$rD, (add i32:$rA, immSExt16:$imm))]>;
994 let Defs = [CARRY] in {
995 def ADDIC : DForm_2<12, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
996 "addic $rD, $rA, $imm", IntGeneral,
997 [(set i32:$rD, (addc i32:$rA, immSExt16:$imm))]>,
998 PPC970_DGroup_Cracked;
999 def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
1000 "addic. $rD, $rA, $imm", IntGeneral,
1003 def ADDIS : DForm_2<15, (outs GPRC:$rD), (ins GPRC_NOR0:$rA, symbolHi:$imm),
1004 "addis $rD, $rA, $imm", IntSimple,
1005 [(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>;
1006 let isCodeGenOnly = 1 in
1007 def LA : DForm_2<14, (outs GPRC:$rD), (ins GPRC_NOR0:$rA, symbolLo:$sym),
1008 "la $rD, $sym($rA)", IntGeneral,
1009 [(set i32:$rD, (add i32:$rA,
1010 (PPClo tglobaladdr:$sym, 0)))]>;
1011 def MULLI : DForm_2< 7, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
1012 "mulli $rD, $rA, $imm", IntMulLI,
1013 [(set i32:$rD, (mul i32:$rA, immSExt16:$imm))]>;
1014 let Defs = [CARRY] in {
1015 def SUBFIC : DForm_2< 8, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
1016 "subfic $rD, $rA, $imm", IntGeneral,
1017 [(set i32:$rD, (subc immSExt16:$imm, i32:$rA))]>;
1020 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
1021 def LI : DForm_2_r0<14, (outs GPRC:$rD), (ins symbolLo:$imm),
1022 "li $rD, $imm", IntSimple,
1023 [(set i32:$rD, immSExt16:$imm)]>;
1024 def LIS : DForm_2_r0<15, (outs GPRC:$rD), (ins symbolHi:$imm),
1025 "lis $rD, $imm", IntSimple,
1026 [(set i32:$rD, imm16ShiftedSExt:$imm)]>;
1030 let PPC970_Unit = 1 in { // FXU Operations.
1031 def ANDIo : DForm_4<28, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1032 "andi. $dst, $src1, $src2", IntGeneral,
1033 [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>,
1035 def ANDISo : DForm_4<29, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1036 "andis. $dst, $src1, $src2", IntGeneral,
1037 [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>,
1039 def ORI : DForm_4<24, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1040 "ori $dst, $src1, $src2", IntSimple,
1041 [(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>;
1042 def ORIS : DForm_4<25, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1043 "oris $dst, $src1, $src2", IntSimple,
1044 [(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>;
1045 def XORI : DForm_4<26, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1046 "xori $dst, $src1, $src2", IntSimple,
1047 [(set i32:$dst, (xor i32:$src1, immZExt16:$src2))]>;
1048 def XORIS : DForm_4<27, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1049 "xoris $dst, $src1, $src2", IntSimple,
1050 [(set i32:$dst, (xor i32:$src1, imm16ShiftedZExt:$src2))]>;
1051 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IntSimple,
1053 def CMPWI : DForm_5_ext<11, (outs CRRC:$crD), (ins GPRC:$rA, s16imm:$imm),
1054 "cmpwi $crD, $rA, $imm", IntCompare>;
1055 def CMPLWI : DForm_6_ext<10, (outs CRRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1056 "cmplwi $dst, $src1, $src2", IntCompare>;
1060 let PPC970_Unit = 1 in { // FXU Operations.
1061 def NAND : XForm_6<31, 476, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1062 "nand $rA, $rS, $rB", IntSimple,
1063 [(set i32:$rA, (not (and i32:$rS, i32:$rB)))]>;
1064 def AND : XForm_6<31, 28, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1065 "and $rA, $rS, $rB", IntSimple,
1066 [(set i32:$rA, (and i32:$rS, i32:$rB))]>;
1067 def ANDC : XForm_6<31, 60, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1068 "andc $rA, $rS, $rB", IntSimple,
1069 [(set i32:$rA, (and i32:$rS, (not i32:$rB)))]>;
1070 def OR : XForm_6<31, 444, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1071 "or $rA, $rS, $rB", IntSimple,
1072 [(set i32:$rA, (or i32:$rS, i32:$rB))]>;
1073 def NOR : XForm_6<31, 124, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1074 "nor $rA, $rS, $rB", IntSimple,
1075 [(set i32:$rA, (not (or i32:$rS, i32:$rB)))]>;
1076 def ORC : XForm_6<31, 412, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1077 "orc $rA, $rS, $rB", IntSimple,
1078 [(set i32:$rA, (or i32:$rS, (not i32:$rB)))]>;
1079 def EQV : XForm_6<31, 284, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1080 "eqv $rA, $rS, $rB", IntSimple,
1081 [(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>;
1082 def XOR : XForm_6<31, 316, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1083 "xor $rA, $rS, $rB", IntSimple,
1084 [(set i32:$rA, (xor i32:$rS, i32:$rB))]>;
1085 def SLW : XForm_6<31, 24, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1086 "slw $rA, $rS, $rB", IntGeneral,
1087 [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>;
1088 def SRW : XForm_6<31, 536, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1089 "srw $rA, $rS, $rB", IntGeneral,
1090 [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>;
1091 let Defs = [CARRY] in {
1092 def SRAW : XForm_6<31, 792, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1093 "sraw $rA, $rS, $rB", IntShift,
1094 [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>;
1098 let PPC970_Unit = 1 in { // FXU Operations.
1099 let Defs = [CARRY] in {
1100 def SRAWI : XForm_10<31, 824, (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH),
1101 "srawi $rA, $rS, $SH", IntShift,
1102 [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>;
1104 def CNTLZW : XForm_11<31, 26, (outs GPRC:$rA), (ins GPRC:$rS),
1105 "cntlzw $rA, $rS", IntGeneral,
1106 [(set i32:$rA, (ctlz i32:$rS))]>;
1107 def EXTSB : XForm_11<31, 954, (outs GPRC:$rA), (ins GPRC:$rS),
1108 "extsb $rA, $rS", IntSimple,
1109 [(set i32:$rA, (sext_inreg i32:$rS, i8))]>;
1110 def EXTSH : XForm_11<31, 922, (outs GPRC:$rA), (ins GPRC:$rS),
1111 "extsh $rA, $rS", IntSimple,
1112 [(set i32:$rA, (sext_inreg i32:$rS, i16))]>;
1114 def CMPW : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
1115 "cmpw $crD, $rA, $rB", IntCompare>;
1116 def CMPLW : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
1117 "cmplw $crD, $rA, $rB", IntCompare>;
1119 let PPC970_Unit = 3 in { // FPU Operations.
1120 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
1121 // "fcmpo $crD, $fA, $fB", FPCompare>;
1122 def FCMPUS : XForm_17<63, 0, (outs CRRC:$crD), (ins F4RC:$fA, F4RC:$fB),
1123 "fcmpu $crD, $fA, $fB", FPCompare>;
1124 def FCMPUD : XForm_17<63, 0, (outs CRRC:$crD), (ins F8RC:$fA, F8RC:$fB),
1125 "fcmpu $crD, $fA, $fB", FPCompare>;
1127 let Uses = [RM] in {
1128 def FCTIWZ : XForm_26<63, 15, (outs F8RC:$frD), (ins F8RC:$frB),
1129 "fctiwz $frD, $frB", FPGeneral,
1130 [(set f64:$frD, (PPCfctiwz f64:$frB))]>;
1131 def FRSP : XForm_26<63, 12, (outs F4RC:$frD), (ins F8RC:$frB),
1132 "frsp $frD, $frB", FPGeneral,
1133 [(set f32:$frD, (fround f64:$frB))]>;
1134 def FSQRT : XForm_26<63, 22, (outs F8RC:$frD), (ins F8RC:$frB),
1135 "fsqrt $frD, $frB", FPSqrt,
1136 [(set f64:$frD, (fsqrt f64:$frB))]>;
1137 def FSQRTS : XForm_26<59, 22, (outs F4RC:$frD), (ins F4RC:$frB),
1138 "fsqrts $frD, $frB", FPSqrt,
1139 [(set f32:$frD, (fsqrt f32:$frB))]>;
1143 /// Note that FMR is defined as pseudo-ops on the PPC970 because they are
1144 /// often coalesced away and we don't want the dispatch group builder to think
1145 /// that they will fill slots (which could cause the load of a LSU reject to
1146 /// sneak into a d-group with a store).
1147 def FMR : XForm_26<63, 72, (outs F4RC:$frD), (ins F4RC:$frB),
1148 "fmr $frD, $frB", FPGeneral,
1149 []>, // (set f32:$frD, f32:$frB)
1152 let PPC970_Unit = 3 in { // FPU Operations.
1153 // These are artificially split into two different forms, for 4/8 byte FP.
1154 def FABSS : XForm_26<63, 264, (outs F4RC:$frD), (ins F4RC:$frB),
1155 "fabs $frD, $frB", FPGeneral,
1156 [(set f32:$frD, (fabs f32:$frB))]>;
1157 def FABSD : XForm_26<63, 264, (outs F8RC:$frD), (ins F8RC:$frB),
1158 "fabs $frD, $frB", FPGeneral,
1159 [(set f64:$frD, (fabs f64:$frB))]>;
1160 def FNABSS : XForm_26<63, 136, (outs F4RC:$frD), (ins F4RC:$frB),
1161 "fnabs $frD, $frB", FPGeneral,
1162 [(set f32:$frD, (fneg (fabs f32:$frB)))]>;
1163 def FNABSD : XForm_26<63, 136, (outs F8RC:$frD), (ins F8RC:$frB),
1164 "fnabs $frD, $frB", FPGeneral,
1165 [(set f64:$frD, (fneg (fabs f64:$frB)))]>;
1166 def FNEGS : XForm_26<63, 40, (outs F4RC:$frD), (ins F4RC:$frB),
1167 "fneg $frD, $frB", FPGeneral,
1168 [(set f32:$frD, (fneg f32:$frB))]>;
1169 def FNEGD : XForm_26<63, 40, (outs F8RC:$frD), (ins F8RC:$frB),
1170 "fneg $frD, $frB", FPGeneral,
1171 [(set f64:$frD, (fneg f64:$frB))]>;
1175 // XL-Form instructions. condition register logical ops.
1177 def MCRF : XLForm_3<19, 0, (outs CRRC:$BF), (ins CRRC:$BFA),
1178 "mcrf $BF, $BFA", BrMCR>,
1179 PPC970_DGroup_First, PPC970_Unit_CRU;
1181 def CREQV : XLForm_1<19, 289, (outs CRBITRC:$CRD),
1182 (ins CRBITRC:$CRA, CRBITRC:$CRB),
1183 "creqv $CRD, $CRA, $CRB", BrCR,
1186 def CROR : XLForm_1<19, 449, (outs CRBITRC:$CRD),
1187 (ins CRBITRC:$CRA, CRBITRC:$CRB),
1188 "cror $CRD, $CRA, $CRB", BrCR,
1191 let isCodeGenOnly = 1 in {
1192 def CRSET : XLForm_1_ext<19, 289, (outs CRBITRC:$dst), (ins),
1193 "creqv $dst, $dst, $dst", BrCR,
1196 def CRUNSET: XLForm_1_ext<19, 193, (outs CRBITRC:$dst), (ins),
1197 "crxor $dst, $dst, $dst", BrCR,
1200 let Defs = [CR1EQ], CRD = 6 in {
1201 def CR6SET : XLForm_1_ext<19, 289, (outs), (ins),
1202 "creqv 6, 6, 6", BrCR,
1205 def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins),
1206 "crxor 6, 6, 6", BrCR,
1211 // XFX-Form instructions. Instructions that deal with SPRs.
1213 let Uses = [CTR] in {
1214 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs GPRC:$rT), (ins),
1215 "mfctr $rT", SprMFSPR>,
1216 PPC970_DGroup_First, PPC970_Unit_FXU;
1218 let Defs = [CTR], Pattern = [(PPCmtctr i32:$rS)] in {
1219 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins GPRC:$rS),
1220 "mtctr $rS", SprMTSPR>,
1221 PPC970_DGroup_First, PPC970_Unit_FXU;
1224 let Defs = [LR] in {
1225 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins GPRC:$rS),
1226 "mtlr $rS", SprMTSPR>,
1227 PPC970_DGroup_First, PPC970_Unit_FXU;
1229 let Uses = [LR] in {
1230 def MFLR : XFXForm_1_ext<31, 339, 8, (outs GPRC:$rT), (ins),
1231 "mflr $rT", SprMFSPR>,
1232 PPC970_DGroup_First, PPC970_Unit_FXU;
1235 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like
1236 // a GPR on the PPC970. As such, copies in and out have the same performance
1237 // characteristics as an OR instruction.
1238 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins GPRC:$rS),
1239 "mtspr 256, $rS", IntGeneral>,
1240 PPC970_DGroup_Single, PPC970_Unit_FXU;
1241 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs GPRC:$rT), (ins),
1242 "mfspr $rT, 256", IntGeneral>,
1243 PPC970_DGroup_First, PPC970_Unit_FXU;
1245 let isCodeGenOnly = 1 in {
1246 def MTVRSAVEv : XFXForm_7_ext<31, 467, 256,
1247 (outs VRSAVERC:$reg), (ins GPRC:$rS),
1248 "mtspr 256, $rS", IntGeneral>,
1249 PPC970_DGroup_Single, PPC970_Unit_FXU;
1250 def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs GPRC:$rT),
1251 (ins VRSAVERC:$reg),
1252 "mfspr $rT, 256", IntGeneral>,
1253 PPC970_DGroup_First, PPC970_Unit_FXU;
1256 // SPILL_VRSAVE - Indicate that we're dumping the VRSAVE register,
1257 // so we'll need to scavenge a register for it.
1259 def SPILL_VRSAVE : Pseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F),
1260 "#SPILL_VRSAVE", []>;
1262 // RESTORE_VRSAVE - Indicate that we're restoring the VRSAVE register (previously
1263 // spilled), so we'll need to scavenge a register for it.
1265 def RESTORE_VRSAVE : Pseudo<(outs VRSAVERC:$vrsave), (ins memri:$F),
1266 "#RESTORE_VRSAVE", []>;
1268 def MTCRF : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins GPRC:$rS),
1269 "mtcrf $FXM, $rS", BrMCRX>,
1270 PPC970_MicroCode, PPC970_Unit_CRU;
1272 // This is a pseudo for MFCR, which implicitly uses all 8 of its subregisters;
1273 // declaring that here gives the local register allocator problems with this:
1275 // MFCR <kill of whatever preg got assigned to vreg>
1276 // while not declaring it breaks DeadMachineInstructionElimination.
1277 // As it turns out, in all cases where we currently use this,
1278 // we're only interested in one subregister of it. Represent this in the
1279 // instruction to keep the register allocator from becoming confused.
1281 // FIXME: Make this a real Pseudo instruction when the JIT switches to MC.
1282 let isCodeGenOnly = 1 in
1283 def MFCRpseud: XFXForm_3<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM),
1284 "#MFCRpseud", SprMFCR>,
1285 PPC970_MicroCode, PPC970_Unit_CRU;
1287 def MFCR : XFXForm_3<31, 19, (outs GPRC:$rT), (ins),
1288 "mfcr $rT", SprMFCR>,
1289 PPC970_MicroCode, PPC970_Unit_CRU;
1291 def MFOCRF: XFXForm_5a<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM),
1292 "mfocrf $rT, $FXM", SprMFCR>,
1293 PPC970_DGroup_First, PPC970_Unit_CRU;
1295 // Pseudo instruction to perform FADD in round-to-zero mode.
1296 let usesCustomInserter = 1, Uses = [RM] in {
1297 def FADDrtz: Pseudo<(outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), "",
1298 [(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>;
1301 // The above pseudo gets expanded to make use of the following instructions
1302 // to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level.
1303 let Uses = [RM], Defs = [RM] in {
1304 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
1305 "mtfsb0 $FM", IntMTFSB0, []>,
1306 PPC970_DGroup_Single, PPC970_Unit_FPU;
1307 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
1308 "mtfsb1 $FM", IntMTFSB0, []>,
1309 PPC970_DGroup_Single, PPC970_Unit_FPU;
1310 def MTFSF : XFLForm<63, 711, (outs), (ins i32imm:$FM, F8RC:$rT),
1311 "mtfsf $FM, $rT", IntMTFSB0, []>,
1312 PPC970_DGroup_Single, PPC970_Unit_FPU;
1314 let Uses = [RM] in {
1315 def MFFS : XForm_42<63, 583, (outs F8RC:$rT), (ins),
1316 "mffs $rT", IntMFFS,
1317 [(set f64:$rT, (PPCmffs))]>,
1318 PPC970_DGroup_Single, PPC970_Unit_FPU;
1322 let PPC970_Unit = 1 in { // FXU Operations.
1324 // XO-Form instructions. Arithmetic instructions that can set overflow bit
1326 def ADD4 : XOForm_1<31, 266, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1327 "add $rT, $rA, $rB", IntSimple,
1328 [(set i32:$rT, (add i32:$rA, i32:$rB))]>;
1329 let Defs = [CARRY] in {
1330 def ADDC : XOForm_1<31, 10, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1331 "addc $rT, $rA, $rB", IntGeneral,
1332 [(set i32:$rT, (addc i32:$rA, i32:$rB))]>,
1333 PPC970_DGroup_Cracked;
1335 def DIVW : XOForm_1<31, 491, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1336 "divw $rT, $rA, $rB", IntDivW,
1337 [(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>,
1338 PPC970_DGroup_First, PPC970_DGroup_Cracked;
1339 def DIVWU : XOForm_1<31, 459, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1340 "divwu $rT, $rA, $rB", IntDivW,
1341 [(set i32:$rT, (udiv i32:$rA, i32:$rB))]>,
1342 PPC970_DGroup_First, PPC970_DGroup_Cracked;
1343 def MULHW : XOForm_1<31, 75, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1344 "mulhw $rT, $rA, $rB", IntMulHW,
1345 [(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>;
1346 def MULHWU : XOForm_1<31, 11, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1347 "mulhwu $rT, $rA, $rB", IntMulHWU,
1348 [(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>;
1349 def MULLW : XOForm_1<31, 235, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1350 "mullw $rT, $rA, $rB", IntMulHW,
1351 [(set i32:$rT, (mul i32:$rA, i32:$rB))]>;
1352 def SUBF : XOForm_1<31, 40, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1353 "subf $rT, $rA, $rB", IntGeneral,
1354 [(set i32:$rT, (sub i32:$rB, i32:$rA))]>;
1355 let Defs = [CARRY] in {
1356 def SUBFC : XOForm_1<31, 8, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1357 "subfc $rT, $rA, $rB", IntGeneral,
1358 [(set i32:$rT, (subc i32:$rB, i32:$rA))]>,
1359 PPC970_DGroup_Cracked;
1361 def NEG : XOForm_3<31, 104, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1362 "neg $rT, $rA", IntSimple,
1363 [(set i32:$rT, (ineg i32:$rA))]>;
1364 let Uses = [CARRY], Defs = [CARRY] in {
1365 def ADDE : XOForm_1<31, 138, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1366 "adde $rT, $rA, $rB", IntGeneral,
1367 [(set i32:$rT, (adde i32:$rA, i32:$rB))]>;
1368 def ADDME : XOForm_3<31, 234, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1369 "addme $rT, $rA", IntGeneral,
1370 [(set i32:$rT, (adde i32:$rA, -1))]>;
1371 def ADDZE : XOForm_3<31, 202, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1372 "addze $rT, $rA", IntGeneral,
1373 [(set i32:$rT, (adde i32:$rA, 0))]>;
1374 def SUBFE : XOForm_1<31, 136, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1375 "subfe $rT, $rA, $rB", IntGeneral,
1376 [(set i32:$rT, (sube i32:$rB, i32:$rA))]>;
1377 def SUBFME : XOForm_3<31, 232, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1378 "subfme $rT, $rA", IntGeneral,
1379 [(set i32:$rT, (sube -1, i32:$rA))]>;
1380 def SUBFZE : XOForm_3<31, 200, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1381 "subfze $rT, $rA", IntGeneral,
1382 [(set i32:$rT, (sube 0, i32:$rA))]>;
1386 // A-Form instructions. Most of the instructions executed in the FPU are of
1389 let PPC970_Unit = 3 in { // FPU Operations.
1390 let Uses = [RM] in {
1391 def FMADD : AForm_1<63, 29,
1392 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1393 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused,
1394 [(set f64:$FRT, (fma f64:$FRA, f64:$FRC, f64:$FRB))]>;
1395 def FMADDS : AForm_1<59, 29,
1396 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1397 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
1398 [(set f32:$FRT, (fma f32:$FRA, f32:$FRC, f32:$FRB))]>;
1399 def FMSUB : AForm_1<63, 28,
1400 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1401 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused,
1403 (fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>;
1404 def FMSUBS : AForm_1<59, 28,
1405 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1406 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
1408 (fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>;
1409 def FNMADD : AForm_1<63, 31,
1410 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1411 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused,
1413 (fneg (fma f64:$FRA, f64:$FRC, f64:$FRB)))]>;
1414 def FNMADDS : AForm_1<59, 31,
1415 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1416 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
1418 (fneg (fma f32:$FRA, f32:$FRC, f32:$FRB)))]>;
1419 def FNMSUB : AForm_1<63, 30,
1420 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1421 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused,
1422 [(set f64:$FRT, (fneg (fma f64:$FRA, f64:$FRC,
1423 (fneg f64:$FRB))))]>;
1424 def FNMSUBS : AForm_1<59, 30,
1425 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1426 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
1427 [(set f32:$FRT, (fneg (fma f32:$FRA, f32:$FRC,
1428 (fneg f32:$FRB))))]>;
1430 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
1431 // having 4 of these, force the comparison to always be an 8-byte double (code
1432 // should use an FMRSD if the input comparison value really wants to be a float)
1433 // and 4/8 byte forms for the result and operand type..
1434 def FSELD : AForm_1<63, 23,
1435 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1436 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
1437 [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>;
1438 def FSELS : AForm_1<63, 23,
1439 (outs F4RC:$FRT), (ins F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1440 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
1441 [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>;
1442 let Uses = [RM] in {
1443 def FADD : AForm_2<63, 21,
1444 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1445 "fadd $FRT, $FRA, $FRB", FPAddSub,
1446 [(set f64:$FRT, (fadd f64:$FRA, f64:$FRB))]>;
1447 def FADDS : AForm_2<59, 21,
1448 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1449 "fadds $FRT, $FRA, $FRB", FPGeneral,
1450 [(set f32:$FRT, (fadd f32:$FRA, f32:$FRB))]>;
1451 def FDIV : AForm_2<63, 18,
1452 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1453 "fdiv $FRT, $FRA, $FRB", FPDivD,
1454 [(set f64:$FRT, (fdiv f64:$FRA, f64:$FRB))]>;
1455 def FDIVS : AForm_2<59, 18,
1456 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1457 "fdivs $FRT, $FRA, $FRB", FPDivS,
1458 [(set f32:$FRT, (fdiv f32:$FRA, f32:$FRB))]>;
1459 def FMUL : AForm_3<63, 25,
1460 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC),
1461 "fmul $FRT, $FRA, $FRC", FPFused,
1462 [(set f64:$FRT, (fmul f64:$FRA, f64:$FRC))]>;
1463 def FMULS : AForm_3<59, 25,
1464 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC),
1465 "fmuls $FRT, $FRA, $FRC", FPGeneral,
1466 [(set f32:$FRT, (fmul f32:$FRA, f32:$FRC))]>;
1467 def FSUB : AForm_2<63, 20,
1468 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1469 "fsub $FRT, $FRA, $FRB", FPAddSub,
1470 [(set f64:$FRT, (fsub f64:$FRA, f64:$FRB))]>;
1471 def FSUBS : AForm_2<59, 20,
1472 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1473 "fsubs $FRT, $FRA, $FRB", FPGeneral,
1474 [(set f32:$FRT, (fsub f32:$FRA, f32:$FRB))]>;
1478 let PPC970_Unit = 1 in { // FXU Operations.
1479 def ISEL : AForm_4<31, 15,
1480 (outs GPRC:$rT), (ins GPRC_NOR0:$rA, GPRC:$rB, CRBITRC:$cond),
1481 "isel $rT, $rA, $rB, $cond", IntGeneral,
1485 let PPC970_Unit = 1 in { // FXU Operations.
1486 // M-Form instructions. rotate and mask instructions.
1488 let isCommutable = 1 in {
1489 // RLWIMI can be commuted if the rotate amount is zero.
1490 def RLWIMI : MForm_2<20,
1491 (outs GPRC:$rA), (ins GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
1492 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate,
1493 []>, PPC970_DGroup_Cracked, RegConstraint<"$rSi = $rA">,
1496 def RLWINM : MForm_2<21,
1497 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1498 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
1500 def RLWINMo : MForm_2<21,
1501 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1502 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
1503 []>, isDOT, PPC970_DGroup_Cracked;
1504 def RLWNM : MForm_2<23,
1505 (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
1506 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral,
1511 //===----------------------------------------------------------------------===//
1512 // PowerPC Instruction Patterns
1515 // Arbitrary immediate support. Implement in terms of LIS/ORI.
1516 def : Pat<(i32 imm:$imm),
1517 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
1519 // Implement the 'not' operation with the NOR instruction.
1520 def NOT : Pat<(not i32:$in),
1523 // ADD an arbitrary immediate.
1524 def : Pat<(add i32:$in, imm:$imm),
1525 (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
1526 // OR an arbitrary immediate.
1527 def : Pat<(or i32:$in, imm:$imm),
1528 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1529 // XOR an arbitrary immediate.
1530 def : Pat<(xor i32:$in, imm:$imm),
1531 (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1533 def : Pat<(sub immSExt16:$imm, i32:$in),
1534 (SUBFIC $in, imm:$imm)>;
1537 def : Pat<(shl i32:$in, (i32 imm:$imm)),
1538 (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>;
1539 def : Pat<(srl i32:$in, (i32 imm:$imm)),
1540 (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>;
1543 def : Pat<(rotl i32:$in, i32:$sh),
1544 (RLWNM $in, $sh, 0, 31)>;
1545 def : Pat<(rotl i32:$in, (i32 imm:$imm)),
1546 (RLWINM $in, imm:$imm, 0, 31)>;
1549 def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm),
1550 (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
1553 def : Pat<(PPCcall (i32 tglobaladdr:$dst)),
1554 (BL tglobaladdr:$dst)>;
1555 def : Pat<(PPCcall (i32 texternalsym:$dst)),
1556 (BL texternalsym:$dst)>;
1559 def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm),
1560 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
1562 def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
1563 (TCRETURNdi texternalsym:$dst, imm:$imm)>;
1565 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
1566 (TCRETURNri CTRRC:$dst, imm:$imm)>;
1570 // Hi and Lo for Darwin Global Addresses.
1571 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
1572 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
1573 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
1574 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
1575 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
1576 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
1577 def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>;
1578 def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>;
1579 def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in),
1580 (ADDIS $in, tglobaltlsaddr:$g)>;
1581 def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in),
1582 (ADDI $in, tglobaltlsaddr:$g)>;
1583 def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)),
1584 (ADDIS $in, tglobaladdr:$g)>;
1585 def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)),
1586 (ADDIS $in, tconstpool:$g)>;
1587 def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)),
1588 (ADDIS $in, tjumptable:$g)>;
1589 def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)),
1590 (ADDIS $in, tblockaddress:$g)>;
1592 // Standard shifts. These are represented separately from the real shifts above
1593 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
1595 def : Pat<(sra i32:$rS, i32:$rB),
1597 def : Pat<(srl i32:$rS, i32:$rB),
1599 def : Pat<(shl i32:$rS, i32:$rB),
1602 def : Pat<(zextloadi1 iaddr:$src),
1604 def : Pat<(zextloadi1 xaddr:$src),
1606 def : Pat<(extloadi1 iaddr:$src),
1608 def : Pat<(extloadi1 xaddr:$src),
1610 def : Pat<(extloadi8 iaddr:$src),
1612 def : Pat<(extloadi8 xaddr:$src),
1614 def : Pat<(extloadi16 iaddr:$src),
1616 def : Pat<(extloadi16 xaddr:$src),
1618 def : Pat<(f64 (extloadf32 iaddr:$src)),
1619 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
1620 def : Pat<(f64 (extloadf32 xaddr:$src)),
1621 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
1623 def : Pat<(f64 (fextend f32:$src)),
1624 (COPY_TO_REGCLASS $src, F8RC)>;
1627 def : Pat<(membarrier (i32 imm /*ll*/),
1631 (i32 imm /*device*/)),
1634 def : Pat<(atomic_fence (imm), (imm)), (SYNC)>;
1636 include "PPCInstrAltivec.td"
1637 include "PPCInstr64Bit.td"