1 //===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x
24 SDTCisVT<0, f64>, SDTCisPtrTy<1>
27 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
28 def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
30 def SDT_PPCvperm : SDTypeProfile<1, 3, [
31 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
34 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
35 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
38 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
39 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
42 def SDT_PPClbrx : SDTypeProfile<1, 2, [
43 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
45 def SDT_PPCstbrx : SDTypeProfile<0, 3, [
46 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
49 def SDT_PPClarx : SDTypeProfile<1, 1, [
50 SDTCisInt<0>, SDTCisPtrTy<1>
52 def SDT_PPCstcx : SDTypeProfile<0, 2, [
53 SDTCisInt<0>, SDTCisPtrTy<1>
56 def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
57 SDTCisPtrTy<0>, SDTCisVT<1, i32>
61 //===----------------------------------------------------------------------===//
62 // PowerPC specific DAG Nodes.
65 def PPCfre : SDNode<"PPCISD::FRE", SDTFPUnaryOp, []>;
66 def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>;
68 def PPCfcfid : SDNode<"PPCISD::FCFID", SDTFPUnaryOp, []>;
69 def PPCfcfidu : SDNode<"PPCISD::FCFIDU", SDTFPUnaryOp, []>;
70 def PPCfcfids : SDNode<"PPCISD::FCFIDS", SDTFPRoundOp, []>;
71 def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>;
72 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
73 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
74 def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>;
75 def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>;
76 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
77 [SDNPHasChain, SDNPMayStore]>;
78 def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx,
79 [SDNPHasChain, SDNPMayLoad]>;
80 def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx,
81 [SDNPHasChain, SDNPMayLoad]>;
83 // Extract FPSCR (not modeled at the DAG level).
84 def PPCmffs : SDNode<"PPCISD::MFFS",
85 SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, []>;
87 // Perform FADD in round-to-zero mode.
88 def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>;
91 def PPCfsel : SDNode<"PPCISD::FSEL",
92 // Type constraint for fsel.
93 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
94 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
96 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
97 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
98 def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, [SDNPMayLoad]>;
99 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
100 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
102 def PPCppc32GOT : SDNode<"PPCISD::PPC32_GOT", SDTIntLeaf, []>;
104 def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>;
105 def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp,
107 def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>;
108 def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>;
109 def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>;
110 def PPCgetTlsAddr : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>;
111 def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>;
112 def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>;
113 def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>;
114 def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp,
116 def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>;
118 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
120 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
121 // amounts. These nodes are generated by the multi-precision shift code.
122 def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>;
123 def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>;
124 def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>;
126 // These are target-independent nodes, but have target-specific formats.
127 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
128 [SDNPHasChain, SDNPOutGlue]>;
129 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd,
130 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
132 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
133 def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall,
134 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
136 def PPCcall_nop : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall,
137 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
139 def PPCload : SDNode<"PPCISD::LOAD", SDTypeProfile<1, 1, []>,
140 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
141 def PPCload_toc : SDNode<"PPCISD::LOAD_TOC", SDTypeProfile<0, 1, []>,
142 [SDNPHasChain, SDNPSideEffect,
143 SDNPInGlue, SDNPOutGlue]>;
144 def PPCtoc_restore : SDNode<"PPCISD::TOC_RESTORE", SDTypeProfile<0, 0, []>,
145 [SDNPHasChain, SDNPSideEffect,
146 SDNPInGlue, SDNPOutGlue]>;
147 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
148 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
149 def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone,
150 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
153 def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone,
154 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
156 def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
157 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
159 def PPCeh_sjlj_setjmp : SDNode<"PPCISD::EH_SJLJ_SETJMP",
160 SDTypeProfile<1, 1, [SDTCisInt<0>,
162 [SDNPHasChain, SDNPSideEffect]>;
163 def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP",
164 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
165 [SDNPHasChain, SDNPSideEffect]>;
167 def SDT_PPCsc : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
168 def PPCsc : SDNode<"PPCISD::SC", SDT_PPCsc,
169 [SDNPHasChain, SDNPSideEffect]>;
171 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
172 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>;
174 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
175 [SDNPHasChain, SDNPOptInGlue]>;
177 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
178 [SDNPHasChain, SDNPMayLoad]>;
179 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
180 [SDNPHasChain, SDNPMayStore]>;
182 // Instructions to set/unset CR bit 6 for SVR4 vararg calls
183 def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone,
184 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
185 def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone,
186 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
188 // Instructions to support atomic operations
189 def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx,
190 [SDNPHasChain, SDNPMayLoad]>;
191 def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx,
192 [SDNPHasChain, SDNPMayStore]>;
194 // Instructions to support medium and large code model
195 def PPCaddisTocHA : SDNode<"PPCISD::ADDIS_TOC_HA", SDTIntBinOp, []>;
196 def PPCldTocL : SDNode<"PPCISD::LD_TOC_L", SDTIntBinOp, [SDNPMayLoad]>;
197 def PPCaddiTocL : SDNode<"PPCISD::ADDI_TOC_L", SDTIntBinOp, []>;
200 // Instructions to support dynamic alloca.
201 def SDTDynOp : SDTypeProfile<1, 2, []>;
202 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
204 //===----------------------------------------------------------------------===//
205 // PowerPC specific transformation functions and pattern fragments.
208 def SHL32 : SDNodeXForm<imm, [{
209 // Transformation function: 31 - imm
210 return getI32Imm(31 - N->getZExtValue());
213 def SRL32 : SDNodeXForm<imm, [{
214 // Transformation function: 32 - imm
215 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0);
218 def LO16 : SDNodeXForm<imm, [{
219 // Transformation function: get the low 16 bits.
220 return getI32Imm((unsigned short)N->getZExtValue());
223 def HI16 : SDNodeXForm<imm, [{
224 // Transformation function: shift the immediate value down into the low bits.
225 return getI32Imm((unsigned)N->getZExtValue() >> 16);
228 def HA16 : SDNodeXForm<imm, [{
229 // Transformation function: shift the immediate value down into the low bits.
230 signed int Val = N->getZExtValue();
231 return getI32Imm((Val - (signed short)Val) >> 16);
233 def MB : SDNodeXForm<imm, [{
234 // Transformation function: get the start bit of a mask
236 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
237 return getI32Imm(mb);
240 def ME : SDNodeXForm<imm, [{
241 // Transformation function: get the end bit of a mask
243 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
244 return getI32Imm(me);
246 def maskimm32 : PatLeaf<(imm), [{
247 // maskImm predicate - True if immediate is a run of ones.
249 if (N->getValueType(0) == MVT::i32)
250 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
255 def imm32SExt16 : Operand<i32>, ImmLeaf<i32, [{
256 // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit
257 // sign extended field. Used by instructions like 'addi'.
258 return (int32_t)Imm == (short)Imm;
260 def imm64SExt16 : Operand<i64>, ImmLeaf<i64, [{
261 // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit
262 // sign extended field. Used by instructions like 'addi'.
263 return (int64_t)Imm == (short)Imm;
265 def immZExt16 : PatLeaf<(imm), [{
266 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
267 // field. Used by instructions like 'ori'.
268 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
271 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
272 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
273 // identical in 32-bit mode, but in 64-bit mode, they return true if the
274 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
276 def imm16ShiftedZExt : PatLeaf<(imm), [{
277 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
278 // immediate are set. Used by instructions like 'xoris'.
279 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
282 def imm16ShiftedSExt : PatLeaf<(imm), [{
283 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
284 // immediate are set. Used by instructions like 'addis'. Identical to
285 // imm16ShiftedZExt in 32-bit mode.
286 if (N->getZExtValue() & 0xFFFF) return false;
287 if (N->getValueType(0) == MVT::i32)
289 // For 64-bit, make sure it is sext right.
290 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
293 // Some r+i load/store instructions (such as LD, STD, LDU, etc.) that require
294 // restricted memrix (4-aligned) constants are alignment sensitive. If these
295 // offsets are hidden behind TOC entries than the values of the lower-order
296 // bits cannot be checked directly. As a result, we need to also incorporate
297 // an alignment check into the relevant patterns.
299 def aligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
300 return cast<LoadSDNode>(N)->getAlignment() >= 4;
302 def aligned4store : PatFrag<(ops node:$val, node:$ptr),
303 (store node:$val, node:$ptr), [{
304 return cast<StoreSDNode>(N)->getAlignment() >= 4;
306 def aligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
307 return cast<LoadSDNode>(N)->getAlignment() >= 4;
309 def aligned4pre_store : PatFrag<
310 (ops node:$val, node:$base, node:$offset),
311 (pre_store node:$val, node:$base, node:$offset), [{
312 return cast<StoreSDNode>(N)->getAlignment() >= 4;
315 def unaligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
316 return cast<LoadSDNode>(N)->getAlignment() < 4;
318 def unaligned4store : PatFrag<(ops node:$val, node:$ptr),
319 (store node:$val, node:$ptr), [{
320 return cast<StoreSDNode>(N)->getAlignment() < 4;
322 def unaligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
323 return cast<LoadSDNode>(N)->getAlignment() < 4;
326 //===----------------------------------------------------------------------===//
327 // PowerPC Flag Definitions.
329 class isPPC64 { bit PPC64 = 1; }
330 class isDOT { bit RC = 1; }
332 class RegConstraint<string C> {
333 string Constraints = C;
335 class NoEncode<string E> {
336 string DisableEncoding = E;
340 //===----------------------------------------------------------------------===//
341 // PowerPC Operand Definitions.
343 // In the default PowerPC assembler syntax, registers are specified simply
344 // by number, so they cannot be distinguished from immediate values (without
345 // looking at the opcode). This means that the default operand matching logic
346 // for the asm parser does not work, and we need to specify custom matchers.
347 // Since those can only be specified with RegisterOperand classes and not
348 // directly on the RegisterClass, all instructions patterns used by the asm
349 // parser need to use a RegisterOperand (instead of a RegisterClass) for
350 // all their register operands.
351 // For this purpose, we define one RegisterOperand for each RegisterClass,
352 // using the same name as the class, just in lower case.
354 def PPCRegGPRCAsmOperand : AsmOperandClass {
355 let Name = "RegGPRC"; let PredicateMethod = "isRegNumber";
357 def gprc : RegisterOperand<GPRC> {
358 let ParserMatchClass = PPCRegGPRCAsmOperand;
360 def PPCRegG8RCAsmOperand : AsmOperandClass {
361 let Name = "RegG8RC"; let PredicateMethod = "isRegNumber";
363 def g8rc : RegisterOperand<G8RC> {
364 let ParserMatchClass = PPCRegG8RCAsmOperand;
366 def PPCRegGPRCNoR0AsmOperand : AsmOperandClass {
367 let Name = "RegGPRCNoR0"; let PredicateMethod = "isRegNumber";
369 def gprc_nor0 : RegisterOperand<GPRC_NOR0> {
370 let ParserMatchClass = PPCRegGPRCNoR0AsmOperand;
372 def PPCRegG8RCNoX0AsmOperand : AsmOperandClass {
373 let Name = "RegG8RCNoX0"; let PredicateMethod = "isRegNumber";
375 def g8rc_nox0 : RegisterOperand<G8RC_NOX0> {
376 let ParserMatchClass = PPCRegG8RCNoX0AsmOperand;
378 def PPCRegF8RCAsmOperand : AsmOperandClass {
379 let Name = "RegF8RC"; let PredicateMethod = "isRegNumber";
381 def f8rc : RegisterOperand<F8RC> {
382 let ParserMatchClass = PPCRegF8RCAsmOperand;
384 def PPCRegF4RCAsmOperand : AsmOperandClass {
385 let Name = "RegF4RC"; let PredicateMethod = "isRegNumber";
387 def f4rc : RegisterOperand<F4RC> {
388 let ParserMatchClass = PPCRegF4RCAsmOperand;
390 def PPCRegVRRCAsmOperand : AsmOperandClass {
391 let Name = "RegVRRC"; let PredicateMethod = "isRegNumber";
393 def vrrc : RegisterOperand<VRRC> {
394 let ParserMatchClass = PPCRegVRRCAsmOperand;
396 def PPCRegCRBITRCAsmOperand : AsmOperandClass {
397 let Name = "RegCRBITRC"; let PredicateMethod = "isCRBitNumber";
399 def crbitrc : RegisterOperand<CRBITRC> {
400 let ParserMatchClass = PPCRegCRBITRCAsmOperand;
402 def PPCRegCRRCAsmOperand : AsmOperandClass {
403 let Name = "RegCRRC"; let PredicateMethod = "isCCRegNumber";
405 def crrc : RegisterOperand<CRRC> {
406 let ParserMatchClass = PPCRegCRRCAsmOperand;
409 def PPCS5ImmAsmOperand : AsmOperandClass {
410 let Name = "S5Imm"; let PredicateMethod = "isS5Imm";
411 let RenderMethod = "addImmOperands";
413 def s5imm : Operand<i32> {
414 let PrintMethod = "printS5ImmOperand";
415 let ParserMatchClass = PPCS5ImmAsmOperand;
416 let DecoderMethod = "decodeSImmOperand<5>";
418 def PPCU5ImmAsmOperand : AsmOperandClass {
419 let Name = "U5Imm"; let PredicateMethod = "isU5Imm";
420 let RenderMethod = "addImmOperands";
422 def u5imm : Operand<i32> {
423 let PrintMethod = "printU5ImmOperand";
424 let ParserMatchClass = PPCU5ImmAsmOperand;
425 let DecoderMethod = "decodeUImmOperand<5>";
427 def PPCU6ImmAsmOperand : AsmOperandClass {
428 let Name = "U6Imm"; let PredicateMethod = "isU6Imm";
429 let RenderMethod = "addImmOperands";
431 def u6imm : Operand<i32> {
432 let PrintMethod = "printU6ImmOperand";
433 let ParserMatchClass = PPCU6ImmAsmOperand;
434 let DecoderMethod = "decodeUImmOperand<6>";
436 def PPCS16ImmAsmOperand : AsmOperandClass {
437 let Name = "S16Imm"; let PredicateMethod = "isS16Imm";
438 let RenderMethod = "addImmOperands";
440 def s16imm : Operand<i32> {
441 let PrintMethod = "printS16ImmOperand";
442 let EncoderMethod = "getImm16Encoding";
443 let ParserMatchClass = PPCS16ImmAsmOperand;
444 let DecoderMethod = "decodeSImmOperand<16>";
446 def PPCU16ImmAsmOperand : AsmOperandClass {
447 let Name = "U16Imm"; let PredicateMethod = "isU16Imm";
448 let RenderMethod = "addImmOperands";
450 def u16imm : Operand<i32> {
451 let PrintMethod = "printU16ImmOperand";
452 let EncoderMethod = "getImm16Encoding";
453 let ParserMatchClass = PPCU16ImmAsmOperand;
454 let DecoderMethod = "decodeUImmOperand<16>";
456 def PPCS17ImmAsmOperand : AsmOperandClass {
457 let Name = "S17Imm"; let PredicateMethod = "isS17Imm";
458 let RenderMethod = "addImmOperands";
460 def s17imm : Operand<i32> {
461 // This operand type is used for addis/lis to allow the assembler parser
462 // to accept immediates in the range -65536..65535 for compatibility with
463 // the GNU assembler. The operand is treated as 16-bit otherwise.
464 let PrintMethod = "printS16ImmOperand";
465 let EncoderMethod = "getImm16Encoding";
466 let ParserMatchClass = PPCS17ImmAsmOperand;
467 let DecoderMethod = "decodeSImmOperand<16>";
469 def PPCDirectBrAsmOperand : AsmOperandClass {
470 let Name = "DirectBr"; let PredicateMethod = "isDirectBr";
471 let RenderMethod = "addBranchTargetOperands";
473 def directbrtarget : Operand<OtherVT> {
474 let PrintMethod = "printBranchOperand";
475 let EncoderMethod = "getDirectBrEncoding";
476 let ParserMatchClass = PPCDirectBrAsmOperand;
478 def absdirectbrtarget : Operand<OtherVT> {
479 let PrintMethod = "printAbsBranchOperand";
480 let EncoderMethod = "getAbsDirectBrEncoding";
481 let ParserMatchClass = PPCDirectBrAsmOperand;
483 def PPCCondBrAsmOperand : AsmOperandClass {
484 let Name = "CondBr"; let PredicateMethod = "isCondBr";
485 let RenderMethod = "addBranchTargetOperands";
487 def condbrtarget : Operand<OtherVT> {
488 let PrintMethod = "printBranchOperand";
489 let EncoderMethod = "getCondBrEncoding";
490 let ParserMatchClass = PPCCondBrAsmOperand;
492 def abscondbrtarget : Operand<OtherVT> {
493 let PrintMethod = "printAbsBranchOperand";
494 let EncoderMethod = "getAbsCondBrEncoding";
495 let ParserMatchClass = PPCCondBrAsmOperand;
497 def calltarget : Operand<iPTR> {
498 let PrintMethod = "printBranchOperand";
499 let EncoderMethod = "getDirectBrEncoding";
500 let ParserMatchClass = PPCDirectBrAsmOperand;
502 def abscalltarget : Operand<iPTR> {
503 let PrintMethod = "printAbsBranchOperand";
504 let EncoderMethod = "getAbsDirectBrEncoding";
505 let ParserMatchClass = PPCDirectBrAsmOperand;
507 def PPCCRBitMaskOperand : AsmOperandClass {
508 let Name = "CRBitMask"; let PredicateMethod = "isCRBitMask";
510 def crbitm: Operand<i8> {
511 let PrintMethod = "printcrbitm";
512 let EncoderMethod = "get_crbitm_encoding";
513 let DecoderMethod = "decodeCRBitMOperand";
514 let ParserMatchClass = PPCCRBitMaskOperand;
517 // A version of ptr_rc which excludes R0 (or X0 in 64-bit mode).
518 def PPCRegGxRCNoR0Operand : AsmOperandClass {
519 let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber";
521 def ptr_rc_nor0 : Operand<iPTR>, PointerLikeRegClass<1> {
522 let ParserMatchClass = PPCRegGxRCNoR0Operand;
524 // A version of ptr_rc usable with the asm parser.
525 def PPCRegGxRCOperand : AsmOperandClass {
526 let Name = "RegGxRC"; let PredicateMethod = "isRegNumber";
528 def ptr_rc_idx : Operand<iPTR>, PointerLikeRegClass<0> {
529 let ParserMatchClass = PPCRegGxRCOperand;
532 def PPCDispRIOperand : AsmOperandClass {
533 let Name = "DispRI"; let PredicateMethod = "isS16Imm";
534 let RenderMethod = "addImmOperands";
536 def dispRI : Operand<iPTR> {
537 let ParserMatchClass = PPCDispRIOperand;
539 def PPCDispRIXOperand : AsmOperandClass {
540 let Name = "DispRIX"; let PredicateMethod = "isS16ImmX4";
541 let RenderMethod = "addImmOperands";
543 def dispRIX : Operand<iPTR> {
544 let ParserMatchClass = PPCDispRIXOperand;
547 def memri : Operand<iPTR> {
548 let PrintMethod = "printMemRegImm";
549 let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg);
550 let EncoderMethod = "getMemRIEncoding";
551 let DecoderMethod = "decodeMemRIOperands";
553 def memrr : Operand<iPTR> {
554 let PrintMethod = "printMemRegReg";
555 let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc_idx:$offreg);
557 def memrix : Operand<iPTR> { // memri where the imm is 4-aligned.
558 let PrintMethod = "printMemRegImm";
559 let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg);
560 let EncoderMethod = "getMemRIXEncoding";
561 let DecoderMethod = "decodeMemRIXOperands";
564 // A single-register address. This is used with the SjLj
565 // pseudo-instructions.
566 def memr : Operand<iPTR> {
567 let MIOperandInfo = (ops ptr_rc:$ptrreg);
569 def PPCTLSRegOperand : AsmOperandClass {
570 let Name = "TLSReg"; let PredicateMethod = "isTLSReg";
571 let RenderMethod = "addTLSRegOperands";
573 def tlsreg32 : Operand<i32> {
574 let EncoderMethod = "getTLSRegEncoding";
575 let ParserMatchClass = PPCTLSRegOperand;
578 // PowerPC Predicate operand.
579 def pred : Operand<OtherVT> {
580 let PrintMethod = "printPredicateOperand";
581 let MIOperandInfo = (ops i32imm:$bibo, crrc:$reg);
584 // Define PowerPC specific addressing mode.
585 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
586 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
587 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
588 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmX4", [], []>; // "std"
590 // The address in a single register. This is used with the SjLj
591 // pseudo-instructions.
592 def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>;
594 /// This is just the offset part of iaddr, used for preinc.
595 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
597 //===----------------------------------------------------------------------===//
598 // PowerPC Instruction Predicate Definitions.
599 def In32BitMode : Predicate<"!PPCSubTarget.isPPC64()">;
600 def In64BitMode : Predicate<"PPCSubTarget.isPPC64()">;
601 def IsBookE : Predicate<"PPCSubTarget.isBookE()">;
602 def IsNotBookE : Predicate<"!PPCSubTarget.isBookE()">;
604 //===----------------------------------------------------------------------===//
605 // PowerPC Multiclass Definitions.
607 multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
608 string asmbase, string asmstr, InstrItinClass itin,
610 let BaseName = asmbase in {
611 def NAME : XForm_6<opcode, xo, OOL, IOL,
612 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
613 pattern>, RecFormRel;
615 def o : XForm_6<opcode, xo, OOL, IOL,
616 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
617 []>, isDOT, RecFormRel;
621 multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
622 string asmbase, string asmstr, InstrItinClass itin,
624 let BaseName = asmbase in {
625 let Defs = [CARRY] in
626 def NAME : XForm_6<opcode, xo, OOL, IOL,
627 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
628 pattern>, RecFormRel;
629 let Defs = [CARRY, CR0] in
630 def o : XForm_6<opcode, xo, OOL, IOL,
631 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
632 []>, isDOT, RecFormRel;
636 multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
637 string asmbase, string asmstr, InstrItinClass itin,
639 let BaseName = asmbase in {
640 let Defs = [CARRY] in
641 def NAME : XForm_10<opcode, xo, OOL, IOL,
642 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
643 pattern>, RecFormRel;
644 let Defs = [CARRY, CR0] in
645 def o : XForm_10<opcode, xo, OOL, IOL,
646 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
647 []>, isDOT, RecFormRel;
651 multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
652 string asmbase, string asmstr, InstrItinClass itin,
654 let BaseName = asmbase in {
655 def NAME : XForm_11<opcode, xo, OOL, IOL,
656 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
657 pattern>, RecFormRel;
659 def o : XForm_11<opcode, xo, OOL, IOL,
660 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
661 []>, isDOT, RecFormRel;
665 multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
666 string asmbase, string asmstr, InstrItinClass itin,
668 let BaseName = asmbase in {
669 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
670 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
671 pattern>, RecFormRel;
673 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
674 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
675 []>, isDOT, RecFormRel;
679 multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
680 string asmbase, string asmstr, InstrItinClass itin,
682 let BaseName = asmbase in {
683 let Defs = [CARRY] in
684 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
685 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
686 pattern>, RecFormRel;
687 let Defs = [CARRY, CR0] in
688 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
689 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
690 []>, isDOT, RecFormRel;
694 multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
695 string asmbase, string asmstr, InstrItinClass itin,
697 let BaseName = asmbase in {
698 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
699 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
700 pattern>, RecFormRel;
702 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
703 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
704 []>, isDOT, RecFormRel;
708 multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
709 string asmbase, string asmstr, InstrItinClass itin,
711 let BaseName = asmbase in {
712 let Defs = [CARRY] in
713 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
714 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
715 pattern>, RecFormRel;
716 let Defs = [CARRY, CR0] in
717 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
718 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
719 []>, isDOT, RecFormRel;
723 multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL,
724 string asmbase, string asmstr, InstrItinClass itin,
726 let BaseName = asmbase in {
727 def NAME : MForm_2<opcode, OOL, IOL,
728 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
729 pattern>, RecFormRel;
731 def o : MForm_2<opcode, OOL, IOL,
732 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
733 []>, isDOT, RecFormRel;
737 multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
738 string asmbase, string asmstr, InstrItinClass itin,
740 let BaseName = asmbase in {
741 def NAME : MDForm_1<opcode, xo, OOL, IOL,
742 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
743 pattern>, RecFormRel;
745 def o : MDForm_1<opcode, xo, OOL, IOL,
746 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
747 []>, isDOT, RecFormRel;
751 multiclass MDSForm_1r<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
752 string asmbase, string asmstr, InstrItinClass itin,
754 let BaseName = asmbase in {
755 def NAME : MDSForm_1<opcode, xo, OOL, IOL,
756 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
757 pattern>, RecFormRel;
759 def o : MDSForm_1<opcode, xo, OOL, IOL,
760 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
761 []>, isDOT, RecFormRel;
765 multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
766 string asmbase, string asmstr, InstrItinClass itin,
768 let BaseName = asmbase in {
769 let Defs = [CARRY] in
770 def NAME : XSForm_1<opcode, xo, OOL, IOL,
771 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
772 pattern>, RecFormRel;
773 let Defs = [CARRY, CR0] in
774 def o : XSForm_1<opcode, xo, OOL, IOL,
775 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
776 []>, isDOT, RecFormRel;
780 multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
781 string asmbase, string asmstr, InstrItinClass itin,
783 let BaseName = asmbase in {
784 def NAME : XForm_26<opcode, xo, OOL, IOL,
785 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
786 pattern>, RecFormRel;
788 def o : XForm_26<opcode, xo, OOL, IOL,
789 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
790 []>, isDOT, RecFormRel;
794 multiclass XForm_28r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
795 string asmbase, string asmstr, InstrItinClass itin,
797 let BaseName = asmbase in {
798 def NAME : XForm_28<opcode, xo, OOL, IOL,
799 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
800 pattern>, RecFormRel;
802 def o : XForm_28<opcode, xo, OOL, IOL,
803 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
804 []>, isDOT, RecFormRel;
808 multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
809 string asmbase, string asmstr, InstrItinClass itin,
811 let BaseName = asmbase in {
812 def NAME : AForm_1<opcode, xo, OOL, IOL,
813 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
814 pattern>, RecFormRel;
816 def o : AForm_1<opcode, xo, OOL, IOL,
817 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
818 []>, isDOT, RecFormRel;
822 multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
823 string asmbase, string asmstr, InstrItinClass itin,
825 let BaseName = asmbase in {
826 def NAME : AForm_2<opcode, xo, OOL, IOL,
827 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
828 pattern>, RecFormRel;
830 def o : AForm_2<opcode, xo, OOL, IOL,
831 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
832 []>, isDOT, RecFormRel;
836 multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
837 string asmbase, string asmstr, InstrItinClass itin,
839 let BaseName = asmbase in {
840 def NAME : AForm_3<opcode, xo, OOL, IOL,
841 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
842 pattern>, RecFormRel;
844 def o : AForm_3<opcode, xo, OOL, IOL,
845 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
846 []>, isDOT, RecFormRel;
850 //===----------------------------------------------------------------------===//
851 // PowerPC Instruction Definitions.
853 // Pseudo-instructions:
855 let hasCtrlDep = 1 in {
856 let Defs = [R1], Uses = [R1] in {
857 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt",
858 [(callseq_start timm:$amt)]>;
859 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt2",
860 [(callseq_end timm:$amt1, timm:$amt2)]>;
863 def UPDATE_VRSAVE : Pseudo<(outs gprc:$rD), (ins gprc:$rS),
864 "UPDATE_VRSAVE $rD, $rS", []>;
867 let Defs = [R1], Uses = [R1] in
868 def DYNALLOC : Pseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC",
870 (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>;
872 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
873 // instruction selection into a branch sequence.
874 let usesCustomInserter = 1, // Expanded after instruction selection.
875 PPC970_Single = 1 in {
876 // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes
877 // because either operand might become the first operand in an isel, and
878 // that operand cannot be r0.
879 def SELECT_CC_I4 : Pseudo<(outs gprc:$dst), (ins crrc:$cond,
880 gprc_nor0:$T, gprc_nor0:$F,
881 i32imm:$BROPC), "#SELECT_CC_I4",
883 def SELECT_CC_I8 : Pseudo<(outs g8rc:$dst), (ins crrc:$cond,
884 g8rc_nox0:$T, g8rc_nox0:$F,
885 i32imm:$BROPC), "#SELECT_CC_I8",
887 def SELECT_CC_F4 : Pseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F,
888 i32imm:$BROPC), "#SELECT_CC_F4",
890 def SELECT_CC_F8 : Pseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F,
891 i32imm:$BROPC), "#SELECT_CC_F8",
893 def SELECT_CC_VRRC: Pseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F,
894 i32imm:$BROPC), "#SELECT_CC_VRRC",
898 // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
899 // scavenge a register for it.
901 def SPILL_CR : Pseudo<(outs), (ins crrc:$cond, memri:$F),
904 // RESTORE_CR - Indicate that we're restoring the CR register (previously
905 // spilled), so we'll need to scavenge a register for it.
907 def RESTORE_CR : Pseudo<(outs crrc:$cond), (ins memri:$F),
910 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
911 let isReturn = 1, Uses = [LR, RM] in
912 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB,
914 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in {
915 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
918 let isCodeGenOnly = 1 in
919 def BCCTR : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
920 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB,
926 def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>,
929 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
930 let isBarrier = 1 in {
931 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst),
934 def BA : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$dst),
935 "ba $dst", IIC_BrB, []>;
938 // BCC represents an arbitrary conditional branch on a predicate.
939 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
940 // a two-value operand where a dag node expects two operands. :(
941 let isCodeGenOnly = 1 in {
942 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst),
943 "b${cond:cc}${cond:pm} ${cond:reg}, $dst"
944 /*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$dst)]*/>;
945 def BCCA : BForm<16, 1, 0, (outs), (ins pred:$cond, abscondbrtarget:$dst),
946 "b${cond:cc}a${cond:pm} ${cond:reg}, $dst">;
948 let isReturn = 1, Uses = [LR, RM] in
949 def BCLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$cond),
950 "b${cond:cc}lr${cond:pm} ${cond:reg}", IIC_BrB, []>;
953 let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in {
954 def BDZLR : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
955 "bdzlr", IIC_BrB, []>;
956 def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
957 "bdnzlr", IIC_BrB, []>;
958 def BDZLRp : XLForm_2_ext<19, 16, 27, 0, 0, (outs), (ins),
959 "bdzlr+", IIC_BrB, []>;
960 def BDNZLRp: XLForm_2_ext<19, 16, 25, 0, 0, (outs), (ins),
961 "bdnzlr+", IIC_BrB, []>;
962 def BDZLRm : XLForm_2_ext<19, 16, 26, 0, 0, (outs), (ins),
963 "bdzlr-", IIC_BrB, []>;
964 def BDNZLRm: XLForm_2_ext<19, 16, 24, 0, 0, (outs), (ins),
965 "bdnzlr-", IIC_BrB, []>;
968 let Defs = [CTR], Uses = [CTR] in {
969 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
971 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
973 def BDZA : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$dst),
975 def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$dst),
977 def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$dst),
979 def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$dst),
981 def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$dst),
983 def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$dst),
985 def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$dst),
987 def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$dst),
989 def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$dst),
991 def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$dst),
996 // The unconditional BCL used by the SjLj setjmp code.
997 let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7 in {
998 let Defs = [LR], Uses = [RM] in {
999 def BCLalways : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst),
1000 "bcl 20, 31, $dst">;
1004 let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
1005 // Convenient aliases for call instructions
1006 let Uses = [RM] in {
1007 def BL : IForm<18, 0, 1, (outs), (ins calltarget:$func),
1008 "bl $func", IIC_BrB, []>; // See Pat patterns below.
1009 def BLA : IForm<18, 1, 1, (outs), (ins abscalltarget:$func),
1010 "bla $func", IIC_BrB, [(PPCcall (i32 imm:$func))]>;
1012 let isCodeGenOnly = 1 in {
1013 def BCCL : BForm<16, 0, 1, (outs), (ins pred:$cond, condbrtarget:$dst),
1014 "b${cond:cc}l${cond:pm} ${cond:reg}, $dst">;
1015 def BCCLA : BForm<16, 1, 1, (outs), (ins pred:$cond, abscondbrtarget:$dst),
1016 "b${cond:cc}la${cond:pm} ${cond:reg}, $dst">;
1019 let Uses = [CTR, RM] in {
1020 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
1021 "bctrl", IIC_BrB, [(PPCbctrl)]>,
1022 Requires<[In32BitMode]>;
1024 let isCodeGenOnly = 1 in
1025 def BCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
1026 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB,
1029 let Uses = [LR, RM] in {
1030 def BLRL : XLForm_2_ext<19, 16, 20, 0, 1, (outs), (ins),
1031 "blrl", IIC_BrB, []>;
1033 let isCodeGenOnly = 1 in
1034 def BCLRL : XLForm_2_br<19, 16, 1, (outs), (ins pred:$cond),
1035 "b${cond:cc}lrl${cond:pm} ${cond:reg}", IIC_BrB,
1038 let Defs = [CTR], Uses = [CTR, RM] in {
1039 def BDZL : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$dst),
1041 def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$dst),
1043 def BDZLA : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$dst),
1045 def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$dst),
1047 def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$dst),
1049 def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$dst),
1051 def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$dst),
1053 def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$dst),
1055 def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$dst),
1057 def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$dst),
1059 def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$dst),
1061 def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$dst),
1064 let Defs = [CTR], Uses = [CTR, LR, RM] in {
1065 def BDZLRL : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins),
1066 "bdzlrl", IIC_BrB, []>;
1067 def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins),
1068 "bdnzlrl", IIC_BrB, []>;
1069 def BDZLRLp : XLForm_2_ext<19, 16, 27, 0, 1, (outs), (ins),
1070 "bdzlrl+", IIC_BrB, []>;
1071 def BDNZLRLp: XLForm_2_ext<19, 16, 25, 0, 1, (outs), (ins),
1072 "bdnzlrl+", IIC_BrB, []>;
1073 def BDZLRLm : XLForm_2_ext<19, 16, 26, 0, 1, (outs), (ins),
1074 "bdzlrl-", IIC_BrB, []>;
1075 def BDNZLRLm: XLForm_2_ext<19, 16, 24, 0, 1, (outs), (ins),
1076 "bdnzlrl-", IIC_BrB, []>;
1080 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1081 def TCRETURNdi :Pseudo< (outs),
1082 (ins calltarget:$dst, i32imm:$offset),
1083 "#TC_RETURNd $dst $offset",
1087 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1088 def TCRETURNai :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
1089 "#TC_RETURNa $func $offset",
1090 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
1092 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1093 def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset),
1094 "#TC_RETURNr $dst $offset",
1098 let isCodeGenOnly = 1 in {
1100 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
1101 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in
1102 def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
1103 []>, Requires<[In32BitMode]>;
1105 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1106 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1107 def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
1111 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1112 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1113 def TAILBA : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst),
1119 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
1121 def EH_SjLj_SetJmp32 : Pseudo<(outs gprc:$dst), (ins memr:$buf),
1122 "#EH_SJLJ_SETJMP32",
1123 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
1124 Requires<[In32BitMode]>;
1125 let isTerminator = 1 in
1126 def EH_SjLj_LongJmp32 : Pseudo<(outs), (ins memr:$buf),
1127 "#EH_SJLJ_LONGJMP32",
1128 [(PPCeh_sjlj_longjmp addr:$buf)]>,
1129 Requires<[In32BitMode]>;
1132 let isBranch = 1, isTerminator = 1 in {
1133 def EH_SjLj_Setup : Pseudo<(outs), (ins directbrtarget:$dst),
1134 "#EH_SjLj_Setup\t$dst", []>;
1138 let PPC970_Unit = 7 in {
1139 def SC : SCForm<17, 1, (outs), (ins i32imm:$lev),
1140 "sc $lev", IIC_BrB, [(PPCsc (i32 imm:$lev))]>;
1143 // DCB* instructions.
1144 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst), "dcba $dst",
1145 IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
1146 PPC970_DGroup_Single;
1147 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst), "dcbf $dst",
1148 IIC_LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
1149 PPC970_DGroup_Single;
1150 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst), "dcbi $dst",
1151 IIC_LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
1152 PPC970_DGroup_Single;
1153 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst), "dcbst $dst",
1154 IIC_LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
1155 PPC970_DGroup_Single;
1156 def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst), "dcbt $dst",
1157 IIC_LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
1158 PPC970_DGroup_Single;
1159 def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst), "dcbtst $dst",
1160 IIC_LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
1161 PPC970_DGroup_Single;
1162 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst), "dcbz $dst",
1163 IIC_LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
1164 PPC970_DGroup_Single;
1165 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), "dcbzl $dst",
1166 IIC_LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
1167 PPC970_DGroup_Single;
1169 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
1170 (DCBT xoaddr:$dst)>;
1172 // Atomic operations
1173 let usesCustomInserter = 1 in {
1174 let Defs = [CR0] in {
1175 def ATOMIC_LOAD_ADD_I8 : Pseudo<
1176 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I8",
1177 [(set i32:$dst, (atomic_load_add_8 xoaddr:$ptr, i32:$incr))]>;
1178 def ATOMIC_LOAD_SUB_I8 : Pseudo<
1179 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I8",
1180 [(set i32:$dst, (atomic_load_sub_8 xoaddr:$ptr, i32:$incr))]>;
1181 def ATOMIC_LOAD_AND_I8 : Pseudo<
1182 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I8",
1183 [(set i32:$dst, (atomic_load_and_8 xoaddr:$ptr, i32:$incr))]>;
1184 def ATOMIC_LOAD_OR_I8 : Pseudo<
1185 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I8",
1186 [(set i32:$dst, (atomic_load_or_8 xoaddr:$ptr, i32:$incr))]>;
1187 def ATOMIC_LOAD_XOR_I8 : Pseudo<
1188 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "ATOMIC_LOAD_XOR_I8",
1189 [(set i32:$dst, (atomic_load_xor_8 xoaddr:$ptr, i32:$incr))]>;
1190 def ATOMIC_LOAD_NAND_I8 : Pseudo<
1191 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8",
1192 [(set i32:$dst, (atomic_load_nand_8 xoaddr:$ptr, i32:$incr))]>;
1193 def ATOMIC_LOAD_ADD_I16 : Pseudo<
1194 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16",
1195 [(set i32:$dst, (atomic_load_add_16 xoaddr:$ptr, i32:$incr))]>;
1196 def ATOMIC_LOAD_SUB_I16 : Pseudo<
1197 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I16",
1198 [(set i32:$dst, (atomic_load_sub_16 xoaddr:$ptr, i32:$incr))]>;
1199 def ATOMIC_LOAD_AND_I16 : Pseudo<
1200 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I16",
1201 [(set i32:$dst, (atomic_load_and_16 xoaddr:$ptr, i32:$incr))]>;
1202 def ATOMIC_LOAD_OR_I16 : Pseudo<
1203 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I16",
1204 [(set i32:$dst, (atomic_load_or_16 xoaddr:$ptr, i32:$incr))]>;
1205 def ATOMIC_LOAD_XOR_I16 : Pseudo<
1206 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I16",
1207 [(set i32:$dst, (atomic_load_xor_16 xoaddr:$ptr, i32:$incr))]>;
1208 def ATOMIC_LOAD_NAND_I16 : Pseudo<
1209 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I16",
1210 [(set i32:$dst, (atomic_load_nand_16 xoaddr:$ptr, i32:$incr))]>;
1211 def ATOMIC_LOAD_ADD_I32 : Pseudo<
1212 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I32",
1213 [(set i32:$dst, (atomic_load_add_32 xoaddr:$ptr, i32:$incr))]>;
1214 def ATOMIC_LOAD_SUB_I32 : Pseudo<
1215 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I32",
1216 [(set i32:$dst, (atomic_load_sub_32 xoaddr:$ptr, i32:$incr))]>;
1217 def ATOMIC_LOAD_AND_I32 : Pseudo<
1218 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I32",
1219 [(set i32:$dst, (atomic_load_and_32 xoaddr:$ptr, i32:$incr))]>;
1220 def ATOMIC_LOAD_OR_I32 : Pseudo<
1221 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I32",
1222 [(set i32:$dst, (atomic_load_or_32 xoaddr:$ptr, i32:$incr))]>;
1223 def ATOMIC_LOAD_XOR_I32 : Pseudo<
1224 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I32",
1225 [(set i32:$dst, (atomic_load_xor_32 xoaddr:$ptr, i32:$incr))]>;
1226 def ATOMIC_LOAD_NAND_I32 : Pseudo<
1227 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I32",
1228 [(set i32:$dst, (atomic_load_nand_32 xoaddr:$ptr, i32:$incr))]>;
1230 def ATOMIC_CMP_SWAP_I8 : Pseudo<
1231 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I8",
1232 [(set i32:$dst, (atomic_cmp_swap_8 xoaddr:$ptr, i32:$old, i32:$new))]>;
1233 def ATOMIC_CMP_SWAP_I16 : Pseudo<
1234 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new",
1235 [(set i32:$dst, (atomic_cmp_swap_16 xoaddr:$ptr, i32:$old, i32:$new))]>;
1236 def ATOMIC_CMP_SWAP_I32 : Pseudo<
1237 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new",
1238 [(set i32:$dst, (atomic_cmp_swap_32 xoaddr:$ptr, i32:$old, i32:$new))]>;
1240 def ATOMIC_SWAP_I8 : Pseudo<
1241 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_i8",
1242 [(set i32:$dst, (atomic_swap_8 xoaddr:$ptr, i32:$new))]>;
1243 def ATOMIC_SWAP_I16 : Pseudo<
1244 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I16",
1245 [(set i32:$dst, (atomic_swap_16 xoaddr:$ptr, i32:$new))]>;
1246 def ATOMIC_SWAP_I32 : Pseudo<
1247 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I32",
1248 [(set i32:$dst, (atomic_swap_32 xoaddr:$ptr, i32:$new))]>;
1252 // Instructions to support atomic operations
1253 def LWARX : XForm_1<31, 20, (outs gprc:$rD), (ins memrr:$src),
1254 "lwarx $rD, $src", IIC_LdStLWARX,
1255 [(set i32:$rD, (PPClarx xoaddr:$src))]>;
1258 def STWCX : XForm_1<31, 150, (outs), (ins gprc:$rS, memrr:$dst),
1259 "stwcx. $rS, $dst", IIC_LdStSTWCX,
1260 [(PPCstcx i32:$rS, xoaddr:$dst)]>,
1263 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
1264 def TRAP : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>;
1266 def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm),
1267 "twi $to, $rA, $imm", IIC_IntTrapW, []>;
1268 def TW : XForm_1<31, 4, (outs), (ins u5imm:$to, gprc:$rA, gprc:$rB),
1269 "tw $to, $rA, $rB", IIC_IntTrapW, []>;
1270 def TDI : DForm_base<2, (outs), (ins u5imm:$to, g8rc:$rA, s16imm:$imm),
1271 "tdi $to, $rA, $imm", IIC_IntTrapD, []>;
1272 def TD : XForm_1<31, 68, (outs), (ins u5imm:$to, g8rc:$rA, g8rc:$rB),
1273 "td $to, $rA, $rB", IIC_IntTrapD, []>;
1275 //===----------------------------------------------------------------------===//
1276 // PPC32 Load Instructions.
1279 // Unindexed (r+i) Loads.
1280 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
1281 def LBZ : DForm_1<34, (outs gprc:$rD), (ins memri:$src),
1282 "lbz $rD, $src", IIC_LdStLoad,
1283 [(set i32:$rD, (zextloadi8 iaddr:$src))]>;
1284 def LHA : DForm_1<42, (outs gprc:$rD), (ins memri:$src),
1285 "lha $rD, $src", IIC_LdStLHA,
1286 [(set i32:$rD, (sextloadi16 iaddr:$src))]>,
1287 PPC970_DGroup_Cracked;
1288 def LHZ : DForm_1<40, (outs gprc:$rD), (ins memri:$src),
1289 "lhz $rD, $src", IIC_LdStLoad,
1290 [(set i32:$rD, (zextloadi16 iaddr:$src))]>;
1291 def LWZ : DForm_1<32, (outs gprc:$rD), (ins memri:$src),
1292 "lwz $rD, $src", IIC_LdStLoad,
1293 [(set i32:$rD, (load iaddr:$src))]>;
1295 def LFS : DForm_1<48, (outs f4rc:$rD), (ins memri:$src),
1296 "lfs $rD, $src", IIC_LdStLFD,
1297 [(set f32:$rD, (load iaddr:$src))]>;
1298 def LFD : DForm_1<50, (outs f8rc:$rD), (ins memri:$src),
1299 "lfd $rD, $src", IIC_LdStLFD,
1300 [(set f64:$rD, (load iaddr:$src))]>;
1303 // Unindexed (r+i) Loads with Update (preinc).
1304 let mayLoad = 1, neverHasSideEffects = 1 in {
1305 def LBZU : DForm_1<35, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1306 "lbzu $rD, $addr", IIC_LdStLoadUpd,
1307 []>, RegConstraint<"$addr.reg = $ea_result">,
1308 NoEncode<"$ea_result">;
1310 def LHAU : DForm_1<43, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1311 "lhau $rD, $addr", IIC_LdStLHAU,
1312 []>, RegConstraint<"$addr.reg = $ea_result">,
1313 NoEncode<"$ea_result">;
1315 def LHZU : DForm_1<41, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1316 "lhzu $rD, $addr", IIC_LdStLoadUpd,
1317 []>, RegConstraint<"$addr.reg = $ea_result">,
1318 NoEncode<"$ea_result">;
1320 def LWZU : DForm_1<33, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1321 "lwzu $rD, $addr", IIC_LdStLoadUpd,
1322 []>, RegConstraint<"$addr.reg = $ea_result">,
1323 NoEncode<"$ea_result">;
1325 def LFSU : DForm_1<49, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1326 "lfsu $rD, $addr", IIC_LdStLFDU,
1327 []>, RegConstraint<"$addr.reg = $ea_result">,
1328 NoEncode<"$ea_result">;
1330 def LFDU : DForm_1<51, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1331 "lfdu $rD, $addr", IIC_LdStLFDU,
1332 []>, RegConstraint<"$addr.reg = $ea_result">,
1333 NoEncode<"$ea_result">;
1336 // Indexed (r+r) Loads with Update (preinc).
1337 def LBZUX : XForm_1<31, 119, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1339 "lbzux $rD, $addr", IIC_LdStLoadUpdX,
1340 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1341 NoEncode<"$ea_result">;
1343 def LHAUX : XForm_1<31, 375, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1345 "lhaux $rD, $addr", IIC_LdStLHAUX,
1346 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1347 NoEncode<"$ea_result">;
1349 def LHZUX : XForm_1<31, 311, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1351 "lhzux $rD, $addr", IIC_LdStLoadUpdX,
1352 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1353 NoEncode<"$ea_result">;
1355 def LWZUX : XForm_1<31, 55, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1357 "lwzux $rD, $addr", IIC_LdStLoadUpdX,
1358 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1359 NoEncode<"$ea_result">;
1361 def LFSUX : XForm_1<31, 567, (outs f4rc:$rD, ptr_rc_nor0:$ea_result),
1363 "lfsux $rD, $addr", IIC_LdStLFDUX,
1364 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1365 NoEncode<"$ea_result">;
1367 def LFDUX : XForm_1<31, 631, (outs f8rc:$rD, ptr_rc_nor0:$ea_result),
1369 "lfdux $rD, $addr", IIC_LdStLFDUX,
1370 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1371 NoEncode<"$ea_result">;
1375 // Indexed (r+r) Loads.
1377 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
1378 def LBZX : XForm_1<31, 87, (outs gprc:$rD), (ins memrr:$src),
1379 "lbzx $rD, $src", IIC_LdStLoad,
1380 [(set i32:$rD, (zextloadi8 xaddr:$src))]>;
1381 def LHAX : XForm_1<31, 343, (outs gprc:$rD), (ins memrr:$src),
1382 "lhax $rD, $src", IIC_LdStLHA,
1383 [(set i32:$rD, (sextloadi16 xaddr:$src))]>,
1384 PPC970_DGroup_Cracked;
1385 def LHZX : XForm_1<31, 279, (outs gprc:$rD), (ins memrr:$src),
1386 "lhzx $rD, $src", IIC_LdStLoad,
1387 [(set i32:$rD, (zextloadi16 xaddr:$src))]>;
1388 def LWZX : XForm_1<31, 23, (outs gprc:$rD), (ins memrr:$src),
1389 "lwzx $rD, $src", IIC_LdStLoad,
1390 [(set i32:$rD, (load xaddr:$src))]>;
1393 def LHBRX : XForm_1<31, 790, (outs gprc:$rD), (ins memrr:$src),
1394 "lhbrx $rD, $src", IIC_LdStLoad,
1395 [(set i32:$rD, (PPClbrx xoaddr:$src, i16))]>;
1396 def LWBRX : XForm_1<31, 534, (outs gprc:$rD), (ins memrr:$src),
1397 "lwbrx $rD, $src", IIC_LdStLoad,
1398 [(set i32:$rD, (PPClbrx xoaddr:$src, i32))]>;
1400 def LFSX : XForm_25<31, 535, (outs f4rc:$frD), (ins memrr:$src),
1401 "lfsx $frD, $src", IIC_LdStLFD,
1402 [(set f32:$frD, (load xaddr:$src))]>;
1403 def LFDX : XForm_25<31, 599, (outs f8rc:$frD), (ins memrr:$src),
1404 "lfdx $frD, $src", IIC_LdStLFD,
1405 [(set f64:$frD, (load xaddr:$src))]>;
1407 def LFIWAX : XForm_25<31, 855, (outs f8rc:$frD), (ins memrr:$src),
1408 "lfiwax $frD, $src", IIC_LdStLFD,
1409 [(set f64:$frD, (PPClfiwax xoaddr:$src))]>;
1410 def LFIWZX : XForm_25<31, 887, (outs f8rc:$frD), (ins memrr:$src),
1411 "lfiwzx $frD, $src", IIC_LdStLFD,
1412 [(set f64:$frD, (PPClfiwzx xoaddr:$src))]>;
1416 def LMW : DForm_1<46, (outs gprc:$rD), (ins memri:$src),
1417 "lmw $rD, $src", IIC_LdStLMW, []>;
1419 //===----------------------------------------------------------------------===//
1420 // PPC32 Store Instructions.
1423 // Unindexed (r+i) Stores.
1424 let PPC970_Unit = 2 in {
1425 def STB : DForm_1<38, (outs), (ins gprc:$rS, memri:$src),
1426 "stb $rS, $src", IIC_LdStStore,
1427 [(truncstorei8 i32:$rS, iaddr:$src)]>;
1428 def STH : DForm_1<44, (outs), (ins gprc:$rS, memri:$src),
1429 "sth $rS, $src", IIC_LdStStore,
1430 [(truncstorei16 i32:$rS, iaddr:$src)]>;
1431 def STW : DForm_1<36, (outs), (ins gprc:$rS, memri:$src),
1432 "stw $rS, $src", IIC_LdStStore,
1433 [(store i32:$rS, iaddr:$src)]>;
1434 def STFS : DForm_1<52, (outs), (ins f4rc:$rS, memri:$dst),
1435 "stfs $rS, $dst", IIC_LdStSTFD,
1436 [(store f32:$rS, iaddr:$dst)]>;
1437 def STFD : DForm_1<54, (outs), (ins f8rc:$rS, memri:$dst),
1438 "stfd $rS, $dst", IIC_LdStSTFD,
1439 [(store f64:$rS, iaddr:$dst)]>;
1442 // Unindexed (r+i) Stores with Update (preinc).
1443 let PPC970_Unit = 2, mayStore = 1 in {
1444 def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1445 "stbu $rS, $dst", IIC_LdStStoreUpd, []>,
1446 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1447 def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1448 "sthu $rS, $dst", IIC_LdStStoreUpd, []>,
1449 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1450 def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1451 "stwu $rS, $dst", IIC_LdStStoreUpd, []>,
1452 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1453 def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memri:$dst),
1454 "stfsu $rS, $dst", IIC_LdStSTFDU, []>,
1455 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1456 def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memri:$dst),
1457 "stfdu $rS, $dst", IIC_LdStSTFDU, []>,
1458 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1461 // Patterns to match the pre-inc stores. We can't put the patterns on
1462 // the instruction definitions directly as ISel wants the address base
1463 // and offset to be separate operands, not a single complex operand.
1464 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1465 (STBU $rS, iaddroff:$ptroff, $ptrreg)>;
1466 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1467 (STHU $rS, iaddroff:$ptroff, $ptrreg)>;
1468 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1469 (STWU $rS, iaddroff:$ptroff, $ptrreg)>;
1470 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1471 (STFSU $rS, iaddroff:$ptroff, $ptrreg)>;
1472 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1473 (STFDU $rS, iaddroff:$ptroff, $ptrreg)>;
1475 // Indexed (r+r) Stores.
1476 let PPC970_Unit = 2 in {
1477 def STBX : XForm_8<31, 215, (outs), (ins gprc:$rS, memrr:$dst),
1478 "stbx $rS, $dst", IIC_LdStStore,
1479 [(truncstorei8 i32:$rS, xaddr:$dst)]>,
1480 PPC970_DGroup_Cracked;
1481 def STHX : XForm_8<31, 407, (outs), (ins gprc:$rS, memrr:$dst),
1482 "sthx $rS, $dst", IIC_LdStStore,
1483 [(truncstorei16 i32:$rS, xaddr:$dst)]>,
1484 PPC970_DGroup_Cracked;
1485 def STWX : XForm_8<31, 151, (outs), (ins gprc:$rS, memrr:$dst),
1486 "stwx $rS, $dst", IIC_LdStStore,
1487 [(store i32:$rS, xaddr:$dst)]>,
1488 PPC970_DGroup_Cracked;
1490 def STHBRX: XForm_8<31, 918, (outs), (ins gprc:$rS, memrr:$dst),
1491 "sthbrx $rS, $dst", IIC_LdStStore,
1492 [(PPCstbrx i32:$rS, xoaddr:$dst, i16)]>,
1493 PPC970_DGroup_Cracked;
1494 def STWBRX: XForm_8<31, 662, (outs), (ins gprc:$rS, memrr:$dst),
1495 "stwbrx $rS, $dst", IIC_LdStStore,
1496 [(PPCstbrx i32:$rS, xoaddr:$dst, i32)]>,
1497 PPC970_DGroup_Cracked;
1499 def STFIWX: XForm_28<31, 983, (outs), (ins f8rc:$frS, memrr:$dst),
1500 "stfiwx $frS, $dst", IIC_LdStSTFD,
1501 [(PPCstfiwx f64:$frS, xoaddr:$dst)]>;
1503 def STFSX : XForm_28<31, 663, (outs), (ins f4rc:$frS, memrr:$dst),
1504 "stfsx $frS, $dst", IIC_LdStSTFD,
1505 [(store f32:$frS, xaddr:$dst)]>;
1506 def STFDX : XForm_28<31, 727, (outs), (ins f8rc:$frS, memrr:$dst),
1507 "stfdx $frS, $dst", IIC_LdStSTFD,
1508 [(store f64:$frS, xaddr:$dst)]>;
1511 // Indexed (r+r) Stores with Update (preinc).
1512 let PPC970_Unit = 2, mayStore = 1 in {
1513 def STBUX : XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1514 "stbux $rS, $dst", IIC_LdStStoreUpd, []>,
1515 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1516 PPC970_DGroup_Cracked;
1517 def STHUX : XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1518 "sthux $rS, $dst", IIC_LdStStoreUpd, []>,
1519 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1520 PPC970_DGroup_Cracked;
1521 def STWUX : XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1522 "stwux $rS, $dst", IIC_LdStStoreUpd, []>,
1523 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1524 PPC970_DGroup_Cracked;
1525 def STFSUX: XForm_8<31, 695, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memrr:$dst),
1526 "stfsux $rS, $dst", IIC_LdStSTFDU, []>,
1527 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1528 PPC970_DGroup_Cracked;
1529 def STFDUX: XForm_8<31, 759, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memrr:$dst),
1530 "stfdux $rS, $dst", IIC_LdStSTFDU, []>,
1531 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1532 PPC970_DGroup_Cracked;
1535 // Patterns to match the pre-inc stores. We can't put the patterns on
1536 // the instruction definitions directly as ISel wants the address base
1537 // and offset to be separate operands, not a single complex operand.
1538 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1539 (STBUX $rS, $ptrreg, $ptroff)>;
1540 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1541 (STHUX $rS, $ptrreg, $ptroff)>;
1542 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1543 (STWUX $rS, $ptrreg, $ptroff)>;
1544 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1545 (STFSUX $rS, $ptrreg, $ptroff)>;
1546 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1547 (STFDUX $rS, $ptrreg, $ptroff)>;
1550 def STMW : DForm_1<47, (outs), (ins gprc:$rS, memri:$dst),
1551 "stmw $rS, $dst", IIC_LdStLMW, []>;
1553 def SYNC : XForm_24_sync<31, 598, (outs), (ins i32imm:$L),
1554 "sync $L", IIC_LdStSync, []>, Requires<[IsNotBookE]>;
1556 let isCodeGenOnly = 1 in {
1557 def MSYNC : XForm_24_sync<31, 598, (outs), (ins),
1558 "msync", IIC_LdStSync, []>, Requires<[IsBookE]> {
1563 def : Pat<(int_ppc_sync), (SYNC 0)>, Requires<[IsNotBookE]>;
1564 def : Pat<(int_ppc_sync), (MSYNC)>, Requires<[IsBookE]>;
1566 //===----------------------------------------------------------------------===//
1567 // PPC32 Arithmetic Instructions.
1570 let PPC970_Unit = 1 in { // FXU Operations.
1571 def ADDI : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$imm),
1572 "addi $rD, $rA, $imm", IIC_IntSimple,
1573 [(set i32:$rD, (add i32:$rA, imm32SExt16:$imm))]>;
1574 let BaseName = "addic" in {
1575 let Defs = [CARRY] in
1576 def ADDIC : DForm_2<12, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1577 "addic $rD, $rA, $imm", IIC_IntGeneral,
1578 [(set i32:$rD, (addc i32:$rA, imm32SExt16:$imm))]>,
1579 RecFormRel, PPC970_DGroup_Cracked;
1580 let Defs = [CARRY, CR0] in
1581 def ADDICo : DForm_2<13, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1582 "addic. $rD, $rA, $imm", IIC_IntGeneral,
1583 []>, isDOT, RecFormRel;
1585 def ADDIS : DForm_2<15, (outs gprc:$rD), (ins gprc_nor0:$rA, s17imm:$imm),
1586 "addis $rD, $rA, $imm", IIC_IntSimple,
1587 [(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>;
1588 let isCodeGenOnly = 1 in
1589 def LA : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$sym),
1590 "la $rD, $sym($rA)", IIC_IntGeneral,
1591 [(set i32:$rD, (add i32:$rA,
1592 (PPClo tglobaladdr:$sym, 0)))]>;
1593 def MULLI : DForm_2< 7, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1594 "mulli $rD, $rA, $imm", IIC_IntMulLI,
1595 [(set i32:$rD, (mul i32:$rA, imm32SExt16:$imm))]>;
1596 let Defs = [CARRY] in
1597 def SUBFIC : DForm_2< 8, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1598 "subfic $rD, $rA, $imm", IIC_IntGeneral,
1599 [(set i32:$rD, (subc imm32SExt16:$imm, i32:$rA))]>;
1601 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
1602 def LI : DForm_2_r0<14, (outs gprc:$rD), (ins s16imm:$imm),
1603 "li $rD, $imm", IIC_IntSimple,
1604 [(set i32:$rD, imm32SExt16:$imm)]>;
1605 def LIS : DForm_2_r0<15, (outs gprc:$rD), (ins s17imm:$imm),
1606 "lis $rD, $imm", IIC_IntSimple,
1607 [(set i32:$rD, imm16ShiftedSExt:$imm)]>;
1611 let PPC970_Unit = 1 in { // FXU Operations.
1612 let Defs = [CR0] in {
1613 def ANDIo : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1614 "andi. $dst, $src1, $src2", IIC_IntGeneral,
1615 [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>,
1617 def ANDISo : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1618 "andis. $dst, $src1, $src2", IIC_IntGeneral,
1619 [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>,
1622 def ORI : DForm_4<24, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1623 "ori $dst, $src1, $src2", IIC_IntSimple,
1624 [(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>;
1625 def ORIS : DForm_4<25, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1626 "oris $dst, $src1, $src2", IIC_IntSimple,
1627 [(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>;
1628 def XORI : DForm_4<26, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1629 "xori $dst, $src1, $src2", IIC_IntSimple,
1630 [(set i32:$dst, (xor i32:$src1, immZExt16:$src2))]>;
1631 def XORIS : DForm_4<27, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1632 "xoris $dst, $src1, $src2", IIC_IntSimple,
1633 [(set i32:$dst, (xor i32:$src1, imm16ShiftedZExt:$src2))]>;
1635 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IIC_IntSimple,
1637 let isCodeGenOnly = 1 in {
1638 // The POWER6 and POWER7 have special group-terminating nops.
1639 def NOP_GT_PWR6 : DForm_4_fixedreg_zero<24, 1, (outs), (ins),
1640 "ori 1, 1, 0", IIC_IntSimple, []>;
1641 def NOP_GT_PWR7 : DForm_4_fixedreg_zero<24, 2, (outs), (ins),
1642 "ori 2, 2, 0", IIC_IntSimple, []>;
1645 let isCompare = 1, neverHasSideEffects = 1 in {
1646 def CMPWI : DForm_5_ext<11, (outs crrc:$crD), (ins gprc:$rA, s16imm:$imm),
1647 "cmpwi $crD, $rA, $imm", IIC_IntCompare>;
1648 def CMPLWI : DForm_6_ext<10, (outs crrc:$dst), (ins gprc:$src1, u16imm:$src2),
1649 "cmplwi $dst, $src1, $src2", IIC_IntCompare>;
1653 let PPC970_Unit = 1, neverHasSideEffects = 1 in { // FXU Operations.
1654 defm NAND : XForm_6r<31, 476, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1655 "nand", "$rA, $rS, $rB", IIC_IntSimple,
1656 [(set i32:$rA, (not (and i32:$rS, i32:$rB)))]>;
1657 defm AND : XForm_6r<31, 28, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1658 "and", "$rA, $rS, $rB", IIC_IntSimple,
1659 [(set i32:$rA, (and i32:$rS, i32:$rB))]>;
1660 defm ANDC : XForm_6r<31, 60, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1661 "andc", "$rA, $rS, $rB", IIC_IntSimple,
1662 [(set i32:$rA, (and i32:$rS, (not i32:$rB)))]>;
1663 defm OR : XForm_6r<31, 444, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1664 "or", "$rA, $rS, $rB", IIC_IntSimple,
1665 [(set i32:$rA, (or i32:$rS, i32:$rB))]>;
1666 defm NOR : XForm_6r<31, 124, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1667 "nor", "$rA, $rS, $rB", IIC_IntSimple,
1668 [(set i32:$rA, (not (or i32:$rS, i32:$rB)))]>;
1669 defm ORC : XForm_6r<31, 412, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1670 "orc", "$rA, $rS, $rB", IIC_IntSimple,
1671 [(set i32:$rA, (or i32:$rS, (not i32:$rB)))]>;
1672 defm EQV : XForm_6r<31, 284, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1673 "eqv", "$rA, $rS, $rB", IIC_IntSimple,
1674 [(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>;
1675 defm XOR : XForm_6r<31, 316, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1676 "xor", "$rA, $rS, $rB", IIC_IntSimple,
1677 [(set i32:$rA, (xor i32:$rS, i32:$rB))]>;
1678 defm SLW : XForm_6r<31, 24, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1679 "slw", "$rA, $rS, $rB", IIC_IntGeneral,
1680 [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>;
1681 defm SRW : XForm_6r<31, 536, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1682 "srw", "$rA, $rS, $rB", IIC_IntGeneral,
1683 [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>;
1684 defm SRAW : XForm_6rc<31, 792, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1685 "sraw", "$rA, $rS, $rB", IIC_IntShift,
1686 [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>;
1689 let PPC970_Unit = 1 in { // FXU Operations.
1690 let neverHasSideEffects = 1 in {
1691 defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH),
1692 "srawi", "$rA, $rS, $SH", IIC_IntShift,
1693 [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>;
1694 defm CNTLZW : XForm_11r<31, 26, (outs gprc:$rA), (ins gprc:$rS),
1695 "cntlzw", "$rA, $rS", IIC_IntGeneral,
1696 [(set i32:$rA, (ctlz i32:$rS))]>;
1697 defm EXTSB : XForm_11r<31, 954, (outs gprc:$rA), (ins gprc:$rS),
1698 "extsb", "$rA, $rS", IIC_IntSimple,
1699 [(set i32:$rA, (sext_inreg i32:$rS, i8))]>;
1700 defm EXTSH : XForm_11r<31, 922, (outs gprc:$rA), (ins gprc:$rS),
1701 "extsh", "$rA, $rS", IIC_IntSimple,
1702 [(set i32:$rA, (sext_inreg i32:$rS, i16))]>;
1704 let isCompare = 1, neverHasSideEffects = 1 in {
1705 def CMPW : XForm_16_ext<31, 0, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
1706 "cmpw $crD, $rA, $rB", IIC_IntCompare>;
1707 def CMPLW : XForm_16_ext<31, 32, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
1708 "cmplw $crD, $rA, $rB", IIC_IntCompare>;
1711 let PPC970_Unit = 3 in { // FPU Operations.
1712 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
1713 // "fcmpo $crD, $fA, $fB", IIC_FPCompare>;
1714 let isCompare = 1, neverHasSideEffects = 1 in {
1715 def FCMPUS : XForm_17<63, 0, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB),
1716 "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
1717 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1718 def FCMPUD : XForm_17<63, 0, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB),
1719 "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
1722 let Uses = [RM] in {
1723 let neverHasSideEffects = 1 in {
1724 defm FCTIW : XForm_26r<63, 14, (outs f8rc:$frD), (ins f8rc:$frB),
1725 "fctiw", "$frD, $frB", IIC_FPGeneral,
1727 defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB),
1728 "fctiwz", "$frD, $frB", IIC_FPGeneral,
1729 [(set f64:$frD, (PPCfctiwz f64:$frB))]>;
1731 defm FRSP : XForm_26r<63, 12, (outs f4rc:$frD), (ins f8rc:$frB),
1732 "frsp", "$frD, $frB", IIC_FPGeneral,
1733 [(set f32:$frD, (fround f64:$frB))]>;
1735 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1736 defm FRIND : XForm_26r<63, 392, (outs f8rc:$frD), (ins f8rc:$frB),
1737 "frin", "$frD, $frB", IIC_FPGeneral,
1738 [(set f64:$frD, (frnd f64:$frB))]>;
1739 defm FRINS : XForm_26r<63, 392, (outs f4rc:$frD), (ins f4rc:$frB),
1740 "frin", "$frD, $frB", IIC_FPGeneral,
1741 [(set f32:$frD, (frnd f32:$frB))]>;
1744 let neverHasSideEffects = 1 in {
1745 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1746 defm FRIPD : XForm_26r<63, 456, (outs f8rc:$frD), (ins f8rc:$frB),
1747 "frip", "$frD, $frB", IIC_FPGeneral,
1748 [(set f64:$frD, (fceil f64:$frB))]>;
1749 defm FRIPS : XForm_26r<63, 456, (outs f4rc:$frD), (ins f4rc:$frB),
1750 "frip", "$frD, $frB", IIC_FPGeneral,
1751 [(set f32:$frD, (fceil f32:$frB))]>;
1752 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1753 defm FRIZD : XForm_26r<63, 424, (outs f8rc:$frD), (ins f8rc:$frB),
1754 "friz", "$frD, $frB", IIC_FPGeneral,
1755 [(set f64:$frD, (ftrunc f64:$frB))]>;
1756 defm FRIZS : XForm_26r<63, 424, (outs f4rc:$frD), (ins f4rc:$frB),
1757 "friz", "$frD, $frB", IIC_FPGeneral,
1758 [(set f32:$frD, (ftrunc f32:$frB))]>;
1759 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1760 defm FRIMD : XForm_26r<63, 488, (outs f8rc:$frD), (ins f8rc:$frB),
1761 "frim", "$frD, $frB", IIC_FPGeneral,
1762 [(set f64:$frD, (ffloor f64:$frB))]>;
1763 defm FRIMS : XForm_26r<63, 488, (outs f4rc:$frD), (ins f4rc:$frB),
1764 "frim", "$frD, $frB", IIC_FPGeneral,
1765 [(set f32:$frD, (ffloor f32:$frB))]>;
1767 defm FSQRT : XForm_26r<63, 22, (outs f8rc:$frD), (ins f8rc:$frB),
1768 "fsqrt", "$frD, $frB", IIC_FPSqrtD,
1769 [(set f64:$frD, (fsqrt f64:$frB))]>;
1770 defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$frD), (ins f4rc:$frB),
1771 "fsqrts", "$frD, $frB", IIC_FPSqrtS,
1772 [(set f32:$frD, (fsqrt f32:$frB))]>;
1777 /// Note that FMR is defined as pseudo-ops on the PPC970 because they are
1778 /// often coalesced away and we don't want the dispatch group builder to think
1779 /// that they will fill slots (which could cause the load of a LSU reject to
1780 /// sneak into a d-group with a store).
1781 let neverHasSideEffects = 1 in
1782 defm FMR : XForm_26r<63, 72, (outs f4rc:$frD), (ins f4rc:$frB),
1783 "fmr", "$frD, $frB", IIC_FPGeneral,
1784 []>, // (set f32:$frD, f32:$frB)
1787 let PPC970_Unit = 3, neverHasSideEffects = 1 in { // FPU Operations.
1788 // These are artificially split into two different forms, for 4/8 byte FP.
1789 defm FABSS : XForm_26r<63, 264, (outs f4rc:$frD), (ins f4rc:$frB),
1790 "fabs", "$frD, $frB", IIC_FPGeneral,
1791 [(set f32:$frD, (fabs f32:$frB))]>;
1792 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1793 defm FABSD : XForm_26r<63, 264, (outs f8rc:$frD), (ins f8rc:$frB),
1794 "fabs", "$frD, $frB", IIC_FPGeneral,
1795 [(set f64:$frD, (fabs f64:$frB))]>;
1796 defm FNABSS : XForm_26r<63, 136, (outs f4rc:$frD), (ins f4rc:$frB),
1797 "fnabs", "$frD, $frB", IIC_FPGeneral,
1798 [(set f32:$frD, (fneg (fabs f32:$frB)))]>;
1799 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1800 defm FNABSD : XForm_26r<63, 136, (outs f8rc:$frD), (ins f8rc:$frB),
1801 "fnabs", "$frD, $frB", IIC_FPGeneral,
1802 [(set f64:$frD, (fneg (fabs f64:$frB)))]>;
1803 defm FNEGS : XForm_26r<63, 40, (outs f4rc:$frD), (ins f4rc:$frB),
1804 "fneg", "$frD, $frB", IIC_FPGeneral,
1805 [(set f32:$frD, (fneg f32:$frB))]>;
1806 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1807 defm FNEGD : XForm_26r<63, 40, (outs f8rc:$frD), (ins f8rc:$frB),
1808 "fneg", "$frD, $frB", IIC_FPGeneral,
1809 [(set f64:$frD, (fneg f64:$frB))]>;
1811 defm FCPSGNS : XForm_28r<63, 8, (outs f4rc:$frD), (ins f4rc:$frA, f4rc:$frB),
1812 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
1813 [(set f32:$frD, (fcopysign f32:$frB, f32:$frA))]>;
1814 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1815 defm FCPSGND : XForm_28r<63, 8, (outs f8rc:$frD), (ins f8rc:$frA, f8rc:$frB),
1816 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
1817 [(set f64:$frD, (fcopysign f64:$frB, f64:$frA))]>;
1819 // Reciprocal estimates.
1820 defm FRE : XForm_26r<63, 24, (outs f8rc:$frD), (ins f8rc:$frB),
1821 "fre", "$frD, $frB", IIC_FPGeneral,
1822 [(set f64:$frD, (PPCfre f64:$frB))]>;
1823 defm FRES : XForm_26r<59, 24, (outs f4rc:$frD), (ins f4rc:$frB),
1824 "fres", "$frD, $frB", IIC_FPGeneral,
1825 [(set f32:$frD, (PPCfre f32:$frB))]>;
1826 defm FRSQRTE : XForm_26r<63, 26, (outs f8rc:$frD), (ins f8rc:$frB),
1827 "frsqrte", "$frD, $frB", IIC_FPGeneral,
1828 [(set f64:$frD, (PPCfrsqrte f64:$frB))]>;
1829 defm FRSQRTES : XForm_26r<59, 26, (outs f4rc:$frD), (ins f4rc:$frB),
1830 "frsqrtes", "$frD, $frB", IIC_FPGeneral,
1831 [(set f32:$frD, (PPCfrsqrte f32:$frB))]>;
1834 // XL-Form instructions. condition register logical ops.
1836 let neverHasSideEffects = 1 in
1837 def MCRF : XLForm_3<19, 0, (outs crrc:$BF), (ins crrc:$BFA),
1838 "mcrf $BF, $BFA", IIC_BrMCR>,
1839 PPC970_DGroup_First, PPC970_Unit_CRU;
1841 def CRAND : XLForm_1<19, 257, (outs crbitrc:$CRD),
1842 (ins crbitrc:$CRA, crbitrc:$CRB),
1843 "crand $CRD, $CRA, $CRB", IIC_BrCR, []>;
1845 def CRNAND : XLForm_1<19, 225, (outs crbitrc:$CRD),
1846 (ins crbitrc:$CRA, crbitrc:$CRB),
1847 "crnand $CRD, $CRA, $CRB", IIC_BrCR, []>;
1849 def CROR : XLForm_1<19, 449, (outs crbitrc:$CRD),
1850 (ins crbitrc:$CRA, crbitrc:$CRB),
1851 "cror $CRD, $CRA, $CRB", IIC_BrCR, []>;
1853 def CRXOR : XLForm_1<19, 193, (outs crbitrc:$CRD),
1854 (ins crbitrc:$CRA, crbitrc:$CRB),
1855 "crxor $CRD, $CRA, $CRB", IIC_BrCR, []>;
1857 def CRNOR : XLForm_1<19, 33, (outs crbitrc:$CRD),
1858 (ins crbitrc:$CRA, crbitrc:$CRB),
1859 "crnor $CRD, $CRA, $CRB", IIC_BrCR, []>;
1861 def CREQV : XLForm_1<19, 289, (outs crbitrc:$CRD),
1862 (ins crbitrc:$CRA, crbitrc:$CRB),
1863 "creqv $CRD, $CRA, $CRB", IIC_BrCR, []>;
1865 def CRANDC : XLForm_1<19, 129, (outs crbitrc:$CRD),
1866 (ins crbitrc:$CRA, crbitrc:$CRB),
1867 "crandc $CRD, $CRA, $CRB", IIC_BrCR, []>;
1869 def CRORC : XLForm_1<19, 417, (outs crbitrc:$CRD),
1870 (ins crbitrc:$CRA, crbitrc:$CRB),
1871 "crorc $CRD, $CRA, $CRB", IIC_BrCR, []>;
1873 let isCodeGenOnly = 1 in {
1874 def CRSET : XLForm_1_ext<19, 289, (outs crbitrc:$dst), (ins),
1875 "creqv $dst, $dst, $dst", IIC_BrCR,
1878 def CRUNSET: XLForm_1_ext<19, 193, (outs crbitrc:$dst), (ins),
1879 "crxor $dst, $dst, $dst", IIC_BrCR,
1882 let Defs = [CR1EQ], CRD = 6 in {
1883 def CR6SET : XLForm_1_ext<19, 289, (outs), (ins),
1884 "creqv 6, 6, 6", IIC_BrCR,
1887 def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins),
1888 "crxor 6, 6, 6", IIC_BrCR,
1893 // XFX-Form instructions. Instructions that deal with SPRs.
1896 def MFSPR : XFXForm_1<31, 339, (outs gprc:$RT), (ins i32imm:$SPR),
1897 "mfspr $RT, $SPR", IIC_SprMFSPR>;
1898 def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RT),
1899 "mtspr $SPR, $RT", IIC_SprMTSPR>;
1901 def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR),
1902 "mftb $RT, $SPR", IIC_SprMFTB>, Deprecated<DeprecatedMFTB>;
1904 let Uses = [CTR] in {
1905 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$rT), (ins),
1906 "mfctr $rT", IIC_SprMFSPR>,
1907 PPC970_DGroup_First, PPC970_Unit_FXU;
1909 let Defs = [CTR], Pattern = [(PPCmtctr i32:$rS)] in {
1910 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
1911 "mtctr $rS", IIC_SprMTSPR>,
1912 PPC970_DGroup_First, PPC970_Unit_FXU;
1914 let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR] in {
1915 let Pattern = [(int_ppc_mtctr i32:$rS)] in
1916 def MTCTRloop : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
1917 "mtctr $rS", IIC_SprMTSPR>,
1918 PPC970_DGroup_First, PPC970_Unit_FXU;
1921 let Defs = [LR] in {
1922 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins gprc:$rS),
1923 "mtlr $rS", IIC_SprMTSPR>,
1924 PPC970_DGroup_First, PPC970_Unit_FXU;
1926 let Uses = [LR] in {
1927 def MFLR : XFXForm_1_ext<31, 339, 8, (outs gprc:$rT), (ins),
1928 "mflr $rT", IIC_SprMFSPR>,
1929 PPC970_DGroup_First, PPC970_Unit_FXU;
1932 let isCodeGenOnly = 1 in {
1933 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed
1934 // like a GPR on the PPC970. As such, copies in and out have the same
1935 // performance characteristics as an OR instruction.
1936 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins gprc:$rS),
1937 "mtspr 256, $rS", IIC_IntGeneral>,
1938 PPC970_DGroup_Single, PPC970_Unit_FXU;
1939 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), (ins),
1940 "mfspr $rT, 256", IIC_IntGeneral>,
1941 PPC970_DGroup_First, PPC970_Unit_FXU;
1943 def MTVRSAVEv : XFXForm_7_ext<31, 467, 256,
1944 (outs VRSAVERC:$reg), (ins gprc:$rS),
1945 "mtspr 256, $rS", IIC_IntGeneral>,
1946 PPC970_DGroup_Single, PPC970_Unit_FXU;
1947 def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT),
1948 (ins VRSAVERC:$reg),
1949 "mfspr $rT, 256", IIC_IntGeneral>,
1950 PPC970_DGroup_First, PPC970_Unit_FXU;
1953 // SPILL_VRSAVE - Indicate that we're dumping the VRSAVE register,
1954 // so we'll need to scavenge a register for it.
1956 def SPILL_VRSAVE : Pseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F),
1957 "#SPILL_VRSAVE", []>;
1959 // RESTORE_VRSAVE - Indicate that we're restoring the VRSAVE register (previously
1960 // spilled), so we'll need to scavenge a register for it.
1962 def RESTORE_VRSAVE : Pseudo<(outs VRSAVERC:$vrsave), (ins memri:$F),
1963 "#RESTORE_VRSAVE", []>;
1965 let neverHasSideEffects = 1 in {
1966 def MTOCRF: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins gprc:$ST),
1967 "mtocrf $FXM, $ST", IIC_BrMCRX>,
1968 PPC970_DGroup_First, PPC970_Unit_CRU;
1970 def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$rS),
1971 "mtcrf $FXM, $rS", IIC_BrMCRX>,
1972 PPC970_MicroCode, PPC970_Unit_CRU;
1974 let hasExtraSrcRegAllocReq = 1 in // to enable post-ra anti-dep breaking.
1975 def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$rT), (ins crbitm:$FXM),
1976 "mfocrf $rT, $FXM", IIC_SprMFCRF>,
1977 PPC970_DGroup_First, PPC970_Unit_CRU;
1979 def MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins),
1980 "mfcr $rT", IIC_SprMFCR>,
1981 PPC970_MicroCode, PPC970_Unit_CRU;
1982 } // neverHasSideEffects = 1
1984 // Pseudo instruction to perform FADD in round-to-zero mode.
1985 let usesCustomInserter = 1, Uses = [RM] in {
1986 def FADDrtz: Pseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "",
1987 [(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>;
1990 // The above pseudo gets expanded to make use of the following instructions
1991 // to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level.
1992 let Uses = [RM], Defs = [RM] in {
1993 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
1994 "mtfsb0 $FM", IIC_IntMTFSB0, []>,
1995 PPC970_DGroup_Single, PPC970_Unit_FPU;
1996 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
1997 "mtfsb1 $FM", IIC_IntMTFSB0, []>,
1998 PPC970_DGroup_Single, PPC970_Unit_FPU;
1999 def MTFSF : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$rT),
2000 "mtfsf $FM, $rT", IIC_IntMTFSB0, []>,
2001 PPC970_DGroup_Single, PPC970_Unit_FPU;
2003 let Uses = [RM] in {
2004 def MFFS : XForm_42<63, 583, (outs f8rc:$rT), (ins),
2005 "mffs $rT", IIC_IntMFFS,
2006 [(set f64:$rT, (PPCmffs))]>,
2007 PPC970_DGroup_Single, PPC970_Unit_FPU;
2011 let PPC970_Unit = 1, neverHasSideEffects = 1 in { // FXU Operations.
2012 // XO-Form instructions. Arithmetic instructions that can set overflow bit
2014 defm ADD4 : XOForm_1r<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2015 "add", "$rT, $rA, $rB", IIC_IntSimple,
2016 [(set i32:$rT, (add i32:$rA, i32:$rB))]>;
2017 let isCodeGenOnly = 1 in
2018 def ADD4TLS : XOForm_1<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, tlsreg32:$rB),
2019 "add $rT, $rA, $rB", IIC_IntSimple,
2020 [(set i32:$rT, (add i32:$rA, tglobaltlsaddr:$rB))]>;
2021 defm ADDC : XOForm_1rc<31, 10, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2022 "addc", "$rT, $rA, $rB", IIC_IntGeneral,
2023 [(set i32:$rT, (addc i32:$rA, i32:$rB))]>,
2024 PPC970_DGroup_Cracked;
2025 defm DIVW : XOForm_1r<31, 491, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2026 "divw", "$rT, $rA, $rB", IIC_IntDivW,
2027 [(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>,
2028 PPC970_DGroup_First, PPC970_DGroup_Cracked;
2029 defm DIVWU : XOForm_1r<31, 459, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2030 "divwu", "$rT, $rA, $rB", IIC_IntDivW,
2031 [(set i32:$rT, (udiv i32:$rA, i32:$rB))]>,
2032 PPC970_DGroup_First, PPC970_DGroup_Cracked;
2033 defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2034 "mulhw", "$rT, $rA, $rB", IIC_IntMulHW,
2035 [(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>;
2036 defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2037 "mulhwu", "$rT, $rA, $rB", IIC_IntMulHWU,
2038 [(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>;
2039 defm MULLW : XOForm_1r<31, 235, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2040 "mullw", "$rT, $rA, $rB", IIC_IntMulHW,
2041 [(set i32:$rT, (mul i32:$rA, i32:$rB))]>;
2042 defm SUBF : XOForm_1r<31, 40, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2043 "subf", "$rT, $rA, $rB", IIC_IntGeneral,
2044 [(set i32:$rT, (sub i32:$rB, i32:$rA))]>;
2045 defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2046 "subfc", "$rT, $rA, $rB", IIC_IntGeneral,
2047 [(set i32:$rT, (subc i32:$rB, i32:$rA))]>,
2048 PPC970_DGroup_Cracked;
2049 defm NEG : XOForm_3r<31, 104, 0, (outs gprc:$rT), (ins gprc:$rA),
2050 "neg", "$rT, $rA", IIC_IntSimple,
2051 [(set i32:$rT, (ineg i32:$rA))]>;
2052 let Uses = [CARRY] in {
2053 defm ADDE : XOForm_1rc<31, 138, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2054 "adde", "$rT, $rA, $rB", IIC_IntGeneral,
2055 [(set i32:$rT, (adde i32:$rA, i32:$rB))]>;
2056 defm ADDME : XOForm_3rc<31, 234, 0, (outs gprc:$rT), (ins gprc:$rA),
2057 "addme", "$rT, $rA", IIC_IntGeneral,
2058 [(set i32:$rT, (adde i32:$rA, -1))]>;
2059 defm ADDZE : XOForm_3rc<31, 202, 0, (outs gprc:$rT), (ins gprc:$rA),
2060 "addze", "$rT, $rA", IIC_IntGeneral,
2061 [(set i32:$rT, (adde i32:$rA, 0))]>;
2062 defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2063 "subfe", "$rT, $rA, $rB", IIC_IntGeneral,
2064 [(set i32:$rT, (sube i32:$rB, i32:$rA))]>;
2065 defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$rT), (ins gprc:$rA),
2066 "subfme", "$rT, $rA", IIC_IntGeneral,
2067 [(set i32:$rT, (sube -1, i32:$rA))]>;
2068 defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$rT), (ins gprc:$rA),
2069 "subfze", "$rT, $rA", IIC_IntGeneral,
2070 [(set i32:$rT, (sube 0, i32:$rA))]>;
2074 // A-Form instructions. Most of the instructions executed in the FPU are of
2077 let PPC970_Unit = 3, neverHasSideEffects = 1 in { // FPU Operations.
2078 let Uses = [RM] in {
2079 defm FMADD : AForm_1r<63, 29,
2080 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2081 "fmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2082 [(set f64:$FRT, (fma f64:$FRA, f64:$FRC, f64:$FRB))]>;
2083 defm FMADDS : AForm_1r<59, 29,
2084 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2085 "fmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2086 [(set f32:$FRT, (fma f32:$FRA, f32:$FRC, f32:$FRB))]>;
2087 defm FMSUB : AForm_1r<63, 28,
2088 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2089 "fmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2091 (fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>;
2092 defm FMSUBS : AForm_1r<59, 28,
2093 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2094 "fmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2096 (fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>;
2097 defm FNMADD : AForm_1r<63, 31,
2098 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2099 "fnmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2101 (fneg (fma f64:$FRA, f64:$FRC, f64:$FRB)))]>;
2102 defm FNMADDS : AForm_1r<59, 31,
2103 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2104 "fnmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2106 (fneg (fma f32:$FRA, f32:$FRC, f32:$FRB)))]>;
2107 defm FNMSUB : AForm_1r<63, 30,
2108 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2109 "fnmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2110 [(set f64:$FRT, (fneg (fma f64:$FRA, f64:$FRC,
2111 (fneg f64:$FRB))))]>;
2112 defm FNMSUBS : AForm_1r<59, 30,
2113 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2114 "fnmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2115 [(set f32:$FRT, (fneg (fma f32:$FRA, f32:$FRC,
2116 (fneg f32:$FRB))))]>;
2118 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
2119 // having 4 of these, force the comparison to always be an 8-byte double (code
2120 // should use an FMRSD if the input comparison value really wants to be a float)
2121 // and 4/8 byte forms for the result and operand type..
2122 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2123 defm FSELD : AForm_1r<63, 23,
2124 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2125 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2126 [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>;
2127 defm FSELS : AForm_1r<63, 23,
2128 (outs f4rc:$FRT), (ins f8rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2129 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2130 [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>;
2131 let Uses = [RM] in {
2132 defm FADD : AForm_2r<63, 21,
2133 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2134 "fadd", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2135 [(set f64:$FRT, (fadd f64:$FRA, f64:$FRB))]>;
2136 defm FADDS : AForm_2r<59, 21,
2137 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2138 "fadds", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2139 [(set f32:$FRT, (fadd f32:$FRA, f32:$FRB))]>;
2140 defm FDIV : AForm_2r<63, 18,
2141 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2142 "fdiv", "$FRT, $FRA, $FRB", IIC_FPDivD,
2143 [(set f64:$FRT, (fdiv f64:$FRA, f64:$FRB))]>;
2144 defm FDIVS : AForm_2r<59, 18,
2145 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2146 "fdivs", "$FRT, $FRA, $FRB", IIC_FPDivS,
2147 [(set f32:$FRT, (fdiv f32:$FRA, f32:$FRB))]>;
2148 defm FMUL : AForm_3r<63, 25,
2149 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC),
2150 "fmul", "$FRT, $FRA, $FRC", IIC_FPFused,
2151 [(set f64:$FRT, (fmul f64:$FRA, f64:$FRC))]>;
2152 defm FMULS : AForm_3r<59, 25,
2153 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC),
2154 "fmuls", "$FRT, $FRA, $FRC", IIC_FPGeneral,
2155 [(set f32:$FRT, (fmul f32:$FRA, f32:$FRC))]>;
2156 defm FSUB : AForm_2r<63, 20,
2157 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2158 "fsub", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2159 [(set f64:$FRT, (fsub f64:$FRA, f64:$FRB))]>;
2160 defm FSUBS : AForm_2r<59, 20,
2161 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2162 "fsubs", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2163 [(set f32:$FRT, (fsub f32:$FRA, f32:$FRB))]>;
2167 let neverHasSideEffects = 1 in {
2168 let PPC970_Unit = 1 in { // FXU Operations.
2170 def ISEL : AForm_4<31, 15,
2171 (outs gprc:$rT), (ins gprc_nor0:$rA, gprc:$rB, crbitrc:$cond),
2172 "isel $rT, $rA, $rB, $cond", IIC_IntGeneral,
2176 let PPC970_Unit = 1 in { // FXU Operations.
2177 // M-Form instructions. rotate and mask instructions.
2179 let isCommutable = 1 in {
2180 // RLWIMI can be commuted if the rotate amount is zero.
2181 defm RLWIMI : MForm_2r<20, (outs gprc:$rA),
2182 (ins gprc:$rSi, gprc:$rS, u5imm:$SH, u5imm:$MB,
2183 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME",
2184 IIC_IntRotate, []>, PPC970_DGroup_Cracked,
2185 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">;
2187 let BaseName = "rlwinm" in {
2188 def RLWINM : MForm_2<21,
2189 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2190 "rlwinm $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
2193 def RLWINMo : MForm_2<21,
2194 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2195 "rlwinm. $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
2196 []>, isDOT, RecFormRel, PPC970_DGroup_Cracked;
2198 defm RLWNM : MForm_2r<23, (outs gprc:$rA),
2199 (ins gprc:$rS, gprc:$rB, u5imm:$MB, u5imm:$ME),
2200 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral,
2203 } // neverHasSideEffects = 1
2205 //===----------------------------------------------------------------------===//
2206 // PowerPC Instruction Patterns
2209 // Arbitrary immediate support. Implement in terms of LIS/ORI.
2210 def : Pat<(i32 imm:$imm),
2211 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
2213 // Implement the 'not' operation with the NOR instruction.
2214 def NOT : Pat<(not i32:$in),
2217 // ADD an arbitrary immediate.
2218 def : Pat<(add i32:$in, imm:$imm),
2219 (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
2220 // OR an arbitrary immediate.
2221 def : Pat<(or i32:$in, imm:$imm),
2222 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2223 // XOR an arbitrary immediate.
2224 def : Pat<(xor i32:$in, imm:$imm),
2225 (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2227 def : Pat<(sub imm32SExt16:$imm, i32:$in),
2228 (SUBFIC $in, imm:$imm)>;
2231 def : Pat<(shl i32:$in, (i32 imm:$imm)),
2232 (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>;
2233 def : Pat<(srl i32:$in, (i32 imm:$imm)),
2234 (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>;
2237 def : Pat<(rotl i32:$in, i32:$sh),
2238 (RLWNM $in, $sh, 0, 31)>;
2239 def : Pat<(rotl i32:$in, (i32 imm:$imm)),
2240 (RLWINM $in, imm:$imm, 0, 31)>;
2243 def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm),
2244 (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
2247 def : Pat<(PPCcall (i32 tglobaladdr:$dst)),
2248 (BL tglobaladdr:$dst)>;
2249 def : Pat<(PPCcall (i32 texternalsym:$dst)),
2250 (BL texternalsym:$dst)>;
2253 def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm),
2254 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
2256 def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
2257 (TCRETURNdi texternalsym:$dst, imm:$imm)>;
2259 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
2260 (TCRETURNri CTRRC:$dst, imm:$imm)>;
2264 // Hi and Lo for Darwin Global Addresses.
2265 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
2266 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
2267 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
2268 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
2269 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
2270 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
2271 def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>;
2272 def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>;
2273 def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in),
2274 (ADDIS $in, tglobaltlsaddr:$g)>;
2275 def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in),
2276 (ADDI $in, tglobaltlsaddr:$g)>;
2277 def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)),
2278 (ADDIS $in, tglobaladdr:$g)>;
2279 def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)),
2280 (ADDIS $in, tconstpool:$g)>;
2281 def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)),
2282 (ADDIS $in, tjumptable:$g)>;
2283 def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)),
2284 (ADDIS $in, tblockaddress:$g)>;
2286 // Support for thread-local storage.
2287 def PPC32GOT: Pseudo<(outs gprc:$rD), (ins), "#PPC32GOT",
2288 [(set i32:$rD, (PPCppc32GOT))]>;
2290 def LDgotTprelL32: Pseudo<(outs gprc:$rD), (ins s16imm:$disp, gprc_nor0:$reg),
2293 (PPCldGotTprelL tglobaltlsaddr:$disp, i32:$reg))]>;
2294 def : Pat<(PPCaddTls i32:$in, tglobaltlsaddr:$g),
2295 (ADD4TLS $in, tglobaltlsaddr:$g)>;
2297 // Standard shifts. These are represented separately from the real shifts above
2298 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
2300 def : Pat<(sra i32:$rS, i32:$rB),
2302 def : Pat<(srl i32:$rS, i32:$rB),
2304 def : Pat<(shl i32:$rS, i32:$rB),
2307 def : Pat<(zextloadi1 iaddr:$src),
2309 def : Pat<(zextloadi1 xaddr:$src),
2311 def : Pat<(extloadi1 iaddr:$src),
2313 def : Pat<(extloadi1 xaddr:$src),
2315 def : Pat<(extloadi8 iaddr:$src),
2317 def : Pat<(extloadi8 xaddr:$src),
2319 def : Pat<(extloadi16 iaddr:$src),
2321 def : Pat<(extloadi16 xaddr:$src),
2323 def : Pat<(f64 (extloadf32 iaddr:$src)),
2324 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
2325 def : Pat<(f64 (extloadf32 xaddr:$src)),
2326 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
2328 def : Pat<(f64 (fextend f32:$src)),
2329 (COPY_TO_REGCLASS $src, F8RC)>;
2331 def : Pat<(atomic_fence (imm), (imm)), (SYNC 0)>, Requires<[IsNotBookE]>;
2332 def : Pat<(atomic_fence (imm), (imm)), (MSYNC)>, Requires<[IsBookE]>;
2334 // Additional FNMSUB patterns: -a*c + b == -(a*c - b)
2335 def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),
2336 (FNMSUB $A, $C, $B)>;
2337 def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B),
2338 (FNMSUB $A, $C, $B)>;
2339 def : Pat<(fma (fneg f32:$A), f32:$C, f32:$B),
2340 (FNMSUBS $A, $C, $B)>;
2341 def : Pat<(fma f32:$A, (fneg f32:$C), f32:$B),
2342 (FNMSUBS $A, $C, $B)>;
2344 // FCOPYSIGN's operand types need not agree.
2345 def : Pat<(fcopysign f64:$frB, f32:$frA),
2346 (FCPSGND (COPY_TO_REGCLASS $frA, F8RC), $frB)>;
2347 def : Pat<(fcopysign f32:$frB, f64:$frA),
2348 (FCPSGNS (COPY_TO_REGCLASS $frA, F4RC), $frB)>;
2350 include "PPCInstrAltivec.td"
2351 include "PPCInstr64Bit.td"
2354 //===----------------------------------------------------------------------===//
2355 // PowerPC Instructions used for assembler/disassembler only
2358 def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins),
2359 "isync", IIC_SprISYNC, []>;
2361 def ICBI : XForm_1a<31, 982, (outs), (ins memrr:$src),
2362 "icbi $src", IIC_LdStICBI, []>;
2364 def EIEIO : XForm_24_eieio<31, 854, (outs), (ins),
2365 "eieio", IIC_LdStLoad, []>;
2367 def WAIT : XForm_24_sync<31, 62, (outs), (ins i32imm:$L),
2368 "wait $L", IIC_LdStLoad, []>;
2370 def MTMSR: XForm_mtmsr<31, 146, (outs), (ins gprc:$RS, i32imm:$L),
2371 "mtmsr $RS, $L", IIC_SprMTMSR>;
2373 def MFMSR : XForm_rs<31, 83, (outs gprc:$RT), (ins),
2374 "mfmsr $RT", IIC_SprMFMSR, []>;
2376 def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, i32imm:$L),
2377 "mtmsrd $RS, $L", IIC_SprMTMSRD>;
2379 def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB),
2380 "slbie $RB", IIC_SprSLBIE, []>;
2382 def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RS, gprc:$RB),
2383 "slbmte $RS, $RB", IIC_SprSLBMTE, []>;
2385 def SLBMFEE : XForm_26<31, 915, (outs gprc:$RT), (ins gprc:$RB),
2386 "slbmfee $RT, $RB", IIC_SprSLBMFEE, []>;
2388 def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", IIC_SprSLBIA, []>;
2390 def TLBSYNC : XForm_0<31, 566, (outs), (ins),
2391 "tlbsync", IIC_SprTLBSYNC, []>;
2393 def TLBIEL : XForm_16b<31, 274, (outs), (ins gprc:$RB),
2394 "tlbiel $RB", IIC_SprTLBIEL, []>;
2396 def TLBIE : XForm_26<31, 306, (outs), (ins gprc:$RS, gprc:$RB),
2397 "tlbie $RB,$RS", IIC_SprTLBIE, []>;
2399 //===----------------------------------------------------------------------===//
2400 // PowerPC Assembler Instruction Aliases
2403 // Pseudo-instructions for alternate assembly syntax (never used by codegen).
2404 // These are aliases that require C++ handling to convert to the target
2405 // instruction, while InstAliases can be handled directly by tblgen.
2406 class PPCAsmPseudo<string asm, dag iops>
2408 let Namespace = "PPC";
2409 bit PPC64 = 0; // Default value, override with isPPC64
2411 let OutOperandList = (outs);
2412 let InOperandList = iops;
2414 let AsmString = asm;
2415 let isAsmParserOnly = 1;
2419 def : InstAlias<"sc", (SC 0)>;
2421 def : InstAlias<"sync", (SYNC 0)>, Requires<[IsNotBookE]>;
2422 def : InstAlias<"msync", (SYNC 0)>, Requires<[IsNotBookE]>;
2423 def : InstAlias<"lwsync", (SYNC 1)>, Requires<[IsNotBookE]>;
2424 def : InstAlias<"ptesync", (SYNC 2)>, Requires<[IsNotBookE]>;
2426 def : InstAlias<"wait", (WAIT 0)>;
2427 def : InstAlias<"waitrsv", (WAIT 1)>;
2428 def : InstAlias<"waitimpl", (WAIT 2)>;
2430 def : InstAlias<"crset $bx", (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
2431 def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
2432 def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
2433 def : InstAlias<"crnot $bx, $by", (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
2435 def : InstAlias<"mtxer $Rx", (MTSPR 1, gprc:$Rx)>;
2436 def : InstAlias<"mfxer $Rx", (MFSPR gprc:$Rx, 1)>;
2438 def : InstAlias<"mftb $Rx", (MFTB gprc:$Rx, 268)>;
2439 def : InstAlias<"mftbu $Rx", (MFTB gprc:$Rx, 269)>;
2441 def : InstAlias<"xnop", (XORI R0, R0, 0)>;
2443 def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
2444 def : InstAlias<"mr. $rA, $rB", (OR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
2446 def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
2447 def : InstAlias<"not. $rA, $rB", (NOR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
2449 def : InstAlias<"mtcr $rA", (MTCRF8 255, g8rc:$rA)>;
2451 def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>;
2453 def SUBI : PPCAsmPseudo<"subi $rA, $rB, $imm",
2454 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
2455 def SUBIS : PPCAsmPseudo<"subis $rA, $rB, $imm",
2456 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
2457 def SUBIC : PPCAsmPseudo<"subic $rA, $rB, $imm",
2458 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
2459 def SUBICo : PPCAsmPseudo<"subic. $rA, $rB, $imm",
2460 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
2462 def : InstAlias<"sub $rA, $rB, $rC", (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
2463 def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
2464 def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
2465 def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
2467 def : InstAlias<"mtmsrd $RS", (MTMSRD gprc:$RS, 0)>;
2468 def : InstAlias<"mtmsr $RS", (MTMSR gprc:$RS, 0)>;
2470 def : InstAlias<"mfsprg $RT, 0", (MFSPR gprc:$RT, 272)>;
2471 def : InstAlias<"mfsprg $RT, 1", (MFSPR gprc:$RT, 273)>;
2472 def : InstAlias<"mfsprg $RT, 2", (MFSPR gprc:$RT, 274)>;
2473 def : InstAlias<"mfsprg $RT, 3", (MFSPR gprc:$RT, 275)>;
2475 def : InstAlias<"mfsprg0 $RT", (MFSPR gprc:$RT, 272)>;
2476 def : InstAlias<"mfsprg1 $RT", (MFSPR gprc:$RT, 273)>;
2477 def : InstAlias<"mfsprg2 $RT", (MFSPR gprc:$RT, 274)>;
2478 def : InstAlias<"mfsprg3 $RT", (MFSPR gprc:$RT, 275)>;
2480 def : InstAlias<"mtsprg 0, $RT", (MTSPR 272, gprc:$RT)>;
2481 def : InstAlias<"mtsprg 1, $RT", (MTSPR 273, gprc:$RT)>;
2482 def : InstAlias<"mtsprg 2, $RT", (MTSPR 274, gprc:$RT)>;
2483 def : InstAlias<"mtsprg 3, $RT", (MTSPR 275, gprc:$RT)>;
2485 def : InstAlias<"mtsprg0 $RT", (MTSPR 272, gprc:$RT)>;
2486 def : InstAlias<"mtsprg1 $RT", (MTSPR 273, gprc:$RT)>;
2487 def : InstAlias<"mtsprg2 $RT", (MTSPR 274, gprc:$RT)>;
2488 def : InstAlias<"mtsprg3 $RT", (MTSPR 275, gprc:$RT)>;
2490 def : InstAlias<"mtasr $RS", (MTSPR 280, gprc:$RS)>;
2492 def : InstAlias<"mfdec $RT", (MFSPR gprc:$RT, 22)>;
2493 def : InstAlias<"mtdec $RT", (MTSPR 22, gprc:$RT)>;
2495 def : InstAlias<"mfpvr $RT", (MFSPR gprc:$RT, 287)>;
2497 def : InstAlias<"mfsdr1 $RT", (MFSPR gprc:$RT, 25)>;
2498 def : InstAlias<"mtsdr1 $RT", (MTSPR 25, gprc:$RT)>;
2500 def : InstAlias<"mfsrr0 $RT", (MFSPR gprc:$RT, 26)>;
2501 def : InstAlias<"mfsrr1 $RT", (MFSPR gprc:$RT, 27)>;
2502 def : InstAlias<"mtsrr0 $RT", (MTSPR 26, gprc:$RT)>;
2503 def : InstAlias<"mtsrr1 $RT", (MTSPR 27, gprc:$RT)>;
2505 def : InstAlias<"tlbie $RB", (TLBIE R0, gprc:$RB)>;
2507 def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b",
2508 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
2509 def EXTLWIo : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b",
2510 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
2511 def EXTRWI : PPCAsmPseudo<"extrwi $rA, $rS, $n, $b",
2512 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
2513 def EXTRWIo : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b",
2514 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
2515 def INSLWI : PPCAsmPseudo<"inslwi $rA, $rS, $n, $b",
2516 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
2517 def INSLWIo : PPCAsmPseudo<"inslwi. $rA, $rS, $n, $b",
2518 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
2519 def INSRWI : PPCAsmPseudo<"insrwi $rA, $rS, $n, $b",
2520 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
2521 def INSRWIo : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b",
2522 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
2523 def ROTRWI : PPCAsmPseudo<"rotrwi $rA, $rS, $n",
2524 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
2525 def ROTRWIo : PPCAsmPseudo<"rotrwi. $rA, $rS, $n",
2526 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
2527 def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n",
2528 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
2529 def SLWIo : PPCAsmPseudo<"slwi. $rA, $rS, $n",
2530 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
2531 def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n",
2532 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
2533 def SRWIo : PPCAsmPseudo<"srwi. $rA, $rS, $n",
2534 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
2535 def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n",
2536 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
2537 def CLRRWIo : PPCAsmPseudo<"clrrwi. $rA, $rS, $n",
2538 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
2539 def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n",
2540 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
2541 def CLRLSLWIo : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n",
2542 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
2544 def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
2545 def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
2546 def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
2547 def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNMo gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
2548 def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
2549 def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
2551 def EXTLDI : PPCAsmPseudo<"extldi $rA, $rS, $n, $b",
2552 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
2553 def EXTLDIo : PPCAsmPseudo<"extldi. $rA, $rS, $n, $b",
2554 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
2555 def EXTRDI : PPCAsmPseudo<"extrdi $rA, $rS, $n, $b",
2556 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
2557 def EXTRDIo : PPCAsmPseudo<"extrdi. $rA, $rS, $n, $b",
2558 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
2559 def INSRDI : PPCAsmPseudo<"insrdi $rA, $rS, $n, $b",
2560 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
2561 def INSRDIo : PPCAsmPseudo<"insrdi. $rA, $rS, $n, $b",
2562 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
2563 def ROTRDI : PPCAsmPseudo<"rotrdi $rA, $rS, $n",
2564 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
2565 def ROTRDIo : PPCAsmPseudo<"rotrdi. $rA, $rS, $n",
2566 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
2567 def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n",
2568 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
2569 def SLDIo : PPCAsmPseudo<"sldi. $rA, $rS, $n",
2570 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
2571 def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n",
2572 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
2573 def SRDIo : PPCAsmPseudo<"srdi. $rA, $rS, $n",
2574 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
2575 def CLRRDI : PPCAsmPseudo<"clrrdi $rA, $rS, $n",
2576 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
2577 def CLRRDIo : PPCAsmPseudo<"clrrdi. $rA, $rS, $n",
2578 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
2579 def CLRLSLDI : PPCAsmPseudo<"clrlsldi $rA, $rS, $b, $n",
2580 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
2581 def CLRLSLDIo : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n",
2582 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
2584 def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
2585 def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
2586 def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
2587 def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCLo g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
2588 def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
2589 def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
2591 // These generic branch instruction forms are used for the assembler parser only.
2592 // Defs and Uses are conservative, since we don't know the BO value.
2593 let PPC970_Unit = 7 in {
2594 let Defs = [CTR], Uses = [CTR, RM] in {
2595 def gBC : BForm_3<16, 0, 0, (outs),
2596 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
2597 "bc $bo, $bi, $dst">;
2598 def gBCA : BForm_3<16, 1, 0, (outs),
2599 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
2600 "bca $bo, $bi, $dst">;
2602 let Defs = [LR, CTR], Uses = [CTR, RM] in {
2603 def gBCL : BForm_3<16, 0, 1, (outs),
2604 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
2605 "bcl $bo, $bi, $dst">;
2606 def gBCLA : BForm_3<16, 1, 1, (outs),
2607 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
2608 "bcla $bo, $bi, $dst">;
2610 let Defs = [CTR], Uses = [CTR, LR, RM] in
2611 def gBCLR : XLForm_2<19, 16, 0, (outs),
2612 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
2613 "bclr $bo, $bi, $bh", IIC_BrB, []>;
2614 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
2615 def gBCLRL : XLForm_2<19, 16, 1, (outs),
2616 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
2617 "bclrl $bo, $bi, $bh", IIC_BrB, []>;
2618 let Defs = [CTR], Uses = [CTR, LR, RM] in
2619 def gBCCTR : XLForm_2<19, 528, 0, (outs),
2620 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
2621 "bcctr $bo, $bi, $bh", IIC_BrB, []>;
2622 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
2623 def gBCCTRL : XLForm_2<19, 528, 1, (outs),
2624 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
2625 "bcctrl $bo, $bi, $bh", IIC_BrB, []>;
2627 def : InstAlias<"bclr $bo, $bi", (gBCLR u5imm:$bo, crbitrc:$bi, 0)>;
2628 def : InstAlias<"bclrl $bo, $bi", (gBCLRL u5imm:$bo, crbitrc:$bi, 0)>;
2629 def : InstAlias<"bcctr $bo, $bi", (gBCCTR u5imm:$bo, crbitrc:$bi, 0)>;
2630 def : InstAlias<"bcctrl $bo, $bi", (gBCCTRL u5imm:$bo, crbitrc:$bi, 0)>;
2632 multiclass BranchSimpleMnemonic1<string name, string pm, int bo> {
2633 def : InstAlias<"b"#name#pm#" $bi, $dst", (gBC bo, crbitrc:$bi, condbrtarget:$dst)>;
2634 def : InstAlias<"b"#name#"a"#pm#" $bi, $dst", (gBCA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
2635 def : InstAlias<"b"#name#"lr"#pm#" $bi", (gBCLR bo, crbitrc:$bi, 0)>;
2636 def : InstAlias<"b"#name#"l"#pm#" $bi, $dst", (gBCL bo, crbitrc:$bi, condbrtarget:$dst)>;
2637 def : InstAlias<"b"#name#"la"#pm#" $bi, $dst", (gBCLA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
2638 def : InstAlias<"b"#name#"lrl"#pm#" $bi", (gBCLRL bo, crbitrc:$bi, 0)>;
2640 multiclass BranchSimpleMnemonic2<string name, string pm, int bo>
2641 : BranchSimpleMnemonic1<name, pm, bo> {
2642 def : InstAlias<"b"#name#"ctr"#pm#" $bi", (gBCCTR bo, crbitrc:$bi, 0)>;
2643 def : InstAlias<"b"#name#"ctrl"#pm#" $bi", (gBCCTRL bo, crbitrc:$bi, 0)>;
2645 defm : BranchSimpleMnemonic2<"t", "", 12>;
2646 defm : BranchSimpleMnemonic2<"f", "", 4>;
2647 defm : BranchSimpleMnemonic2<"t", "-", 14>;
2648 defm : BranchSimpleMnemonic2<"f", "-", 6>;
2649 defm : BranchSimpleMnemonic2<"t", "+", 15>;
2650 defm : BranchSimpleMnemonic2<"f", "+", 7>;
2651 defm : BranchSimpleMnemonic1<"dnzt", "", 8>;
2652 defm : BranchSimpleMnemonic1<"dnzf", "", 0>;
2653 defm : BranchSimpleMnemonic1<"dzt", "", 10>;
2654 defm : BranchSimpleMnemonic1<"dzf", "", 2>;
2656 multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> {
2657 def : InstAlias<"b"#name#pm#" $cc, $dst",
2658 (BCC bibo, crrc:$cc, condbrtarget:$dst)>;
2659 def : InstAlias<"b"#name#pm#" $dst",
2660 (BCC bibo, CR0, condbrtarget:$dst)>;
2662 def : InstAlias<"b"#name#"a"#pm#" $cc, $dst",
2663 (BCCA bibo, crrc:$cc, abscondbrtarget:$dst)>;
2664 def : InstAlias<"b"#name#"a"#pm#" $dst",
2665 (BCCA bibo, CR0, abscondbrtarget:$dst)>;
2667 def : InstAlias<"b"#name#"lr"#pm#" $cc",
2668 (BCLR bibo, crrc:$cc)>;
2669 def : InstAlias<"b"#name#"lr"#pm,
2672 def : InstAlias<"b"#name#"ctr"#pm#" $cc",
2673 (BCCTR bibo, crrc:$cc)>;
2674 def : InstAlias<"b"#name#"ctr"#pm,
2677 def : InstAlias<"b"#name#"l"#pm#" $cc, $dst",
2678 (BCCL bibo, crrc:$cc, condbrtarget:$dst)>;
2679 def : InstAlias<"b"#name#"l"#pm#" $dst",
2680 (BCCL bibo, CR0, condbrtarget:$dst)>;
2682 def : InstAlias<"b"#name#"la"#pm#" $cc, $dst",
2683 (BCCLA bibo, crrc:$cc, abscondbrtarget:$dst)>;
2684 def : InstAlias<"b"#name#"la"#pm#" $dst",
2685 (BCCLA bibo, CR0, abscondbrtarget:$dst)>;
2687 def : InstAlias<"b"#name#"lrl"#pm#" $cc",
2688 (BCLRL bibo, crrc:$cc)>;
2689 def : InstAlias<"b"#name#"lrl"#pm,
2692 def : InstAlias<"b"#name#"ctrl"#pm#" $cc",
2693 (BCCTRL bibo, crrc:$cc)>;
2694 def : InstAlias<"b"#name#"ctrl"#pm,
2695 (BCCTRL bibo, CR0)>;
2697 multiclass BranchExtendedMnemonic<string name, int bibo> {
2698 defm : BranchExtendedMnemonicPM<name, "", bibo>;
2699 defm : BranchExtendedMnemonicPM<name, "-", !add(bibo, 2)>;
2700 defm : BranchExtendedMnemonicPM<name, "+", !add(bibo, 3)>;
2702 defm : BranchExtendedMnemonic<"lt", 12>;
2703 defm : BranchExtendedMnemonic<"gt", 44>;
2704 defm : BranchExtendedMnemonic<"eq", 76>;
2705 defm : BranchExtendedMnemonic<"un", 108>;
2706 defm : BranchExtendedMnemonic<"so", 108>;
2707 defm : BranchExtendedMnemonic<"ge", 4>;
2708 defm : BranchExtendedMnemonic<"nl", 4>;
2709 defm : BranchExtendedMnemonic<"le", 36>;
2710 defm : BranchExtendedMnemonic<"ng", 36>;
2711 defm : BranchExtendedMnemonic<"ne", 68>;
2712 defm : BranchExtendedMnemonic<"nu", 100>;
2713 defm : BranchExtendedMnemonic<"ns", 100>;
2715 def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>;
2716 def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>;
2717 def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>;
2718 def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>;
2719 def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm64:$imm)>;
2720 def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>;
2721 def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm64:$imm)>;
2722 def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>;
2724 def : InstAlias<"cmpi $bf, 0, $rA, $imm", (CMPWI crrc:$bf, gprc:$rA, s16imm:$imm)>;
2725 def : InstAlias<"cmp $bf, 0, $rA, $rB", (CMPW crrc:$bf, gprc:$rA, gprc:$rB)>;
2726 def : InstAlias<"cmpli $bf, 0, $rA, $imm", (CMPLWI crrc:$bf, gprc:$rA, u16imm:$imm)>;
2727 def : InstAlias<"cmpl $bf, 0, $rA, $rB", (CMPLW crrc:$bf, gprc:$rA, gprc:$rB)>;
2728 def : InstAlias<"cmpi $bf, 1, $rA, $imm", (CMPDI crrc:$bf, g8rc:$rA, s16imm64:$imm)>;
2729 def : InstAlias<"cmp $bf, 1, $rA, $rB", (CMPD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
2730 def : InstAlias<"cmpli $bf, 1, $rA, $imm", (CMPLDI crrc:$bf, g8rc:$rA, u16imm64:$imm)>;
2731 def : InstAlias<"cmpl $bf, 1, $rA, $rB", (CMPLD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
2733 multiclass TrapExtendedMnemonic<string name, int to> {
2734 def : InstAlias<"td"#name#"i $rA, $imm", (TDI to, g8rc:$rA, s16imm:$imm)>;
2735 def : InstAlias<"td"#name#" $rA, $rB", (TD to, g8rc:$rA, g8rc:$rB)>;
2736 def : InstAlias<"tw"#name#"i $rA, $imm", (TWI to, gprc:$rA, s16imm:$imm)>;
2737 def : InstAlias<"tw"#name#" $rA, $rB", (TW to, gprc:$rA, gprc:$rB)>;
2739 defm : TrapExtendedMnemonic<"lt", 16>;
2740 defm : TrapExtendedMnemonic<"le", 20>;
2741 defm : TrapExtendedMnemonic<"eq", 4>;
2742 defm : TrapExtendedMnemonic<"ge", 12>;
2743 defm : TrapExtendedMnemonic<"gt", 8>;
2744 defm : TrapExtendedMnemonic<"nl", 12>;
2745 defm : TrapExtendedMnemonic<"ne", 24>;
2746 defm : TrapExtendedMnemonic<"ng", 20>;
2747 defm : TrapExtendedMnemonic<"llt", 2>;
2748 defm : TrapExtendedMnemonic<"lle", 6>;
2749 defm : TrapExtendedMnemonic<"lge", 5>;
2750 defm : TrapExtendedMnemonic<"lgt", 1>;
2751 defm : TrapExtendedMnemonic<"lnl", 5>;
2752 defm : TrapExtendedMnemonic<"lng", 6>;
2753 defm : TrapExtendedMnemonic<"u", 31>;