1 //===-- PPCJITInfo.cpp - Implement the JIT interfaces for the PowerPC -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the JIT interfaces for the 32-bit PowerPC target.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "jit"
15 #include "PPCJITInfo.h"
16 #include "PPCRelocations.h"
17 #include "PPCTargetMachine.h"
18 #include "llvm/IR/Function.h"
19 #include "llvm/Support/Debug.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include "llvm/Support/Memory.h"
22 #include "llvm/Support/raw_ostream.h"
25 static TargetJITInfo::JITCompilerFn JITCompilerFunction;
27 #define BUILD_ADDIS(RD,RS,IMM16) \
28 ((15 << 26) | ((RD) << 21) | ((RS) << 16) | ((IMM16) & 65535))
29 #define BUILD_ORI(RD,RS,UIMM16) \
30 ((24 << 26) | ((RS) << 21) | ((RD) << 16) | ((UIMM16) & 65535))
31 #define BUILD_ORIS(RD,RS,UIMM16) \
32 ((25 << 26) | ((RS) << 21) | ((RD) << 16) | ((UIMM16) & 65535))
33 #define BUILD_RLDICR(RD,RS,SH,ME) \
34 ((30 << 26) | ((RS) << 21) | ((RD) << 16) | (((SH) & 31) << 11) | \
35 (((ME) & 63) << 6) | (1 << 2) | ((((SH) >> 5) & 1) << 1))
36 #define BUILD_MTSPR(RS,SPR) \
37 ((31 << 26) | ((RS) << 21) | ((SPR) << 16) | (467 << 1))
38 #define BUILD_BCCTRx(BO,BI,LINK) \
39 ((19 << 26) | ((BO) << 21) | ((BI) << 16) | (528 << 1) | ((LINK) & 1))
40 #define BUILD_B(TARGET, LINK) \
41 ((18 << 26) | (((TARGET) & 0x00FFFFFF) << 2) | ((LINK) & 1))
44 #define BUILD_LIS(RD,IMM16) BUILD_ADDIS(RD,0,IMM16)
45 #define BUILD_SLDI(RD,RS,IMM6) BUILD_RLDICR(RD,RS,IMM6,63-IMM6)
46 #define BUILD_MTCTR(RS) BUILD_MTSPR(RS,9)
47 #define BUILD_BCTR(LINK) BUILD_BCCTRx(20,0,LINK)
49 static void EmitBranchToAt(uint64_t At, uint64_t To, bool isCall, bool is64Bit){
50 intptr_t Offset = ((intptr_t)To - (intptr_t)At) >> 2;
51 unsigned *AtI = (unsigned*)(intptr_t)At;
53 if (Offset >= -(1 << 23) && Offset < (1 << 23)) { // In range?
54 AtI[0] = BUILD_B(Offset, isCall); // b/bl target
55 } else if (!is64Bit) {
56 AtI[0] = BUILD_LIS(12, To >> 16); // lis r12, hi16(address)
57 AtI[1] = BUILD_ORI(12, 12, To); // ori r12, r12, lo16(address)
58 AtI[2] = BUILD_MTCTR(12); // mtctr r12
59 AtI[3] = BUILD_BCTR(isCall); // bctr/bctrl
61 AtI[0] = BUILD_LIS(12, To >> 48); // lis r12, hi16(address)
62 AtI[1] = BUILD_ORI(12, 12, To >> 32); // ori r12, r12, lo16(address)
63 AtI[2] = BUILD_SLDI(12, 12, 32); // sldi r12, r12, 32
64 AtI[3] = BUILD_ORIS(12, 12, To >> 16); // oris r12, r12, hi16(address)
65 AtI[4] = BUILD_ORI(12, 12, To); // ori r12, r12, lo16(address)
66 AtI[5] = BUILD_MTCTR(12); // mtctr r12
67 AtI[6] = BUILD_BCTR(isCall); // bctr/bctrl
71 extern "C" void PPC32CompilationCallback();
72 extern "C" void PPC64CompilationCallback();
74 #if !defined(__powerpc__) || defined(__powerpc64__)
75 void PPC32CompilationCallback() {
76 llvm_unreachable("This is not a 32bit PowerPC, you can't execute this!");
78 #elif !defined(__ELF__)
79 // CompilationCallback stub - We can't use a C function with inline assembly in
80 // it, because we the prolog/epilog inserted by GCC won't work for us. Instead,
81 // write our own wrapper, which does things our way, so we have complete control
82 // over register saving and restoring.
86 ".globl _PPC32CompilationCallback\n"
87 "_PPC32CompilationCallback:\n"
88 // Make space for 8 ints r[3-10] and 13 doubles f[1-13] and the
89 // FIXME: need to save v[0-19] for altivec?
90 // FIXME: could shrink frame
91 // Set up a proper stack frame
93 // PowerPC32 ABI linkage - 24 bytes
94 // parameters - 32 bytes
95 // 13 double registers - 104 bytes
96 // 8 int registers - 32 bytes
100 // Save all int arg registers
101 "stw r10, 204(r1)\n" "stw r9, 200(r1)\n"
102 "stw r8, 196(r1)\n" "stw r7, 192(r1)\n"
103 "stw r6, 188(r1)\n" "stw r5, 184(r1)\n"
104 "stw r4, 180(r1)\n" "stw r3, 176(r1)\n"
105 // Save all call-clobbered FP regs.
106 "stfd f13, 168(r1)\n" "stfd f12, 160(r1)\n"
107 "stfd f11, 152(r1)\n" "stfd f10, 144(r1)\n"
108 "stfd f9, 136(r1)\n" "stfd f8, 128(r1)\n"
109 "stfd f7, 120(r1)\n" "stfd f6, 112(r1)\n"
110 "stfd f5, 104(r1)\n" "stfd f4, 96(r1)\n"
111 "stfd f3, 88(r1)\n" "stfd f2, 80(r1)\n"
113 // Arguments to Compilation Callback:
114 // r3 - our lr (address of the call instruction in stub plus 4)
115 // r4 - stub's lr (address of instruction that called the stub plus 4)
116 // r5 - is64Bit - always 0.
118 "lwz r2, 208(r1)\n" // stub's frame
119 "lwz r4, 8(r2)\n" // stub's lr
120 "li r5, 0\n" // 0 == 32 bit
121 "bl _LLVMPPCCompilationCallback\n"
123 // Restore all int arg registers
124 "lwz r10, 204(r1)\n" "lwz r9, 200(r1)\n"
125 "lwz r8, 196(r1)\n" "lwz r7, 192(r1)\n"
126 "lwz r6, 188(r1)\n" "lwz r5, 184(r1)\n"
127 "lwz r4, 180(r1)\n" "lwz r3, 176(r1)\n"
128 // Restore all FP arg registers
129 "lfd f13, 168(r1)\n" "lfd f12, 160(r1)\n"
130 "lfd f11, 152(r1)\n" "lfd f10, 144(r1)\n"
131 "lfd f9, 136(r1)\n" "lfd f8, 128(r1)\n"
132 "lfd f7, 120(r1)\n" "lfd f6, 112(r1)\n"
133 "lfd f5, 104(r1)\n" "lfd f4, 96(r1)\n"
134 "lfd f3, 88(r1)\n" "lfd f2, 80(r1)\n"
136 // Pop 3 frames off the stack and branch to target
144 // ELF PPC 32 support
146 // CompilationCallback stub - We can't use a C function with inline assembly in
147 // it, because we the prolog/epilog inserted by GCC won't work for us. Instead,
148 // write our own wrapper, which does things our way, so we have complete control
149 // over register saving and restoring.
153 ".globl PPC32CompilationCallback\n"
154 "PPC32CompilationCallback:\n"
155 // Make space for 8 ints r[3-10] and 8 doubles f[1-8] and the
156 // FIXME: need to save v[0-19] for altivec?
157 // FIXME: could shrink frame
158 // Set up a proper stack frame
160 // 8 double registers - 64 bytes
161 // 8 int registers - 32 bytes
165 // Save all int arg registers
166 "stw 10, 100(1)\n" "stw 9, 96(1)\n"
167 "stw 8, 92(1)\n" "stw 7, 88(1)\n"
168 "stw 6, 84(1)\n" "stw 5, 80(1)\n"
169 "stw 4, 76(1)\n" "stw 3, 72(1)\n"
170 // Save all call-clobbered FP regs.
172 "stfd 7, 56(1)\n" "stfd 6, 48(1)\n"
173 "stfd 5, 40(1)\n" "stfd 4, 32(1)\n"
174 "stfd 3, 24(1)\n" "stfd 2, 16(1)\n"
176 // Arguments to Compilation Callback:
177 // r3 - our lr (address of the call instruction in stub plus 4)
178 // r4 - stub's lr (address of instruction that called the stub plus 4)
179 // r5 - is64Bit - always 0.
181 "lwz 5, 104(1)\n" // stub's frame
182 "lwz 4, 4(5)\n" // stub's lr
183 "li 5, 0\n" // 0 == 32 bit
184 "bl LLVMPPCCompilationCallback\n"
186 // Restore all int arg registers
187 "lwz 10, 100(1)\n" "lwz 9, 96(1)\n"
188 "lwz 8, 92(1)\n" "lwz 7, 88(1)\n"
189 "lwz 6, 84(1)\n" "lwz 5, 80(1)\n"
190 "lwz 4, 76(1)\n" "lwz 3, 72(1)\n"
191 // Restore all FP arg registers
193 "lfd 7, 56(1)\n" "lfd 6, 48(1)\n"
194 "lfd 5, 40(1)\n" "lfd 4, 32(1)\n"
195 "lfd 3, 24(1)\n" "lfd 2, 16(1)\n"
197 // Pop 3 frames off the stack and branch to target
205 #ifndef __powerpc64__
206 void PPC64CompilationCallback() {
207 llvm_unreachable("This is not a 64bit PowerPC, you can't execute this!");
214 ".globl PPC64CompilationCallback\n"
215 ".section \".opd\",\"aw\",@progbits\n"
217 "PPC64CompilationCallback:\n"
218 ".quad .L.PPC64CompilationCallback,.TOC.@tocbase,0\n"
219 ".size PPC64CompilationCallback,24\n"
222 ".type PPC64CompilationCallback,@function\n"
223 ".L.PPC64CompilationCallback:\n"
228 ".globl _PPC64CompilationCallback\n"
229 "_PPC64CompilationCallback:\n"
231 // Make space for 8 ints r[3-10] and 13 doubles f[1-13] and the
232 // FIXME: need to save v[0-19] for altivec?
233 // Set up a proper stack frame
235 // PowerPC64 ABI linkage - 48 bytes
236 // parameters - 64 bytes
237 // 13 double registers - 104 bytes
238 // 8 int registers - 64 bytes
242 // Save all int arg registers
243 "std 10, 272(1)\n" "std 9, 264(1)\n"
244 "std 8, 256(1)\n" "std 7, 248(1)\n"
245 "std 6, 240(1)\n" "std 5, 232(1)\n"
246 "std 4, 224(1)\n" "std 3, 216(1)\n"
247 // Save all call-clobbered FP regs.
248 "stfd 13, 208(1)\n" "stfd 12, 200(1)\n"
249 "stfd 11, 192(1)\n" "stfd 10, 184(1)\n"
250 "stfd 9, 176(1)\n" "stfd 8, 168(1)\n"
251 "stfd 7, 160(1)\n" "stfd 6, 152(1)\n"
252 "stfd 5, 144(1)\n" "stfd 4, 136(1)\n"
253 "stfd 3, 128(1)\n" "stfd 2, 120(1)\n"
255 // Arguments to Compilation Callback:
256 // r3 - our lr (address of the call instruction in stub plus 4)
257 // r4 - stub's lr (address of instruction that called the stub plus 4)
258 // r5 - is64Bit - always 1.
259 "mr 3, 0\n" // return address (still in r0)
260 "ld 5, 280(1)\n" // stub's frame
261 "ld 4, 16(5)\n" // stub's lr
262 "li 5, 1\n" // 1 == 64 bit
264 "bl LLVMPPCCompilationCallback\n"
267 "bl _LLVMPPCCompilationCallback\n"
270 // Restore all int arg registers
271 "ld 10, 272(1)\n" "ld 9, 264(1)\n"
272 "ld 8, 256(1)\n" "ld 7, 248(1)\n"
273 "ld 6, 240(1)\n" "ld 5, 232(1)\n"
274 "ld 4, 224(1)\n" "ld 3, 216(1)\n"
275 // Restore all FP arg registers
276 "lfd 13, 208(1)\n" "lfd 12, 200(1)\n"
277 "lfd 11, 192(1)\n" "lfd 10, 184(1)\n"
278 "lfd 9, 176(1)\n" "lfd 8, 168(1)\n"
279 "lfd 7, 160(1)\n" "lfd 6, 152(1)\n"
280 "lfd 5, 144(1)\n" "lfd 4, 136(1)\n"
281 "lfd 3, 128(1)\n" "lfd 2, 120(1)\n"
283 // Pop 3 frames off the stack and branch to target
287 // XXX: any special TOC handling in the ELF case for JIT?
293 LLVM_LIBRARY_VISIBILITY void *
294 LLVMPPCCompilationCallback(unsigned *StubCallAddrPlus4,
295 unsigned *OrigCallAddrPlus4,
297 // Adjust the pointer to the address of the call instruction in the stub
298 // emitted by emitFunctionStub, rather than the instruction after it.
299 unsigned *StubCallAddr = StubCallAddrPlus4 - 1;
300 unsigned *OrigCallAddr = OrigCallAddrPlus4 - 1;
302 void *Target = JITCompilerFunction(StubCallAddr);
304 // Check to see if *OrigCallAddr is a 'bl' instruction, and if we can rewrite
305 // it to branch directly to the destination. If so, rewrite it so it does not
306 // need to go through the stub anymore.
307 unsigned OrigCallInst = *OrigCallAddr;
308 if ((OrigCallInst >> 26) == 18) { // Direct call.
309 intptr_t Offset = ((intptr_t)Target - (intptr_t)OrigCallAddr) >> 2;
311 if (Offset >= -(1 << 23) && Offset < (1 << 23)) { // In range?
312 // Clear the original target out.
313 OrigCallInst &= (63 << 26) | 3;
314 // Fill in the new target.
315 OrigCallInst |= (Offset & ((1 << 24)-1)) << 2;
317 *OrigCallAddr = OrigCallInst;
321 // Assert that we are coming from a stub that was created with our
323 if ((*StubCallAddr >> 26) == 18)
326 assert((*StubCallAddr >> 26) == 19 && "Call in stub is not indirect!");
327 StubCallAddr -= is64Bit ? 9 : 6;
330 // Rewrite the stub with an unconditional branch to the target, for any users
331 // who took the address of the stub.
332 EmitBranchToAt((intptr_t)StubCallAddr, (intptr_t)Target, false, is64Bit);
333 sys::Memory::InvalidateInstructionCache(StubCallAddr, 7*4);
335 // Put the address of the target function to call and the address to return to
336 // after calling the target function in a place that is easy to get on the
337 // stack after we restore all regs.
344 TargetJITInfo::LazyResolverFn
345 PPCJITInfo::getLazyResolverFunction(JITCompilerFn Fn) {
346 JITCompilerFunction = Fn;
347 return is64Bit ? PPC64CompilationCallback : PPC32CompilationCallback;
350 TargetJITInfo::StubLayout PPCJITInfo::getStubLayout() {
351 // The stub contains up to 10 4-byte instructions, aligned at 4 bytes: 3
352 // instructions to save the caller's address if this is a lazy-compilation
353 // stub, plus a 1-, 4-, or 7-instruction sequence to load an arbitrary address
354 // into a register and jump through it.
355 StubLayout Result = {10*4, 4};
359 #if (defined(__POWERPC__) || defined (__ppc__) || defined(_POWER)) && \
361 extern "C" void sys_icache_invalidate(const void *Addr, size_t len);
364 void *PPCJITInfo::emitFunctionStub(const Function* F, void *Fn,
365 JITCodeEmitter &JCE) {
366 // If this is just a call to an external function, emit a branch instead of a
367 // call. The code is the same except for one bit of the last instruction.
368 if (Fn != (void*)(intptr_t)PPC32CompilationCallback &&
369 Fn != (void*)(intptr_t)PPC64CompilationCallback) {
370 void *Addr = (void*)JCE.getCurrentPCValue();
378 EmitBranchToAt((intptr_t)Addr, (intptr_t)Fn, false, is64Bit);
379 sys::Memory::InvalidateInstructionCache(Addr, 7*4);
383 void *Addr = (void*)JCE.getCurrentPCValue();
385 JCE.emitWordBE(0xf821ffb1); // stdu r1,-80(r1)
386 JCE.emitWordBE(0x7d6802a6); // mflr r11
387 JCE.emitWordBE(0xf9610060); // std r11, 96(r1)
388 } else if (TM.getSubtargetImpl()->isDarwinABI()){
389 JCE.emitWordBE(0x9421ffe0); // stwu r1,-32(r1)
390 JCE.emitWordBE(0x7d6802a6); // mflr r11
391 JCE.emitWordBE(0x91610028); // stw r11, 40(r1)
393 JCE.emitWordBE(0x9421ffe0); // stwu r1,-32(r1)
394 JCE.emitWordBE(0x7d6802a6); // mflr r11
395 JCE.emitWordBE(0x91610024); // stw r11, 36(r1)
397 intptr_t BranchAddr = (intptr_t)JCE.getCurrentPCValue();
405 EmitBranchToAt(BranchAddr, (intptr_t)Fn, true, is64Bit);
406 sys::Memory::InvalidateInstructionCache(Addr, 10*4);
411 void PPCJITInfo::relocate(void *Function, MachineRelocation *MR,
412 unsigned NumRelocs, unsigned char* GOTBase) {
413 for (unsigned i = 0; i != NumRelocs; ++i, ++MR) {
414 unsigned *RelocPos = (unsigned*)Function + MR->getMachineCodeOffset()/4;
415 intptr_t ResultPtr = (intptr_t)MR->getResultPointer();
416 switch ((PPC::RelocationType)MR->getRelocationType()) {
417 default: llvm_unreachable("Unknown relocation type!");
418 case PPC::reloc_pcrel_bx:
419 // PC-relative relocation for b and bl instructions.
420 ResultPtr = (ResultPtr-(intptr_t)RelocPos) >> 2;
421 assert(ResultPtr >= -(1 << 23) && ResultPtr < (1 << 23) &&
422 "Relocation out of range!");
423 *RelocPos |= (ResultPtr & ((1 << 24)-1)) << 2;
425 case PPC::reloc_pcrel_bcx:
426 // PC-relative relocation for BLT,BLE,BEQ,BGE,BGT,BNE, or other
428 ResultPtr = (ResultPtr-(intptr_t)RelocPos) >> 2;
429 assert(ResultPtr >= -(1 << 13) && ResultPtr < (1 << 13) &&
430 "Relocation out of range!");
431 *RelocPos |= (ResultPtr & ((1 << 14)-1)) << 2;
433 case PPC::reloc_absolute_high: // high bits of ref -> low 16 of instr
434 case PPC::reloc_absolute_low: { // low bits of ref -> low 16 of instr
435 ResultPtr += MR->getConstantVal();
437 // If this is a high-part access, get the high-part.
438 if (MR->getRelocationType() == PPC::reloc_absolute_high) {
439 // If the low part will have a carry (really a borrow) from the low
440 // 16-bits into the high 16, add a bit to borrow from.
441 if (((int)ResultPtr << 16) < 0)
442 ResultPtr += 1 << 16;
446 // Do the addition then mask, so the addition does not overflow the 16-bit
447 // immediate section of the instruction.
448 unsigned LowBits = (*RelocPos + ResultPtr) & 65535;
449 unsigned HighBits = *RelocPos & ~65535;
450 *RelocPos = LowBits | HighBits; // Slam into low 16-bits
453 case PPC::reloc_absolute_low_ix: { // low bits of ref -> low 14 of instr
454 ResultPtr += MR->getConstantVal();
455 // Do the addition then mask, so the addition does not overflow the 16-bit
456 // immediate section of the instruction.
457 unsigned LowBits = (*RelocPos + ResultPtr) & 0xFFFC;
458 unsigned HighBits = *RelocPos & 0xFFFF0003;
459 *RelocPos = LowBits | HighBits; // Slam into low 14-bits.
466 void PPCJITInfo::replaceMachineCodeForFunction(void *Old, void *New) {
467 EmitBranchToAt((intptr_t)Old, (intptr_t)New, false, is64Bit);
468 sys::Memory::InvalidateInstructionCache(Old, 7*4);