1 //===-- PPCMCCodeEmitter.cpp - Convert PPC code to machine code -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mccodeemitter"
16 #include "PPCRegisterInfo.h"
17 #include "PPCFixupKinds.h"
18 #include "llvm/MC/MCCodeEmitter.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/ADT/Statistic.h"
21 #include "llvm/Support/raw_ostream.h"
22 #include "llvm/Support/ErrorHandling.h"
25 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
28 class PPCMCCodeEmitter : public MCCodeEmitter {
29 PPCMCCodeEmitter(const PPCMCCodeEmitter &); // DO NOT IMPLEMENT
30 void operator=(const PPCMCCodeEmitter &); // DO NOT IMPLEMENT
31 const TargetMachine &TM;
35 PPCMCCodeEmitter(TargetMachine &tm, MCContext &ctx)
39 ~PPCMCCodeEmitter() {}
41 unsigned getNumFixupKinds() const { return PPC::NumTargetFixupKinds; }
43 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
44 const static MCFixupKindInfo Infos[] = {
45 // name offset bits flags
46 { "fixup_ppc_br24", 6, 24, MCFixupKindInfo::FKF_IsPCRel },
47 { "fixup_ppc_brcond14", 16, 14, MCFixupKindInfo::FKF_IsPCRel }
50 if (Kind < FirstTargetFixupKind)
51 return MCCodeEmitter::getFixupKindInfo(Kind);
53 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
55 return Infos[Kind - FirstTargetFixupKind];
58 unsigned getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
59 SmallVectorImpl<MCFixup> &Fixups) const;
61 unsigned getCondBrEncoding(const MCInst &MI, unsigned OpNo,
62 SmallVectorImpl<MCFixup> &Fixups) const;
64 unsigned get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
65 SmallVectorImpl<MCFixup> &Fixups) const;
67 /// getMachineOpValue - Return binary encoding of operand. If the machine
68 /// operand requires relocation, record the relocation and return zero.
69 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
70 SmallVectorImpl<MCFixup> &Fixups) const;
72 // getBinaryCodeForInstr - TableGen'erated function for getting the
73 // binary encoding for an instruction.
74 unsigned getBinaryCodeForInstr(const MCInst &MI,
75 SmallVectorImpl<MCFixup> &Fixups) const;
76 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
77 SmallVectorImpl<MCFixup> &Fixups) const {
78 unsigned Bits = getBinaryCodeForInstr(MI, Fixups);
80 // Output the constant in big endian byte order.
81 for (unsigned i = 0; i != 4; ++i) {
82 OS << (char)(Bits >> 24);
86 ++MCNumEmitted; // Keep track of the # of mi's emitted.
91 } // end anonymous namespace
93 MCCodeEmitter *llvm::createPPCMCCodeEmitter(const Target &, TargetMachine &TM,
95 return new PPCMCCodeEmitter(TM, Ctx);
98 unsigned PPCMCCodeEmitter::
99 getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
100 SmallVectorImpl<MCFixup> &Fixups) const {
101 const MCOperand &MO = MI.getOperand(OpNo);
102 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
104 // Add a fixup for the branch target.
105 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
106 (MCFixupKind)PPC::fixup_ppc_br24));
110 unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo,
111 SmallVectorImpl<MCFixup> &Fixups) const {
112 const MCOperand &MO = MI.getOperand(OpNo);
113 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
115 // Add a fixup for the branch target.
116 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
117 (MCFixupKind)PPC::fixup_ppc_brcond14));
122 unsigned PPCMCCodeEmitter::
123 get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
124 SmallVectorImpl<MCFixup> &Fixups) const {
125 const MCOperand &MO = MI.getOperand(OpNo);
126 assert((MI.getOpcode() == PPC::MTCRF || MI.getOpcode() == PPC::MFOCRF) &&
127 (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7));
128 return 0x80 >> PPCRegisterInfo::getRegisterNumbering(MO.getReg());
132 unsigned PPCMCCodeEmitter::
133 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
134 SmallVectorImpl<MCFixup> &Fixups) const {
136 assert(MI.getOpcode() != PPC::MTCRF && MI.getOpcode() != PPC::MFOCRF);
137 return PPCRegisterInfo::getRegisterNumbering(MO.getReg());
148 #include "PPCGenMCCodeEmitter.inc"