1 //===-- PPCMCCodeEmitter.cpp - Convert PPC code to machine code -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mccodeemitter"
16 #include "PPCRegisterInfo.h"
17 #include "llvm/MC/MCCodeEmitter.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Support/raw_ostream.h"
21 #include "llvm/Support/ErrorHandling.h"
24 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
27 class PPCMCCodeEmitter : public MCCodeEmitter {
28 PPCMCCodeEmitter(const PPCMCCodeEmitter &); // DO NOT IMPLEMENT
29 void operator=(const PPCMCCodeEmitter &); // DO NOT IMPLEMENT
30 const TargetMachine &TM;
34 PPCMCCodeEmitter(TargetMachine &tm, MCContext &ctx)
38 ~PPCMCCodeEmitter() {}
40 unsigned getNumFixupKinds() const { return 0 /*PPC::NumTargetFixupKinds*/; }
42 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
43 const static MCFixupKindInfo Infos[] = {
44 // name offset bits flags
45 { "fixup_arm_pcrel_12", 2, 12, MCFixupKindInfo::FKF_IsPCRel }
47 { "fixup_arm_vfp_pcrel_12", 3, 8, MCFixupKindInfo::FKF_IsPCRel },
48 { "fixup_arm_branch", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
52 if (Kind < FirstTargetFixupKind)
53 return MCCodeEmitter::getFixupKindInfo(Kind);
55 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
57 return Infos[Kind - FirstTargetFixupKind];
60 unsigned get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
61 SmallVectorImpl<MCFixup> &Fixups) const;
63 /// getMachineOpValue - Return binary encoding of operand. If the machine
64 /// operand requires relocation, record the relocation and return zero.
65 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
66 SmallVectorImpl<MCFixup> &Fixups) const;
68 // getBinaryCodeForInstr - TableGen'erated function for getting the
69 // binary encoding for an instruction.
70 unsigned getBinaryCodeForInstr(const MCInst &MI,
71 SmallVectorImpl<MCFixup> &Fixups) const;
72 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
73 SmallVectorImpl<MCFixup> &Fixups) const {
74 unsigned Bits = getBinaryCodeForInstr(MI, Fixups);
76 // Output the constant in big endian byte order.
77 for (unsigned i = 0; i != 4; ++i) {
78 OS << (char)(Bits >> 24);
82 ++MCNumEmitted; // Keep track of the # of mi's emitted.
87 } // end anonymous namespace
89 MCCodeEmitter *llvm::createPPCMCCodeEmitter(const Target &, TargetMachine &TM,
91 return new PPCMCCodeEmitter(TM, Ctx);
94 unsigned PPCMCCodeEmitter::
95 get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
96 SmallVectorImpl<MCFixup> &Fixups) const {
97 const MCOperand &MO = MI.getOperand(OpNo);
98 assert((MI.getOpcode() == PPC::MTCRF || MI.getOpcode() == PPC::MFOCRF) &&
99 (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7));
100 return 0x80 >> PPCRegisterInfo::getRegisterNumbering(MO.getReg());
104 unsigned PPCMCCodeEmitter::
105 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
106 SmallVectorImpl<MCFixup> &Fixups) const {
108 assert(MI.getOpcode() != PPC::MTCRF && MI.getOpcode() != PPC::MFOCRF);
109 return PPCRegisterInfo::getRegisterNumbering(MO.getReg());
120 #include "PPCGenMCCodeEmitter.inc"