1 //===- PPC32RegisterInfo.cpp - PowerPC32 Register Information ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC32 implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "reginfo"
16 #include "PowerPCInstrBuilder.h"
17 #include "PPC32RegisterInfo.h"
18 #include "llvm/Constants.h"
19 #include "llvm/Type.h"
20 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/Target/TargetFrameInfo.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/ADT/STLExtras.h"
34 PPC32RegisterInfo::PPC32RegisterInfo()
35 : PPC32GenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP) {
36 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
37 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
38 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
39 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
40 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
41 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
42 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
43 ImmToIdxMap[PPC::ADDI] = PPC::ADD;
46 static const TargetRegisterClass *getClass(unsigned SrcReg) {
47 if (PPC32::FPRCRegisterClass->contains(SrcReg))
48 return PPC32::FPRCRegisterClass;
49 assert(PPC32::GPRCRegisterClass->contains(SrcReg) && "Reg not FPR or GPR");
50 return PPC32::GPRCRegisterClass;
53 static unsigned getIdx(const TargetRegisterClass *RC) {
54 if (RC == PPC32::GPRCRegisterClass) {
55 switch (RC->getSize()) {
56 default: assert(0 && "Invalid data size!");
61 } else if (RC == PPC32::FPRCRegisterClass) {
62 switch (RC->getSize()) {
63 default: assert(0 && "Invalid data size!");
67 } else if (RC == PPC32::CRRCRegisterClass) {
68 switch (RC->getSize()) {
69 default: assert(0 && "Invalid data size!");
73 std::cerr << "Invalid register class to getIdx()!\n";
78 PPC32RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
79 MachineBasicBlock::iterator MI,
80 unsigned SrcReg, int FrameIdx) const {
81 static const unsigned Opcode[] = {
82 PPC::STB, PPC::STH, PPC::STW, PPC::STFS, PPC::STFD
84 const TargetRegisterClass *RegClass = getClass(SrcReg);
85 unsigned OC = Opcode[getIdx(RegClass)];
86 if (SrcReg == PPC::LR) {
87 BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11);
88 addFrameReference(BuildMI(MBB, MI, OC, 3).addReg(PPC::R11),FrameIdx);
89 } else if (RegClass == PPC32::CRRCRegisterClass) {
90 BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R11);
91 addFrameReference(BuildMI(MBB, MI, OC, 3).addReg(PPC::R11),FrameIdx);
93 addFrameReference(BuildMI(MBB, MI, OC, 3).addReg(SrcReg),FrameIdx);
98 PPC32RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
99 MachineBasicBlock::iterator MI,
100 unsigned DestReg, int FrameIdx) const {
101 static const unsigned Opcode[] = {
102 PPC::LBZ, PPC::LHZ, PPC::LWZ, PPC::LFS, PPC::LFD
104 const TargetRegisterClass *RegClass = getClass(SrcReg);
105 unsigned OC = Opcode[getIdx(RegClass)];
106 if (DestReg == PPC::LR) {
107 addFrameReference(BuildMI(MBB, MI, OC, 2, PPC::R11), FrameIdx);
108 BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11);
109 } else if (RegClass == PPC32::CRRCRegisterClass) {
110 addFrameReference(BuildMI(MBB, MI, OC, 2, PPC::R11), FrameIdx);
111 BuildMI(MBB, MI, PPC::MTCRF, 1, DestReg).addReg(PPC::R11);
113 addFrameReference(BuildMI(MBB, MI, OC, 2, DestReg), FrameIdx);
117 void PPC32RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
118 MachineBasicBlock::iterator MI,
119 unsigned DestReg, unsigned SrcReg,
120 const TargetRegisterClass *RC) const {
123 if (RC == PPC32::GPRCRegisterClass) {
124 BuildMI(MBB, MI, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
125 } else if (RC == PPC32::FPRCRegisterClass) {
126 BuildMI(MBB, MI, PPC::FMR, 1, DestReg).addReg(SrcReg);
127 } else if (RC == PPC32::CRRCRegisterClass) {
128 BuildMI(MBB, MI, PPC::MCRF, 1, DestReg).addReg(SrcReg);
130 std::cerr << "Attempt to copy register that is not GPR or FPR";
135 //===----------------------------------------------------------------------===//
136 // Stack Frame Processing methods
137 //===----------------------------------------------------------------------===//
139 // hasFP - Return true if the specified function should have a dedicated frame
140 // pointer register. This is true if the function has variable sized allocas or
141 // if frame pointer elimination is disabled.
143 static bool hasFP(MachineFunction &MF) {
144 return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
147 void PPC32RegisterInfo::
148 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
149 MachineBasicBlock::iterator I) const {
151 // If we have a frame pointer, convert as follows:
152 // ADJCALLSTACKDOWN -> addi, r1, r1, -amount
153 // ADJCALLSTACKUP -> addi, r1, r1, amount
154 MachineInstr *Old = I;
155 unsigned Amount = Old->getOperand(0).getImmedValue();
157 // We need to keep the stack aligned properly. To do this, we round the
158 // amount of space needed for the outgoing arguments up to the next
159 // alignment boundary.
160 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
161 Amount = (Amount+Align-1)/Align*Align;
163 // Replace the pseudo instruction with a new instruction...
164 if (Old->getOpcode() == PPC::ADJCALLSTACKDOWN) {
165 MBB.insert(I, BuildMI(PPC::ADDI, 2, PPC::R1).addReg(PPC::R1)
168 assert(Old->getOpcode() == PPC::ADJCALLSTACKUP);
169 MBB.insert(I, BuildMI(PPC::ADDI, 2, PPC::R1).addReg(PPC::R1)
178 PPC32RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
180 MachineInstr &MI = *II;
181 MachineBasicBlock &MBB = *MI.getParent();
182 MachineFunction &MF = *MBB.getParent();
184 while (!MI.getOperand(i).isFrameIndex()) {
186 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
189 int FrameIndex = MI.getOperand(i).getFrameIndex();
191 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
192 MI.SetMachineOperandReg(i, hasFP(MF) ? PPC::R31 : PPC::R1);
194 // Take into account whether it's an add or mem instruction
195 unsigned OffIdx = (i == 2) ? 1 : 2;
197 // Now add the frame object offset to the offset from r1.
198 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
199 MI.getOperand(OffIdx).getImmedValue();
201 // If we're not using a Frame Pointer that has been set to the value of the
202 // SP before having the stack size subtracted from it, then add the stack size
203 // to Offset to get the correct offset.
204 Offset += MF.getFrameInfo()->getStackSize();
206 if (Offset > 32767 || Offset < -32768) {
207 // Insert a set of r0 with the full offset value before the ld, st, or add
208 MachineBasicBlock *MBB = MI.getParent();
209 MBB->insert(II, BuildMI(PPC::LIS, 1, PPC::R0).addSImm(Offset >> 16));
210 MBB->insert(II, BuildMI(PPC::ORI, 2, PPC::R0).addReg(PPC::R0)
212 // convert into indexed form of the instruction
213 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
214 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
215 unsigned NewOpcode = const_cast<std::map<unsigned, unsigned>& >(ImmToIdxMap)[MI.getOpcode()];
216 assert(NewOpcode && "No indexed form of load or store available!");
217 MI.setOpcode(NewOpcode);
218 MI.SetMachineOperandReg(1, MI.getOperand(i).getReg());
219 MI.SetMachineOperandReg(2, PPC::R0);
221 MI.SetMachineOperandConst(OffIdx,MachineOperand::MO_SignExtendedImmed,Offset);
226 void PPC32RegisterInfo::emitPrologue(MachineFunction &MF) const {
227 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
228 MachineBasicBlock::iterator MBBI = MBB.begin();
229 MachineFrameInfo *MFI = MF.getFrameInfo();
232 // Get the number of bytes to allocate from the FrameInfo
233 unsigned NumBytes = MFI->getStackSize();
235 // If we have calls, we cannot use the red zone to store callee save registers
236 // and we must set up a stack frame, so calculate the necessary size here.
237 if (MFI->hasCalls()) {
238 // We reserve argument space for call sites in the function immediately on
239 // entry to the current function. This eliminates the need for add/sub
240 // brackets around call sites.
241 NumBytes += MFI->getMaxCallFrameSize();
244 // If we are a leaf function, and use up to 224 bytes of stack space,
245 // and don't have a frame pointer, then we do not need to adjust the stack
246 // pointer (we fit in the Red Zone).
247 if ((NumBytes == 0) || (NumBytes <= 224 && !hasFP(MF) && !MFI->hasCalls())) {
248 MFI->setStackSize(0);
252 // Add the size of R1 to NumBytes size for the store of R1 to the bottom
253 // of the stack and round the size to a multiple of the alignment.
254 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
255 unsigned GPRSize = getSpillSize(PPC::R1)/8;
256 unsigned Size = hasFP(MF) ? GPRSize + GPRSize : GPRSize;
257 NumBytes = (NumBytes+Size+Align-1)/Align*Align;
259 // Update frame info to pretend that this is part of the stack...
260 MFI->setStackSize(NumBytes);
262 // Adjust stack pointer: r1 -= numbytes.
263 if (NumBytes <= 32768) {
264 MI=BuildMI(PPC::STWU,3).addReg(PPC::R1).addSImm(-NumBytes).addReg(PPC::R1);
265 MBB.insert(MBBI, MI);
267 int NegNumbytes = -NumBytes;
268 MI = BuildMI(PPC::LIS, 1, PPC::R0).addSImm(NegNumbytes >> 16);
269 MBB.insert(MBBI, MI);
270 MI = BuildMI(PPC::ORI, 2, PPC::R0).addReg(PPC::R0)
271 .addImm(NegNumbytes & 0xFFFF);
272 MBB.insert(MBBI, MI);
273 MI = BuildMI(PPC::STWUX, 3).addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
274 MBB.insert(MBBI, MI);
278 MI = BuildMI(PPC::STW, 3).addReg(PPC::R31).addSImm(GPRSize).addReg(PPC::R1);
279 MBB.insert(MBBI, MI);
280 MI = BuildMI(PPC::OR, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1);
281 MBB.insert(MBBI, MI);
285 void PPC32RegisterInfo::emitEpilogue(MachineFunction &MF,
286 MachineBasicBlock &MBB) const {
287 const MachineFrameInfo *MFI = MF.getFrameInfo();
288 MachineBasicBlock::iterator MBBI = prior(MBB.end());
290 assert(MBBI->getOpcode() == PPC::BLR &&
291 "Can only insert epilog into returning blocks");
293 // Get the number of bytes allocated from the FrameInfo...
294 unsigned NumBytes = MFI->getStackSize();
295 unsigned GPRSize = getSpillSize(PPC::R31)/8;
299 MI = BuildMI(PPC::LWZ, 2, PPC::R31).addSImm(GPRSize).addReg(PPC::R31);
300 MBB.insert(MBBI, MI);
302 MI = BuildMI(PPC::LWZ, 2, PPC::R1).addSImm(0).addReg(PPC::R1);
303 MBB.insert(MBBI, MI);
307 #include "PPC32GenRegisterInfo.inc"