1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetRegisterInfo
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "reginfo"
17 #include "PPCInstrBuilder.h"
18 #include "PPCMachineFunctionInfo.h"
19 #include "PPCRegisterInfo.h"
20 #include "PPCFrameInfo.h"
21 #include "PPCSubtarget.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Type.h"
24 #include "llvm/CodeGen/ValueTypes.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineModuleInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineLocation.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAGNodes.h"
32 #include "llvm/Target/TargetFrameInfo.h"
33 #include "llvm/Target/TargetInstrInfo.h"
34 #include "llvm/Target/TargetMachine.h"
35 #include "llvm/Target/TargetOptions.h"
36 #include "llvm/Support/CommandLine.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/MathExtras.h"
39 #include "llvm/ADT/BitVector.h"
40 #include "llvm/ADT/STLExtras.h"
44 /// getRegisterNumbering - Given the enum value for some register, e.g.
45 /// PPC::F14, return the number that it corresponds to (e.g. 14).
46 unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
50 case R0 : case X0 : case F0 : case V0 : case CR0: return 0;
51 case R1 : case X1 : case F1 : case V1 : case CR1: return 1;
52 case R2 : case X2 : case F2 : case V2 : case CR2: return 2;
53 case R3 : case X3 : case F3 : case V3 : case CR3: return 3;
54 case R4 : case X4 : case F4 : case V4 : case CR4: return 4;
55 case R5 : case X5 : case F5 : case V5 : case CR5: return 5;
56 case R6 : case X6 : case F6 : case V6 : case CR6: return 6;
57 case R7 : case X7 : case F7 : case V7 : case CR7: return 7;
58 case R8 : case X8 : case F8 : case V8 : return 8;
59 case R9 : case X9 : case F9 : case V9 : return 9;
60 case R10: case X10: case F10: case V10: return 10;
61 case R11: case X11: case F11: case V11: return 11;
62 case R12: case X12: case F12: case V12: return 12;
63 case R13: case X13: case F13: case V13: return 13;
64 case R14: case X14: case F14: case V14: return 14;
65 case R15: case X15: case F15: case V15: return 15;
66 case R16: case X16: case F16: case V16: return 16;
67 case R17: case X17: case F17: case V17: return 17;
68 case R18: case X18: case F18: case V18: return 18;
69 case R19: case X19: case F19: case V19: return 19;
70 case R20: case X20: case F20: case V20: return 20;
71 case R21: case X21: case F21: case V21: return 21;
72 case R22: case X22: case F22: case V22: return 22;
73 case R23: case X23: case F23: case V23: return 23;
74 case R24: case X24: case F24: case V24: return 24;
75 case R25: case X25: case F25: case V25: return 25;
76 case R26: case X26: case F26: case V26: return 26;
77 case R27: case X27: case F27: case V27: return 27;
78 case R28: case X28: case F28: case V28: return 28;
79 case R29: case X29: case F29: case V29: return 29;
80 case R30: case X30: case F30: case V30: return 30;
81 case R31: case X31: case F31: case V31: return 31;
83 cerr << "Unhandled reg in PPCRegisterInfo::getRegisterNumbering!\n";
88 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST,
89 const TargetInstrInfo &tii)
90 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
91 Subtarget(ST), TII(tii) {
92 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
93 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
94 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
95 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
96 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
97 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
98 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
99 ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
102 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8;
103 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8;
104 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8;
105 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX;
106 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32;
109 void PPCRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
110 MachineBasicBlock::iterator I,
112 const MachineInstr *Orig) const {
113 MachineInstr *MI = Orig->clone();
114 MI->getOperand(0).setReg(DestReg);
119 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
120 // 32-bit Darwin calling convention.
121 static const unsigned Macho32_CalleeSavedRegs[] = {
122 PPC::R13, PPC::R14, PPC::R15,
123 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
124 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
125 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
126 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
128 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
129 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
130 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
131 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
134 PPC::CR2, PPC::CR3, PPC::CR4,
135 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
136 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
137 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
142 static const unsigned ELF32_CalleeSavedRegs[] = {
143 PPC::R13, PPC::R14, PPC::R15,
144 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
145 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
146 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
147 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
150 PPC::F10, PPC::F11, PPC::F12, PPC::F13,
151 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
152 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
153 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
154 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
157 PPC::CR2, PPC::CR3, PPC::CR4,
158 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
159 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
160 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
164 // 64-bit Darwin calling convention.
165 static const unsigned Macho64_CalleeSavedRegs[] = {
167 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
168 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
169 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
170 PPC::X28, PPC::X29, PPC::X30, PPC::X31,
172 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
173 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
174 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
175 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
178 PPC::CR2, PPC::CR3, PPC::CR4,
179 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
180 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
181 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
186 if (Subtarget.isMachoABI())
187 return Subtarget.isPPC64() ? Macho64_CalleeSavedRegs :
188 Macho32_CalleeSavedRegs;
191 return ELF32_CalleeSavedRegs;
194 const TargetRegisterClass* const*
195 PPCRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
196 // 32-bit Macho calling convention.
197 static const TargetRegisterClass * const Macho32_CalleeSavedRegClasses[] = {
198 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
199 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
200 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
201 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
202 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
204 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
205 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
206 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
207 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
208 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
210 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
212 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
213 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
214 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
216 &PPC::GPRCRegClass, 0
219 static const TargetRegisterClass * const ELF32_CalleeSavedRegClasses[] = {
220 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
221 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
222 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
223 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
224 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
227 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
228 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
229 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
230 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
231 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
232 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
234 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
236 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
237 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
238 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
240 &PPC::GPRCRegClass, 0
243 // 64-bit Macho calling convention.
244 static const TargetRegisterClass * const Macho64_CalleeSavedRegClasses[] = {
245 &PPC::G8RCRegClass,&PPC::G8RCRegClass,
246 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
247 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
248 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
249 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
251 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
252 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
253 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
254 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
255 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
257 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
259 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
260 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
261 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
263 &PPC::G8RCRegClass, 0
266 if (Subtarget.isMachoABI())
267 return Subtarget.isPPC64() ? Macho64_CalleeSavedRegClasses :
268 Macho32_CalleeSavedRegClasses;
271 return ELF32_CalleeSavedRegClasses;
274 // needsFP - Return true if the specified function should have a dedicated frame
275 // pointer register. This is true if the function has variable sized allocas or
276 // if frame pointer elimination is disabled.
278 static bool needsFP(const MachineFunction &MF) {
279 const MachineFrameInfo *MFI = MF.getFrameInfo();
280 return NoFramePointerElim || MFI->hasVarSizedObjects();
283 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
284 BitVector Reserved(getNumRegs());
285 Reserved.set(PPC::R0);
286 Reserved.set(PPC::R1);
287 Reserved.set(PPC::LR);
288 // In Linux, r2 is reserved for the OS.
289 if (!Subtarget.isDarwin())
290 Reserved.set(PPC::R2);
291 // On PPC64, r13 is the thread pointer. Never allocate this register.
292 // Note that this is overconservative, as it also prevents allocation of
293 // R31 when the FP is not needed.
294 if (Subtarget.isPPC64()) {
295 Reserved.set(PPC::R13);
296 Reserved.set(PPC::R31);
299 Reserved.set(PPC::R31);
303 //===----------------------------------------------------------------------===//
304 // Stack Frame Processing methods
305 //===----------------------------------------------------------------------===//
307 // hasFP - Return true if the specified function actually has a dedicated frame
308 // pointer register. This is true if the function needs a frame pointer and has
309 // a non-zero stack size.
310 bool PPCRegisterInfo::hasFP(const MachineFunction &MF) const {
311 const MachineFrameInfo *MFI = MF.getFrameInfo();
312 return MFI->getStackSize() && needsFP(MF);
315 /// MustSaveLR - Return true if this function requires that we save the LR
316 /// register onto the stack in the prolog and restore it in the epilog of the
318 static bool MustSaveLR(const MachineFunction &MF) {
319 const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>();
321 // We need an save/restore of LR if there is any use/def of LR explicitly, or
322 // if there is some use of the LR stack slot (e.g. for builtin_return_address.
323 return MFI->usesLR() || MFI->isLRStoreRequired() ||
324 // FIXME: Anything that has a call should clobber the LR register,
325 // isn't this redundant??
326 MF.getFrameInfo()->hasCalls();
329 void PPCRegisterInfo::
330 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
331 MachineBasicBlock::iterator I) const {
332 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
336 /// LowerDynamicAlloc - Generate the code for allocating an object in the
337 /// current frame. The sequence of code with be in the general form
339 /// addi R0, SP, #frameSize ; get the address of the previous frame
340 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size
341 /// addi Rnew, SP, #maxCalFrameSize ; get the top of the allocation
343 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const {
344 // Get the instruction.
345 MachineInstr &MI = *II;
346 // Get the instruction's basic block.
347 MachineBasicBlock &MBB = *MI.getParent();
348 // Get the basic block's function.
349 MachineFunction &MF = *MBB.getParent();
350 // Get the frame info.
351 MachineFrameInfo *MFI = MF.getFrameInfo();
352 // Determine whether 64-bit pointers are used.
353 bool LP64 = Subtarget.isPPC64();
355 // Get the maximum call stack size.
356 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
357 // Get the total frame size.
358 unsigned FrameSize = MFI->getStackSize();
360 // Get stack alignments.
361 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
362 unsigned MaxAlign = MFI->getMaxAlignment();
363 assert(MaxAlign <= TargetAlign &&
364 "Dynamic alloca with large aligns not supported");
366 // Determine the previous frame's address. If FrameSize can't be
367 // represented as 16 bits or we need special alignment, then we load the
368 // previous frame's address from 0(SP). Why not do an addis of the hi?
369 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
370 // Constructing the constant and adding would take 3 instructions.
371 // Fortunately, a frame greater than 32K is rare.
372 if (MaxAlign < TargetAlign && isInt16(FrameSize)) {
373 BuildMI(MBB, II, TII.get(PPC::ADDI), PPC::R0)
377 BuildMI(MBB, II, TII.get(PPC::LD), PPC::X0)
381 BuildMI(MBB, II, TII.get(PPC::LWZ), PPC::R0)
386 // Grow the stack and update the stack pointer link, then
387 // determine the address of new allocated space.
389 BuildMI(MBB, II, TII.get(PPC::STDUX))
392 .addReg(MI.getOperand(1).getReg());
393 BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
395 .addImm(maxCallFrameSize);
397 BuildMI(MBB, II, TII.get(PPC::STWUX))
400 .addReg(MI.getOperand(1).getReg());
401 BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
403 .addImm(maxCallFrameSize);
406 // Discard the DYNALLOC instruction.
410 void PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
411 int SPAdj, RegScavenger *RS) const {
412 assert(SPAdj == 0 && "Unexpected");
414 // Get the instruction.
415 MachineInstr &MI = *II;
416 // Get the instruction's basic block.
417 MachineBasicBlock &MBB = *MI.getParent();
418 // Get the basic block's function.
419 MachineFunction &MF = *MBB.getParent();
420 // Get the frame info.
421 MachineFrameInfo *MFI = MF.getFrameInfo();
423 // Find out which operand is the frame index.
424 unsigned FIOperandNo = 0;
425 while (!MI.getOperand(FIOperandNo).isFrameIndex()) {
427 assert(FIOperandNo != MI.getNumOperands() &&
428 "Instr doesn't have FrameIndex operand!");
430 // Take into account whether it's an add or mem instruction
431 unsigned OffsetOperandNo = (FIOperandNo == 2) ? 1 : 2;
432 if (MI.getOpcode() == TargetInstrInfo::INLINEASM)
433 OffsetOperandNo = FIOperandNo-1;
435 // Get the frame index.
436 int FrameIndex = MI.getOperand(FIOperandNo).getIndex();
438 // Get the frame pointer save index. Users of this index are primarily
439 // DYNALLOC instructions.
440 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
441 int FPSI = FI->getFramePointerSaveIndex();
442 // Get the instruction opcode.
443 unsigned OpC = MI.getOpcode();
445 // Special case for dynamic alloca.
446 if (FPSI && FrameIndex == FPSI &&
447 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
448 lowerDynamicAlloc(II);
452 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
453 MI.getOperand(FIOperandNo).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1,
456 // Figure out if the offset in the instruction is shifted right two bits. This
457 // is true for instructions like "STD", which the machine implicitly adds two
459 bool isIXAddr = false;
469 // Now add the frame object offset to the offset from r1.
470 int Offset = MFI->getObjectOffset(FrameIndex);
472 Offset += MI.getOperand(OffsetOperandNo).getImm();
474 Offset += MI.getOperand(OffsetOperandNo).getImm() << 2;
476 // If we're not using a Frame Pointer that has been set to the value of the
477 // SP before having the stack size subtracted from it, then add the stack size
478 // to Offset to get the correct offset.
479 Offset += MFI->getStackSize();
481 // If we can, encode the offset directly into the instruction. If this is a
482 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If
483 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits
484 // clear can be encoded. This is extremely uncommon, because normally you
485 // only "std" to a stack slot that is at least 4-byte aligned, but it can
486 // happen in invalid code.
487 if (isInt16(Offset) && (!isIXAddr || (Offset & 3) == 0)) {
489 Offset >>= 2; // The actual encoded value has the low two bits zero.
490 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
494 // Insert a set of r0 with the full offset value before the ld, st, or add
495 BuildMI(MBB, II, TII.get(PPC::LIS), PPC::R0).addImm(Offset >> 16);
496 BuildMI(MBB, II, TII.get(PPC::ORI), PPC::R0).addReg(PPC::R0).addImm(Offset);
498 // Convert into indexed form of the instruction
499 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
500 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
501 unsigned OperandBase;
502 if (OpC != TargetInstrInfo::INLINEASM) {
503 assert(ImmToIdxMap.count(OpC) &&
504 "No indexed form of load or store available!");
505 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second;
506 MI.setDesc(TII.get(NewOpcode));
509 OperandBase = OffsetOperandNo;
512 unsigned StackReg = MI.getOperand(FIOperandNo).getReg();
513 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false);
514 MI.getOperand(OperandBase+1).ChangeToRegister(PPC::R0, false);
517 /// VRRegNo - Map from a numbered VR register to its enum value.
519 static const unsigned short VRRegNo[] = {
520 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
521 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
522 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
523 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
526 /// RemoveVRSaveCode - We have found that this function does not need any code
527 /// to manipulate the VRSAVE register, even though it uses vector registers.
528 /// This can happen when the only registers used are known to be live in or out
529 /// of the function. Remove all of the VRSAVE related code from the function.
530 static void RemoveVRSaveCode(MachineInstr *MI) {
531 MachineBasicBlock *Entry = MI->getParent();
532 MachineFunction *MF = Entry->getParent();
534 // We know that the MTVRSAVE instruction immediately follows MI. Remove it.
535 MachineBasicBlock::iterator MBBI = MI;
537 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
538 MBBI->eraseFromParent();
540 bool RemovedAllMTVRSAVEs = true;
541 // See if we can find and remove the MTVRSAVE instruction from all of the
543 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
544 // If last instruction is a return instruction, add an epilogue
545 if (!I->empty() && I->back().getDesc().isReturn()) {
546 bool FoundIt = false;
547 for (MBBI = I->end(); MBBI != I->begin(); ) {
549 if (MBBI->getOpcode() == PPC::MTVRSAVE) {
550 MBBI->eraseFromParent(); // remove it.
555 RemovedAllMTVRSAVEs &= FoundIt;
559 // If we found and removed all MTVRSAVE instructions, remove the read of
561 if (RemovedAllMTVRSAVEs) {
563 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
565 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
566 MBBI->eraseFromParent();
569 // Finally, nuke the UPDATE_VRSAVE.
570 MI->eraseFromParent();
573 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
574 // instruction selector. Based on the vector registers that have been used,
575 // transform this into the appropriate ORI instruction.
576 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) {
577 MachineFunction *MF = MI->getParent()->getParent();
579 unsigned UsedRegMask = 0;
580 for (unsigned i = 0; i != 32; ++i)
581 if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i]))
582 UsedRegMask |= 1 << (31-i);
584 // Live in and live out values already must be in the mask, so don't bother
586 for (MachineRegisterInfo::livein_iterator
587 I = MF->getRegInfo().livein_begin(),
588 E = MF->getRegInfo().livein_end(); I != E; ++I) {
589 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first);
590 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg.
591 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
593 for (MachineRegisterInfo::liveout_iterator
594 I = MF->getRegInfo().liveout_begin(),
595 E = MF->getRegInfo().liveout_end(); I != E; ++I) {
596 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I);
597 if (VRRegNo[RegNo] == *I) // If this really is a vector reg.
598 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
601 unsigned SrcReg = MI->getOperand(1).getReg();
602 unsigned DstReg = MI->getOperand(0).getReg();
603 // If no registers are used, turn this into a copy.
604 if (UsedRegMask == 0) {
605 // Remove all VRSAVE code.
606 RemoveVRSaveCode(MI);
608 } else if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
609 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg)
610 .addReg(SrcReg).addImm(UsedRegMask);
611 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
612 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
613 .addReg(SrcReg).addImm(UsedRegMask >> 16);
615 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
616 .addReg(SrcReg).addImm(UsedRegMask >> 16);
617 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg)
618 .addReg(DstReg).addImm(UsedRegMask & 0xFFFF);
621 // Remove the old UPDATE_VRSAVE instruction.
622 MI->eraseFromParent();
625 /// determineFrameLayout - Determine the size of the frame and maximum call
627 void PPCRegisterInfo::determineFrameLayout(MachineFunction &MF) const {
628 MachineFrameInfo *MFI = MF.getFrameInfo();
630 // Get the number of bytes to allocate from the FrameInfo
631 unsigned FrameSize = MFI->getStackSize();
633 // Get the alignments provided by the target, and the maximum alignment
634 // (if any) of the fixed frame objects.
635 unsigned MaxAlign = MFI->getMaxAlignment();
636 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
637 unsigned AlignMask = TargetAlign - 1; //
639 // If we are a leaf function, and use up to 224 bytes of stack space,
640 // don't have a frame pointer, calls, or dynamic alloca then we do not need
641 // to adjust the stack pointer (we fit in the Red Zone).
642 if (FrameSize <= 224 && // Fits in red zone.
643 !MFI->hasVarSizedObjects() && // No dynamic alloca.
644 !MFI->hasCalls() && // No calls.
645 MaxAlign <= TargetAlign) { // No special alignment.
647 MFI->setStackSize(0);
651 // Get the maximum call frame size of all the calls.
652 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
654 // Maximum call frame needs to be at least big enough for linkage and 8 args.
655 unsigned minCallFrameSize =
656 PPCFrameInfo::getMinCallFrameSize(Subtarget.isPPC64(),
657 Subtarget.isMachoABI());
658 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
660 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
661 // that allocations will be aligned.
662 if (MFI->hasVarSizedObjects())
663 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
665 // Update maximum call frame size.
666 MFI->setMaxCallFrameSize(maxCallFrameSize);
668 // Include call frame size in total.
669 FrameSize += maxCallFrameSize;
671 // Make sure the frame is aligned.
672 FrameSize = (FrameSize + AlignMask) & ~AlignMask;
674 // Update frame info.
675 MFI->setStackSize(FrameSize);
678 void PPCRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
681 // Save and clear the LR state.
682 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
683 unsigned LR = getRARegister();
684 FI->setUsesLR(MF.getRegInfo().isPhysRegUsed(LR));
685 MF.getRegInfo().setPhysRegUnused(LR);
687 // Save R31 if necessary
688 int FPSI = FI->getFramePointerSaveIndex();
689 bool IsPPC64 = Subtarget.isPPC64();
690 bool IsELF32_ABI = Subtarget.isELF32_ABI();
691 bool IsMachoABI = Subtarget.isMachoABI();
692 const MachineFrameInfo *MFI = MF.getFrameInfo();
694 // If the frame pointer save index hasn't been defined yet.
695 if (!FPSI && (NoFramePointerElim || MFI->hasVarSizedObjects()) &&
697 // Find out what the fix offset of the frame pointer save area.
698 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64,
700 // Allocate the frame index for frame pointer save area.
701 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset);
703 FI->setFramePointerSaveIndex(FPSI);
708 void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
709 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
710 MachineBasicBlock::iterator MBBI = MBB.begin();
711 MachineFrameInfo *MFI = MF.getFrameInfo();
712 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
714 // Prepare for frame info.
715 unsigned FrameLabelId = 0;
717 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
719 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
720 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
721 HandleVRSaveUpdate(MBBI, TII);
726 // Move MBBI back to the beginning of the function.
729 // Work out frame sizes.
730 determineFrameLayout(MF);
731 unsigned FrameSize = MFI->getStackSize();
733 int NegFrameSize = -FrameSize;
735 // Get processor type.
736 bool IsPPC64 = Subtarget.isPPC64();
737 // Get operating system
738 bool IsMachoABI = Subtarget.isMachoABI();
739 // Check if the link register (LR) has been used.
740 bool UsesLR = MustSaveLR(MF);
741 // Do we have a frame pointer for this function?
742 bool HasFP = hasFP(MF) && FrameSize;
744 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI);
745 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI);
749 BuildMI(MBB, MBBI, TII.get(PPC::MFLR8), PPC::X0);
752 BuildMI(MBB, MBBI, TII.get(PPC::STD))
753 .addReg(PPC::X31).addImm(FPOffset/4).addReg(PPC::X1);
756 BuildMI(MBB, MBBI, TII.get(PPC::STD))
757 .addReg(PPC::X0).addImm(LROffset/4).addReg(PPC::X1);
760 BuildMI(MBB, MBBI, TII.get(PPC::MFLR), PPC::R0);
763 BuildMI(MBB, MBBI, TII.get(PPC::STW))
764 .addReg(PPC::R31).addImm(FPOffset).addReg(PPC::R1);
767 BuildMI(MBB, MBBI, TII.get(PPC::STW))
768 .addReg(PPC::R0).addImm(LROffset).addReg(PPC::R1);
771 // Skip if a leaf routine.
772 if (!FrameSize) return;
774 // Get stack alignments.
775 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
776 unsigned MaxAlign = MFI->getMaxAlignment();
778 if (MMI && MMI->needsFrameInfo()) {
779 // Mark effective beginning of when frame pointer becomes valid.
780 FrameLabelId = MMI->NextLabelID();
781 BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(FrameLabelId).addImm(0);
784 // Adjust stack pointer: r1 += NegFrameSize.
785 // If there is a preferred stack alignment, align R1 now
788 if (MaxAlign > TargetAlign) {
789 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!");
790 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!");
791 BuildMI(MBB, MBBI, TII.get(PPC::RLWINM), PPC::R0)
792 .addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31);
793 BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC) ,PPC::R0).addReg(PPC::R0)
794 .addImm(NegFrameSize);
795 BuildMI(MBB, MBBI, TII.get(PPC::STWUX))
796 .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
797 } else if (isInt16(NegFrameSize)) {
798 BuildMI(MBB, MBBI, TII.get(PPC::STWU),
799 PPC::R1).addReg(PPC::R1).addImm(NegFrameSize).addReg(PPC::R1);
801 BuildMI(MBB, MBBI, TII.get(PPC::LIS), PPC::R0).addImm(NegFrameSize >> 16);
802 BuildMI(MBB, MBBI, TII.get(PPC::ORI), PPC::R0).addReg(PPC::R0)
803 .addImm(NegFrameSize & 0xFFFF);
804 BuildMI(MBB, MBBI, TII.get(PPC::STWUX)).addReg(PPC::R1).addReg(PPC::R1)
808 if (MaxAlign > TargetAlign) {
809 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!");
810 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!");
811 BuildMI(MBB, MBBI, TII.get(PPC::RLDICL), PPC::X0)
812 .addReg(PPC::X1).addImm(0).addImm(64-Log2_32(MaxAlign));
813 BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC8), PPC::X0).addReg(PPC::X0)
814 .addImm(NegFrameSize);
815 BuildMI(MBB, MBBI, TII.get(PPC::STDUX))
816 .addReg(PPC::X1).addReg(PPC::X1).addReg(PPC::X0);
817 } else if (isInt16(NegFrameSize)) {
818 BuildMI(MBB, MBBI, TII.get(PPC::STDU), PPC::X1)
819 .addReg(PPC::X1).addImm(NegFrameSize/4).addReg(PPC::X1);
821 BuildMI(MBB, MBBI, TII.get(PPC::LIS8), PPC::X0).addImm(NegFrameSize >>16);
822 BuildMI(MBB, MBBI, TII.get(PPC::ORI8), PPC::X0).addReg(PPC::X0)
823 .addImm(NegFrameSize & 0xFFFF);
824 BuildMI(MBB, MBBI, TII.get(PPC::STDUX)).addReg(PPC::X1).addReg(PPC::X1)
829 if (MMI && MMI->needsFrameInfo()) {
830 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
833 // Show update of SP.
834 MachineLocation SPDst(MachineLocation::VirtualFP);
835 MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize);
836 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
838 MachineLocation SP(IsPPC64 ? PPC::X31 : PPC::R31);
839 Moves.push_back(MachineMove(FrameLabelId, SP, SP));
843 MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset);
844 MachineLocation FPSrc(IsPPC64 ? PPC::X31 : PPC::R31);
845 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc));
848 // Add callee saved registers to move list.
849 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
850 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
851 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
852 unsigned Reg = CSI[I].getReg();
853 if (Reg == PPC::LR || Reg == PPC::LR8) continue;
854 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
855 MachineLocation CSSrc(Reg);
856 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
859 MachineLocation LRDst(MachineLocation::VirtualFP, LROffset);
860 MachineLocation LRSrc(IsPPC64 ? PPC::LR8 : PPC::LR);
861 Moves.push_back(MachineMove(FrameLabelId, LRDst, LRSrc));
863 // Mark effective beginning of when frame pointer is ready.
864 unsigned ReadyLabelId = MMI->NextLabelID();
865 BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(ReadyLabelId).addImm(0);
867 MachineLocation FPDst(HasFP ? (IsPPC64 ? PPC::X31 : PPC::R31) :
868 (IsPPC64 ? PPC::X1 : PPC::R1));
869 MachineLocation FPSrc(MachineLocation::VirtualFP);
870 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
873 // If there is a frame pointer, copy R1 into R31
876 BuildMI(MBB, MBBI, TII.get(PPC::OR), PPC::R31).addReg(PPC::R1)
879 BuildMI(MBB, MBBI, TII.get(PPC::OR8), PPC::X31).addReg(PPC::X1)
885 void PPCRegisterInfo::emitEpilogue(MachineFunction &MF,
886 MachineBasicBlock &MBB) const {
887 MachineBasicBlock::iterator MBBI = prior(MBB.end());
888 assert(MBBI->getOpcode() == PPC::BLR &&
889 "Can only insert epilog into returning blocks");
891 // Get alignment info so we know how to restore r1
892 const MachineFrameInfo *MFI = MF.getFrameInfo();
893 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
894 unsigned MaxAlign = MFI->getMaxAlignment();
896 // Get the number of bytes allocated from the FrameInfo.
897 unsigned FrameSize = MFI->getStackSize();
899 // Get processor type.
900 bool IsPPC64 = Subtarget.isPPC64();
901 // Get operating system
902 bool IsMachoABI = Subtarget.isMachoABI();
903 // Check if the link register (LR) has been used.
904 bool UsesLR = MustSaveLR(MF);
905 // Do we have a frame pointer for this function?
906 bool HasFP = hasFP(MF) && FrameSize;
908 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI);
909 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI);
912 // The loaded (or persistent) stack pointer value is offset by the 'stwu'
913 // on entry to the function. Add this offset back now.
914 if (!Subtarget.isPPC64()) {
915 if (isInt16(FrameSize) && TargetAlign >= MaxAlign &&
916 !MFI->hasVarSizedObjects()) {
917 BuildMI(MBB, MBBI, TII.get(PPC::ADDI), PPC::R1)
918 .addReg(PPC::R1).addImm(FrameSize);
920 BuildMI(MBB, MBBI, TII.get(PPC::LWZ),PPC::R1).addImm(0).addReg(PPC::R1);
923 if (isInt16(FrameSize) && TargetAlign >= MaxAlign &&
924 !MFI->hasVarSizedObjects()) {
925 BuildMI(MBB, MBBI, TII.get(PPC::ADDI8), PPC::X1)
926 .addReg(PPC::X1).addImm(FrameSize);
928 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X1).addImm(0).addReg(PPC::X1);
935 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X0)
936 .addImm(LROffset/4).addReg(PPC::X1);
939 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X31)
940 .addImm(FPOffset/4).addReg(PPC::X1);
943 BuildMI(MBB, MBBI, TII.get(PPC::MTLR8)).addReg(PPC::X0);
946 BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R0)
947 .addImm(LROffset).addReg(PPC::R1);
950 BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R31)
951 .addImm(FPOffset).addReg(PPC::R1);
954 BuildMI(MBB, MBBI, TII.get(PPC::MTLR)).addReg(PPC::R0);
958 unsigned PPCRegisterInfo::getRARegister() const {
959 return !Subtarget.isPPC64() ? PPC::LR : PPC::LR8;
962 unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const {
963 if (!Subtarget.isPPC64())
964 return hasFP(MF) ? PPC::R31 : PPC::R1;
966 return hasFP(MF) ? PPC::X31 : PPC::X1;
969 void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
971 // Initial state of the frame pointer is R1.
972 MachineLocation Dst(MachineLocation::VirtualFP);
973 MachineLocation Src(PPC::R1, 0);
974 Moves.push_back(MachineMove(0, Dst, Src));
977 unsigned PPCRegisterInfo::getEHExceptionRegister() const {
978 return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3;
981 unsigned PPCRegisterInfo::getEHHandlerRegister() const {
982 return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4;
985 int PPCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
986 // FIXME: Most probably dwarf numbers differs for Linux and Darwin
987 return PPCGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
990 #include "PPCGenRegisterInfo.inc"