1 //===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetRegisterInfo
13 //===----------------------------------------------------------------------===//
15 #include "PPCRegisterInfo.h"
17 #include "PPCFrameLowering.h"
18 #include "PPCInstrBuilder.h"
19 #include "PPCMachineFunctionInfo.h"
20 #include "PPCSubtarget.h"
21 #include "PPCTargetMachine.h"
22 #include "llvm/ADT/BitVector.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineModuleInfo.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/RegisterScavenging.h"
30 #include "llvm/IR/CallingConv.h"
31 #include "llvm/IR/Constants.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/IR/Type.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include "llvm/Target/TargetFrameLowering.h"
40 #include "llvm/Target/TargetInstrInfo.h"
41 #include "llvm/Target/TargetMachine.h"
42 #include "llvm/Target/TargetOptions.h"
47 #define DEBUG_TYPE "reginfo"
49 #define GET_REGINFO_TARGET_DESC
50 #include "PPCGenRegisterInfo.inc"
53 EnableBasePointer("ppc-use-base-pointer", cl::Hidden, cl::init(true),
54 cl::desc("Enable use of a base pointer for complex stack frames"));
57 AlwaysBasePointer("ppc-always-use-base-pointer", cl::Hidden, cl::init(false),
58 cl::desc("Force the use of a base pointer in every function"));
60 PPCRegisterInfo::PPCRegisterInfo(const PPCTargetMachine &TM)
61 : PPCGenRegisterInfo(TM.isPPC64() ? PPC::LR8 : PPC::LR,
63 TM.isPPC64() ? 0 : 1),
65 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
66 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
67 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
68 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
69 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
70 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
71 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
72 ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
73 ImmToIdxMap[PPC::LWA_32] = PPC::LWAX_32;
76 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8;
77 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8;
78 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8;
79 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX;
80 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8;
83 /// getPointerRegClass - Return the register class to use to hold pointers.
84 /// This is used for addressing modes.
85 const TargetRegisterClass *
86 PPCRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
88 // Note that PPCInstrInfo::FoldImmediate also directly uses this Kind value
89 // when it checks for ZERO folding.
92 return &PPC::G8RC_NOX0RegClass;
93 return &PPC::GPRC_NOR0RegClass;
97 return &PPC::G8RCRegClass;
98 return &PPC::GPRCRegClass;
102 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
103 const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>();
104 if (MF->getFunction()->getCallingConv() == CallingConv::AnyReg) {
105 if (Subtarget.hasVSX())
106 return CSR_64_AllRegs_VSX_SaveList;
107 if (Subtarget.hasAltivec())
108 return CSR_64_AllRegs_Altivec_SaveList;
109 return CSR_64_AllRegs_SaveList;
112 if (Subtarget.isDarwinABI())
114 ? (Subtarget.hasAltivec() ? CSR_Darwin64_Altivec_SaveList
115 : CSR_Darwin64_SaveList)
116 : (Subtarget.hasAltivec() ? CSR_Darwin32_Altivec_SaveList
117 : CSR_Darwin32_SaveList);
119 // On PPC64, we might need to save r2 (but only if it is not reserved).
120 bool SaveR2 = MF->getRegInfo().isAllocatable(PPC::X2);
123 ? (Subtarget.hasAltivec()
124 ? (SaveR2 ? CSR_SVR464_R2_Altivec_SaveList
125 : CSR_SVR464_Altivec_SaveList)
126 : (SaveR2 ? CSR_SVR464_R2_SaveList : CSR_SVR464_SaveList))
127 : (Subtarget.hasAltivec() ? CSR_SVR432_Altivec_SaveList
128 : CSR_SVR432_SaveList);
132 PPCRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
133 CallingConv::ID CC) const {
134 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
135 if (CC == CallingConv::AnyReg) {
136 if (Subtarget.hasVSX())
137 return CSR_64_AllRegs_VSX_RegMask;
138 if (Subtarget.hasAltivec())
139 return CSR_64_AllRegs_Altivec_RegMask;
140 return CSR_64_AllRegs_RegMask;
143 if (Subtarget.isDarwinABI())
144 return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_Darwin64_Altivec_RegMask
145 : CSR_Darwin64_RegMask)
146 : (Subtarget.hasAltivec() ? CSR_Darwin32_Altivec_RegMask
147 : CSR_Darwin32_RegMask);
149 return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_SVR464_Altivec_RegMask
150 : CSR_SVR464_RegMask)
151 : (Subtarget.hasAltivec() ? CSR_SVR432_Altivec_RegMask
152 : CSR_SVR432_RegMask);
156 PPCRegisterInfo::getNoPreservedMask() const {
157 return CSR_NoRegs_RegMask;
160 void PPCRegisterInfo::adjustStackMapLiveOutMask(uint32_t *Mask) const {
161 for (unsigned PseudoReg : {PPC::ZERO, PPC::ZERO8, PPC::RM})
162 Mask[PseudoReg / 32] &= ~(1u << (PseudoReg % 32));
165 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
166 BitVector Reserved(getNumRegs());
167 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
168 const PPCFrameLowering *TFI = getFrameLowering(MF);
170 // The ZERO register is not really a register, but the representation of r0
171 // when used in instructions that treat r0 as the constant 0.
172 Reserved.set(PPC::ZERO);
173 Reserved.set(PPC::ZERO8);
175 // The FP register is also not really a register, but is the representation
176 // of the frame pointer register used by ISD::FRAMEADDR.
177 Reserved.set(PPC::FP);
178 Reserved.set(PPC::FP8);
180 // The BP register is also not really a register, but is the representation
181 // of the base pointer register used by setjmp.
182 Reserved.set(PPC::BP);
183 Reserved.set(PPC::BP8);
185 // The counter registers must be reserved so that counter-based loops can
186 // be correctly formed (and the mtctr instructions are not DCE'd).
187 Reserved.set(PPC::CTR);
188 Reserved.set(PPC::CTR8);
190 Reserved.set(PPC::R1);
191 Reserved.set(PPC::LR);
192 Reserved.set(PPC::LR8);
193 Reserved.set(PPC::RM);
195 if (!Subtarget.isDarwinABI() || !Subtarget.hasAltivec())
196 Reserved.set(PPC::VRSAVE);
198 // The SVR4 ABI reserves r2 and r13
199 if (Subtarget.isSVR4ABI()) {
200 Reserved.set(PPC::R2); // System-reserved register
201 Reserved.set(PPC::R13); // Small Data Area pointer register
204 // On PPC64, r13 is the thread pointer. Never allocate this register.
206 Reserved.set(PPC::R13);
208 Reserved.set(PPC::X1);
209 Reserved.set(PPC::X13);
211 if (TFI->needsFP(MF))
212 Reserved.set(PPC::X31);
214 if (hasBasePointer(MF))
215 Reserved.set(PPC::X30);
217 // The 64-bit SVR4 ABI reserves r2 for the TOC pointer.
218 if (Subtarget.isSVR4ABI()) {
219 // We only reserve r2 if we need to use the TOC pointer. If we have no
220 // explicit uses of the TOC pointer (meaning we're a leaf function with
221 // no constant-pool loads, etc.) and we have no potential uses inside an
222 // inline asm block, then we can treat r2 has an ordinary callee-saved
224 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
225 if (FuncInfo->usesTOCBasePtr() || MF.hasInlineAsm())
226 Reserved.set(PPC::X2);
228 Reserved.reset(PPC::R2);
232 if (TFI->needsFP(MF))
233 Reserved.set(PPC::R31);
235 if (hasBasePointer(MF)) {
236 if (Subtarget.isSVR4ABI() && !TM.isPPC64() &&
237 TM.getRelocationModel() == Reloc::PIC_)
238 Reserved.set(PPC::R29);
240 Reserved.set(PPC::R30);
243 if (Subtarget.isSVR4ABI() && !TM.isPPC64() &&
244 TM.getRelocationModel() == Reloc::PIC_)
245 Reserved.set(PPC::R30);
247 // Reserve Altivec registers when Altivec is unavailable.
248 if (!Subtarget.hasAltivec())
249 for (TargetRegisterClass::iterator I = PPC::VRRCRegClass.begin(),
250 IE = PPC::VRRCRegClass.end(); I != IE; ++I)
256 unsigned PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
257 MachineFunction &MF) const {
258 const PPCFrameLowering *TFI = getFrameLowering(MF);
259 const unsigned DefaultSafety = 1;
261 switch (RC->getID()) {
264 case PPC::G8RC_NOX0RegClassID:
265 case PPC::GPRC_NOR0RegClassID:
266 case PPC::G8RCRegClassID:
267 case PPC::GPRCRegClassID: {
268 unsigned FP = TFI->hasFP(MF) ? 1 : 0;
269 return 32 - FP - DefaultSafety;
271 case PPC::F8RCRegClassID:
272 case PPC::F4RCRegClassID:
273 case PPC::QFRCRegClassID:
274 case PPC::QSRCRegClassID:
275 case PPC::QBRCRegClassID:
276 case PPC::VRRCRegClassID:
277 case PPC::VFRCRegClassID:
278 case PPC::VSLRCRegClassID:
279 case PPC::VSHRCRegClassID:
280 return 32 - DefaultSafety;
281 case PPC::VSRCRegClassID:
282 case PPC::VSFRCRegClassID:
283 case PPC::VSSRCRegClassID:
284 return 64 - DefaultSafety;
285 case PPC::CRRCRegClassID:
286 return 8 - DefaultSafety;
290 const TargetRegisterClass *
291 PPCRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
292 const MachineFunction &MF) const {
293 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
294 if (Subtarget.hasVSX()) {
295 // With VSX, we can inflate various sub-register classes to the full VSX
298 if (RC == &PPC::F8RCRegClass)
299 return &PPC::VSFRCRegClass;
300 else if (RC == &PPC::VRRCRegClass)
301 return &PPC::VSRCRegClass;
302 else if (RC == &PPC::F4RCRegClass && Subtarget.hasP8Vector())
303 return &PPC::VSSRCRegClass;
306 return TargetRegisterInfo::getLargestLegalSuperClass(RC, MF);
309 //===----------------------------------------------------------------------===//
310 // Stack Frame Processing methods
311 //===----------------------------------------------------------------------===//
313 /// lowerDynamicAlloc - Generate the code for allocating an object in the
314 /// current frame. The sequence of code with be in the general form
316 /// addi R0, SP, \#frameSize ; get the address of the previous frame
317 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size
318 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation
320 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const {
321 // Get the instruction.
322 MachineInstr &MI = *II;
323 // Get the instruction's basic block.
324 MachineBasicBlock &MBB = *MI.getParent();
325 // Get the basic block's function.
326 MachineFunction &MF = *MBB.getParent();
327 // Get the frame info.
328 MachineFrameInfo *MFI = MF.getFrameInfo();
329 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
330 // Get the instruction info.
331 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
332 // Determine whether 64-bit pointers are used.
333 bool LP64 = TM.isPPC64();
334 DebugLoc dl = MI.getDebugLoc();
336 // Get the maximum call stack size.
337 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
338 // Get the total frame size.
339 unsigned FrameSize = MFI->getStackSize();
341 // Get stack alignments.
342 const PPCFrameLowering *TFI = getFrameLowering(MF);
343 unsigned TargetAlign = TFI->getStackAlignment();
344 unsigned MaxAlign = MFI->getMaxAlignment();
345 assert((maxCallFrameSize & (MaxAlign-1)) == 0 &&
346 "Maximum call-frame size not sufficiently aligned");
348 // Determine the previous frame's address. If FrameSize can't be
349 // represented as 16 bits or we need special alignment, then we load the
350 // previous frame's address from 0(SP). Why not do an addis of the hi?
351 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
352 // Constructing the constant and adding would take 3 instructions.
353 // Fortunately, a frame greater than 32K is rare.
354 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
355 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
356 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
358 if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) {
359 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg)
363 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg)
367 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg)
372 bool KillNegSizeReg = MI.getOperand(1).isKill();
373 unsigned NegSizeReg = MI.getOperand(1).getReg();
375 // Grow the stack and update the stack pointer link, then determine the
376 // address of new allocated space.
378 if (MaxAlign > TargetAlign) {
379 unsigned UnalNegSizeReg = NegSizeReg;
380 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC);
382 // Unfortunately, there is no andi, only andi., and we can't insert that
383 // here because we might clobber cr0 while it is live.
384 BuildMI(MBB, II, dl, TII.get(PPC::LI8), NegSizeReg)
385 .addImm(~(MaxAlign-1));
387 unsigned NegSizeReg1 = NegSizeReg;
388 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC);
389 BuildMI(MBB, II, dl, TII.get(PPC::AND8), NegSizeReg)
390 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg))
391 .addReg(NegSizeReg1, RegState::Kill);
392 KillNegSizeReg = true;
395 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1)
396 .addReg(Reg, RegState::Kill)
398 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg));
399 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
401 .addImm(maxCallFrameSize);
403 if (MaxAlign > TargetAlign) {
404 unsigned UnalNegSizeReg = NegSizeReg;
405 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC);
407 // Unfortunately, there is no andi, only andi., and we can't insert that
408 // here because we might clobber cr0 while it is live.
409 BuildMI(MBB, II, dl, TII.get(PPC::LI), NegSizeReg)
410 .addImm(~(MaxAlign-1));
412 unsigned NegSizeReg1 = NegSizeReg;
413 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC);
414 BuildMI(MBB, II, dl, TII.get(PPC::AND), NegSizeReg)
415 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg))
416 .addReg(NegSizeReg1, RegState::Kill);
417 KillNegSizeReg = true;
420 BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1)
421 .addReg(Reg, RegState::Kill)
423 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg));
424 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
426 .addImm(maxCallFrameSize);
429 // Discard the DYNALLOC instruction.
433 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of
434 /// reserving a whole register (R0), we scrounge for one here. This generates
437 /// mfcr rA ; Move the conditional register into GPR rA.
438 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot.
439 /// stw rA, FI ; Store rA to the frame.
441 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II,
442 unsigned FrameIndex) const {
443 // Get the instruction.
444 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>
445 // Get the instruction's basic block.
446 MachineBasicBlock &MBB = *MI.getParent();
447 MachineFunction &MF = *MBB.getParent();
448 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
449 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
450 DebugLoc dl = MI.getDebugLoc();
452 bool LP64 = TM.isPPC64();
453 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
454 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
456 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
457 unsigned SrcReg = MI.getOperand(0).getReg();
459 // We need to store the CR in the low 4-bits of the saved value. First, issue
460 // an MFOCRF to save all of the CRBits and, if needed, kill the SrcReg.
461 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg)
462 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
464 // If the saved register wasn't CR0, shift the bits left so that they are in
466 if (SrcReg != PPC::CR0) {
468 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
470 // rlwinm rA, rA, ShiftBits, 0, 31.
471 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
472 .addReg(Reg1, RegState::Kill)
473 .addImm(getEncodingValue(SrcReg) * 4)
478 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW))
479 .addReg(Reg, RegState::Kill),
482 // Discard the pseudo instruction.
486 void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II,
487 unsigned FrameIndex) const {
488 // Get the instruction.
489 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset>
490 // Get the instruction's basic block.
491 MachineBasicBlock &MBB = *MI.getParent();
492 MachineFunction &MF = *MBB.getParent();
493 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
494 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
495 DebugLoc dl = MI.getDebugLoc();
497 bool LP64 = TM.isPPC64();
498 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
499 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
501 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
502 unsigned DestReg = MI.getOperand(0).getReg();
503 assert(MI.definesRegister(DestReg) &&
504 "RESTORE_CR does not define its destination");
506 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ),
509 // If the reloaded register isn't CR0, shift the bits right so that they are
510 // in the right CR's slot.
511 if (DestReg != PPC::CR0) {
513 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
515 unsigned ShiftBits = getEncodingValue(DestReg)*4;
516 // rlwinm r11, r11, 32-ShiftBits, 0, 31.
517 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
518 .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0)
522 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), DestReg)
523 .addReg(Reg, RegState::Kill);
525 // Discard the pseudo instruction.
529 void PPCRegisterInfo::lowerCRBitSpilling(MachineBasicBlock::iterator II,
530 unsigned FrameIndex) const {
531 // Get the instruction.
532 MachineInstr &MI = *II; // ; SPILL_CRBIT <SrcReg>, <offset>
533 // Get the instruction's basic block.
534 MachineBasicBlock &MBB = *MI.getParent();
535 MachineFunction &MF = *MBB.getParent();
536 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
537 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
538 DebugLoc dl = MI.getDebugLoc();
540 bool LP64 = TM.isPPC64();
541 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
542 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
544 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
545 unsigned SrcReg = MI.getOperand(0).getReg();
547 BuildMI(MBB, II, dl, TII.get(TargetOpcode::KILL),
548 getCRFromCRBit(SrcReg))
549 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
551 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg)
552 .addReg(getCRFromCRBit(SrcReg));
554 // If the saved register wasn't CR0LT, shift the bits left so that the bit to
555 // store is the first one. Mask all but that bit.
557 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
559 // rlwinm rA, rA, ShiftBits, 0, 0.
560 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
561 .addReg(Reg1, RegState::Kill)
562 .addImm(getEncodingValue(SrcReg))
563 .addImm(0).addImm(0);
565 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW))
566 .addReg(Reg, RegState::Kill),
569 // Discard the pseudo instruction.
573 void PPCRegisterInfo::lowerCRBitRestore(MachineBasicBlock::iterator II,
574 unsigned FrameIndex) const {
575 // Get the instruction.
576 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CRBIT <offset>
577 // Get the instruction's basic block.
578 MachineBasicBlock &MBB = *MI.getParent();
579 MachineFunction &MF = *MBB.getParent();
580 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
581 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
582 DebugLoc dl = MI.getDebugLoc();
584 bool LP64 = TM.isPPC64();
585 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
586 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
588 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
589 unsigned DestReg = MI.getOperand(0).getReg();
590 assert(MI.definesRegister(DestReg) &&
591 "RESTORE_CRBIT does not define its destination");
593 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ),
596 BuildMI(MBB, II, dl, TII.get(TargetOpcode::IMPLICIT_DEF), DestReg);
598 unsigned RegO = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
599 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), RegO)
600 .addReg(getCRFromCRBit(DestReg));
602 unsigned ShiftBits = getEncodingValue(DestReg);
603 // rlwimi r11, r10, 32-ShiftBits, ..., ...
604 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWIMI8 : PPC::RLWIMI), RegO)
605 .addReg(RegO, RegState::Kill).addReg(Reg, RegState::Kill)
606 .addImm(ShiftBits ? 32-ShiftBits : 0)
607 .addImm(ShiftBits).addImm(ShiftBits);
609 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF),
610 getCRFromCRBit(DestReg))
611 .addReg(RegO, RegState::Kill)
612 // Make sure we have a use dependency all the way through this
613 // sequence of instructions. We can't have the other bits in the CR
614 // modified in between the mfocrf and the mtocrf.
615 .addReg(getCRFromCRBit(DestReg), RegState::Implicit);
617 // Discard the pseudo instruction.
621 void PPCRegisterInfo::lowerVRSAVESpilling(MachineBasicBlock::iterator II,
622 unsigned FrameIndex) const {
623 // Get the instruction.
624 MachineInstr &MI = *II; // ; SPILL_VRSAVE <SrcReg>, <offset>
625 // Get the instruction's basic block.
626 MachineBasicBlock &MBB = *MI.getParent();
627 MachineFunction &MF = *MBB.getParent();
628 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
629 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
630 DebugLoc dl = MI.getDebugLoc();
632 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
633 unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC);
634 unsigned SrcReg = MI.getOperand(0).getReg();
636 BuildMI(MBB, II, dl, TII.get(PPC::MFVRSAVEv), Reg)
637 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
639 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::STW))
640 .addReg(Reg, RegState::Kill),
643 // Discard the pseudo instruction.
647 void PPCRegisterInfo::lowerVRSAVERestore(MachineBasicBlock::iterator II,
648 unsigned FrameIndex) const {
649 // Get the instruction.
650 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_VRSAVE <offset>
651 // Get the instruction's basic block.
652 MachineBasicBlock &MBB = *MI.getParent();
653 MachineFunction &MF = *MBB.getParent();
654 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
655 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
656 DebugLoc dl = MI.getDebugLoc();
658 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
659 unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC);
660 unsigned DestReg = MI.getOperand(0).getReg();
661 assert(MI.definesRegister(DestReg) &&
662 "RESTORE_VRSAVE does not define its destination");
664 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::LWZ),
667 BuildMI(MBB, II, dl, TII.get(PPC::MTVRSAVEv), DestReg)
668 .addReg(Reg, RegState::Kill);
670 // Discard the pseudo instruction.
675 PPCRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
676 unsigned Reg, int &FrameIdx) const {
677 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
678 // For the nonvolatile condition registers (CR2, CR3, CR4) in an SVR4
679 // ABI, return true to prevent allocating an additional frame slot.
680 // For 64-bit, the CR save area is at SP+8; the value of FrameIdx = 0
681 // is arbitrary and will be subsequently ignored. For 32-bit, we have
682 // previously created the stack slot if needed, so return its FrameIdx.
683 if (Subtarget.isSVR4ABI() && PPC::CR2 <= Reg && Reg <= PPC::CR4) {
687 const PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
688 FrameIdx = FI->getCRSpillFrameIndex();
695 // Figure out if the offset in the instruction must be a multiple of 4.
696 // This is true for instructions like "STD".
697 static bool usesIXAddr(const MachineInstr &MI) {
698 unsigned OpC = MI.getOpcode();
711 // Return the OffsetOperandNo given the FIOperandNum (and the instruction).
712 static unsigned getOffsetONFromFION(const MachineInstr &MI,
713 unsigned FIOperandNum) {
714 // Take into account whether it's an add or mem instruction
715 unsigned OffsetOperandNo = (FIOperandNum == 2) ? 1 : 2;
716 if (MI.isInlineAsm())
717 OffsetOperandNo = FIOperandNum - 1;
718 else if (MI.getOpcode() == TargetOpcode::STACKMAP ||
719 MI.getOpcode() == TargetOpcode::PATCHPOINT)
720 OffsetOperandNo = FIOperandNum + 1;
722 return OffsetOperandNo;
726 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
727 int SPAdj, unsigned FIOperandNum,
728 RegScavenger *RS) const {
729 assert(SPAdj == 0 && "Unexpected");
731 // Get the instruction.
732 MachineInstr &MI = *II;
733 // Get the instruction's basic block.
734 MachineBasicBlock &MBB = *MI.getParent();
735 // Get the basic block's function.
736 MachineFunction &MF = *MBB.getParent();
737 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
738 // Get the instruction info.
739 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
740 // Get the frame info.
741 MachineFrameInfo *MFI = MF.getFrameInfo();
742 DebugLoc dl = MI.getDebugLoc();
744 unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum);
746 // Get the frame index.
747 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
749 // Get the frame pointer save index. Users of this index are primarily
750 // DYNALLOC instructions.
751 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
752 int FPSI = FI->getFramePointerSaveIndex();
753 // Get the instruction opcode.
754 unsigned OpC = MI.getOpcode();
756 // Special case for dynamic alloca.
757 if (FPSI && FrameIndex == FPSI &&
758 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
759 lowerDynamicAlloc(II);
763 // Special case for pseudo-ops SPILL_CR and RESTORE_CR, etc.
764 if (OpC == PPC::SPILL_CR) {
765 lowerCRSpilling(II, FrameIndex);
767 } else if (OpC == PPC::RESTORE_CR) {
768 lowerCRRestore(II, FrameIndex);
770 } else if (OpC == PPC::SPILL_CRBIT) {
771 lowerCRBitSpilling(II, FrameIndex);
773 } else if (OpC == PPC::RESTORE_CRBIT) {
774 lowerCRBitRestore(II, FrameIndex);
776 } else if (OpC == PPC::SPILL_VRSAVE) {
777 lowerVRSAVESpilling(II, FrameIndex);
779 } else if (OpC == PPC::RESTORE_VRSAVE) {
780 lowerVRSAVERestore(II, FrameIndex);
784 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
785 MI.getOperand(FIOperandNum).ChangeToRegister(
786 FrameIndex < 0 ? getBaseRegister(MF) : getFrameRegister(MF), false);
788 // Figure out if the offset in the instruction is shifted right two bits.
789 bool isIXAddr = usesIXAddr(MI);
791 // If the instruction is not present in ImmToIdxMap, then it has no immediate
792 // form (and must be r+r).
793 bool noImmForm = !MI.isInlineAsm() && OpC != TargetOpcode::STACKMAP &&
794 OpC != TargetOpcode::PATCHPOINT && !ImmToIdxMap.count(OpC);
796 // Now add the frame object offset to the offset from r1.
797 int Offset = MFI->getObjectOffset(FrameIndex);
798 Offset += MI.getOperand(OffsetOperandNo).getImm();
800 // If we're not using a Frame Pointer that has been set to the value of the
801 // SP before having the stack size subtracted from it, then add the stack size
802 // to Offset to get the correct offset.
803 // Naked functions have stack size 0, although getStackSize may not reflect that
804 // because we didn't call all the pieces that compute it for naked functions.
805 if (!MF.getFunction()->hasFnAttribute(Attribute::Naked)) {
806 if (!(hasBasePointer(MF) && FrameIndex < 0))
807 Offset += MFI->getStackSize();
810 // If we can, encode the offset directly into the instruction. If this is a
811 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If
812 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits
813 // clear can be encoded. This is extremely uncommon, because normally you
814 // only "std" to a stack slot that is at least 4-byte aligned, but it can
815 // happen in invalid code.
816 assert(OpC != PPC::DBG_VALUE &&
817 "This should be handled in a target-independent way");
818 if (!noImmForm && ((isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0)) ||
819 OpC == TargetOpcode::STACKMAP ||
820 OpC == TargetOpcode::PATCHPOINT)) {
821 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
825 // The offset doesn't fit into a single register, scavenge one to build the
828 bool is64Bit = TM.isPPC64();
829 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
830 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
831 const TargetRegisterClass *RC = is64Bit ? G8RC : GPRC;
832 unsigned SRegHi = MF.getRegInfo().createVirtualRegister(RC),
833 SReg = MF.getRegInfo().createVirtualRegister(RC);
835 // Insert a set of rA with the full offset value before the ld, st, or add
836 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SRegHi)
837 .addImm(Offset >> 16);
838 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg)
839 .addReg(SRegHi, RegState::Kill)
842 // Convert into indexed form of the instruction:
844 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
845 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
846 unsigned OperandBase;
850 else if (OpC != TargetOpcode::INLINEASM) {
851 assert(ImmToIdxMap.count(OpC) &&
852 "No indexed form of load or store available!");
853 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second;
854 MI.setDesc(TII.get(NewOpcode));
857 OperandBase = OffsetOperandNo;
860 unsigned StackReg = MI.getOperand(FIOperandNum).getReg();
861 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false);
862 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true);
865 unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
866 const PPCFrameLowering *TFI = getFrameLowering(MF);
869 return TFI->hasFP(MF) ? PPC::R31 : PPC::R1;
871 return TFI->hasFP(MF) ? PPC::X31 : PPC::X1;
874 unsigned PPCRegisterInfo::getBaseRegister(const MachineFunction &MF) const {
875 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
876 if (!hasBasePointer(MF))
877 return getFrameRegister(MF);
882 if (Subtarget.isSVR4ABI() &&
883 TM.getRelocationModel() == Reloc::PIC_)
889 bool PPCRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
890 if (!EnableBasePointer)
892 if (AlwaysBasePointer)
895 // If we need to realign the stack, then the stack pointer can no longer
896 // serve as an offset into the caller's stack space. As a result, we need a
898 return needsStackRealignment(MF);
901 bool PPCRegisterInfo::canRealignStack(const MachineFunction &MF) const {
902 if (MF.getFunction()->hasFnAttribute("no-realign-stack"))
908 bool PPCRegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
909 const PPCFrameLowering *TFI = getFrameLowering(MF);
910 const MachineFrameInfo *MFI = MF.getFrameInfo();
911 const Function *F = MF.getFunction();
912 unsigned StackAlign = TFI->getStackAlignment();
913 bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) ||
914 F->hasFnAttribute(Attribute::StackAlignment));
916 return requiresRealignment && canRealignStack(MF);
919 /// Returns true if the instruction's frame index
920 /// reference would be better served by a base register other than FP
921 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
922 /// references it should create new base registers for.
923 bool PPCRegisterInfo::
924 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
925 assert(Offset < 0 && "Local offset must be negative");
927 // It's the load/store FI references that cause issues, as it can be difficult
928 // to materialize the offset if it won't fit in the literal field. Estimate
929 // based on the size of the local frame and some conservative assumptions
930 // about the rest of the stack frame (note, this is pre-regalloc, so
931 // we don't know everything for certain yet) whether this offset is likely
932 // to be out of range of the immediate. Return true if so.
934 // We only generate virtual base registers for loads and stores that have
935 // an r+i form. Return false for everything else.
936 unsigned OpC = MI->getOpcode();
937 if (!ImmToIdxMap.count(OpC))
940 // Don't generate a new virtual base register just to add zero to it.
941 if ((OpC == PPC::ADDI || OpC == PPC::ADDI8) &&
942 MI->getOperand(2).getImm() == 0)
945 MachineBasicBlock &MBB = *MI->getParent();
946 MachineFunction &MF = *MBB.getParent();
947 const PPCFrameLowering *TFI = getFrameLowering(MF);
948 unsigned StackEst = TFI->determineFrameLayout(MF, false, true);
950 // If we likely don't need a stack frame, then we probably don't need a
951 // virtual base register either.
955 // Estimate an offset from the stack pointer.
956 // The incoming offset is relating to the SP at the start of the function,
957 // but when we access the local it'll be relative to the SP after local
958 // allocation, so adjust our SP-relative offset by that allocation size.
961 // The frame pointer will point to the end of the stack, so estimate the
962 // offset as the difference between the object offset and the FP location.
963 return !isFrameOffsetLegal(MI, getBaseRegister(MF), Offset);
966 /// Insert defining instruction(s) for BaseReg to
967 /// be a pointer to FrameIdx at the beginning of the basic block.
968 void PPCRegisterInfo::
969 materializeFrameBaseRegister(MachineBasicBlock *MBB,
970 unsigned BaseReg, int FrameIdx,
971 int64_t Offset) const {
972 unsigned ADDriOpc = TM.isPPC64() ? PPC::ADDI8 : PPC::ADDI;
974 MachineBasicBlock::iterator Ins = MBB->begin();
975 DebugLoc DL; // Defaults to "unknown"
976 if (Ins != MBB->end())
977 DL = Ins->getDebugLoc();
979 const MachineFunction &MF = *MBB->getParent();
980 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
981 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
982 const MCInstrDesc &MCID = TII.get(ADDriOpc);
983 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
984 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
986 BuildMI(*MBB, Ins, DL, MCID, BaseReg)
987 .addFrameIndex(FrameIdx).addImm(Offset);
990 void PPCRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
991 int64_t Offset) const {
992 unsigned FIOperandNum = 0;
993 while (!MI.getOperand(FIOperandNum).isFI()) {
995 assert(FIOperandNum < MI.getNumOperands() &&
996 "Instr doesn't have FrameIndex operand!");
999 MI.getOperand(FIOperandNum).ChangeToRegister(BaseReg, false);
1000 unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum);
1001 Offset += MI.getOperand(OffsetOperandNo).getImm();
1002 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
1004 MachineBasicBlock &MBB = *MI.getParent();
1005 MachineFunction &MF = *MBB.getParent();
1006 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1007 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1008 const MCInstrDesc &MCID = MI.getDesc();
1009 MachineRegisterInfo &MRI = MF.getRegInfo();
1010 MRI.constrainRegClass(BaseReg,
1011 TII.getRegClass(MCID, FIOperandNum, this, MF));
1014 bool PPCRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
1016 int64_t Offset) const {
1017 unsigned FIOperandNum = 0;
1018 while (!MI->getOperand(FIOperandNum).isFI()) {
1020 assert(FIOperandNum < MI->getNumOperands() &&
1021 "Instr doesn't have FrameIndex operand!");
1024 unsigned OffsetOperandNo = getOffsetONFromFION(*MI, FIOperandNum);
1025 Offset += MI->getOperand(OffsetOperandNo).getImm();
1027 return MI->getOpcode() == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm
1028 MI->getOpcode() == TargetOpcode::STACKMAP ||
1029 MI->getOpcode() == TargetOpcode::PATCHPOINT ||
1030 (isInt<16>(Offset) && (!usesIXAddr(*MI) || (Offset & 3) == 0));