1 //===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetRegisterInfo
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "reginfo"
17 #include "PPCInstrBuilder.h"
18 #include "PPCMachineFunctionInfo.h"
19 #include "PPCRegisterInfo.h"
20 #include "PPCFrameLowering.h"
21 #include "PPCSubtarget.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/Function.h"
25 #include "llvm/Type.h"
26 #include "llvm/CodeGen/ValueTypes.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineModuleInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/RegisterScavenging.h"
33 #include "llvm/Target/TargetFrameLowering.h"
34 #include "llvm/Target/TargetInstrInfo.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
37 #include "llvm/Support/CommandLine.h"
38 #include "llvm/Support/Debug.h"
39 #include "llvm/Support/ErrorHandling.h"
40 #include "llvm/Support/MathExtras.h"
41 #include "llvm/Support/raw_ostream.h"
42 #include "llvm/ADT/BitVector.h"
43 #include "llvm/ADT/STLExtras.h"
46 #define GET_REGINFO_TARGET_DESC
47 #include "PPCGenRegisterInfo.inc"
50 cl::opt<bool> DisablePPC32RS("disable-ppc32-regscavenger",
52 cl::desc("Disable PPC32 register scavenger"),
54 cl::opt<bool> DisablePPC64RS("disable-ppc64-regscavenger",
56 cl::desc("Disable PPC64 register scavenger"),
62 // FIXME (64-bit): Should be inlined.
64 PPCRegisterInfo::requiresRegisterScavenging(const MachineFunction &) const {
65 return ((!DisablePPC32RS && !Subtarget.isPPC64()) ||
66 (!DisablePPC64RS && Subtarget.isPPC64()));
69 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST,
70 const TargetInstrInfo &tii)
71 : PPCGenRegisterInfo(ST.isPPC64() ? PPC::LR8 : PPC::LR,
73 ST.isPPC64() ? 0 : 1),
74 Subtarget(ST), TII(tii) {
75 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
76 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
77 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
78 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
79 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
80 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
81 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
82 ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
85 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8;
86 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8;
87 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8;
88 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX;
89 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32;
92 /// getPointerRegClass - Return the register class to use to hold pointers.
93 /// This is used for addressing modes.
94 const TargetRegisterClass *
95 PPCRegisterInfo::getPointerRegClass(unsigned Kind) const {
96 if (Subtarget.isPPC64())
97 return &PPC::G8RCRegClass;
98 return &PPC::GPRCRegClass;
102 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
103 // 32-bit Darwin calling convention.
104 static const uint16_t Darwin32_CalleeSavedRegs[] = {
105 PPC::R13, PPC::R14, PPC::R15,
106 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
107 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
108 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
109 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
111 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
112 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
113 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
114 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
117 PPC::CR2, PPC::CR3, PPC::CR4,
118 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
119 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
120 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
125 // 32-bit SVR4 calling convention.
126 static const uint16_t SVR4_CalleeSavedRegs[] = {
128 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
129 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
130 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
131 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
133 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
134 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
135 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
136 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
139 PPC::CR2, PPC::CR3, PPC::CR4,
143 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
144 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
145 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
149 // 64-bit Darwin calling convention.
150 static const uint16_t Darwin64_CalleeSavedRegs[] = {
152 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
153 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
154 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
155 PPC::X28, PPC::X29, PPC::X30, PPC::X31,
157 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
158 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
159 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
160 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
163 PPC::CR2, PPC::CR3, PPC::CR4,
164 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
165 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
166 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
171 // 64-bit SVR4 calling convention.
172 static const uint16_t SVR4_64_CalleeSavedRegs[] = {
174 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
175 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
176 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
177 PPC::X28, PPC::X29, PPC::X30, PPC::X31,
179 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
180 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
181 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
182 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
185 PPC::CR2, PPC::CR3, PPC::CR4,
189 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
190 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
191 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
196 if (Subtarget.isDarwinABI())
197 return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegs :
198 Darwin32_CalleeSavedRegs;
200 return Subtarget.isPPC64() ? SVR4_64_CalleeSavedRegs : SVR4_CalleeSavedRegs;
203 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
204 BitVector Reserved(getNumRegs());
205 const PPCFrameLowering *PPCFI =
206 static_cast<const PPCFrameLowering*>(MF.getTarget().getFrameLowering());
208 Reserved.set(PPC::R0);
209 Reserved.set(PPC::R1);
210 Reserved.set(PPC::LR);
211 Reserved.set(PPC::LR8);
212 Reserved.set(PPC::RM);
214 // The SVR4 ABI reserves r2 and r13
215 if (Subtarget.isSVR4ABI()) {
216 Reserved.set(PPC::R2); // System-reserved register
217 Reserved.set(PPC::R13); // Small Data Area pointer register
219 // Reserve R2 on Darwin to hack around the problem of save/restore of CR
220 // when the stack frame is too big to address directly; we need two regs.
222 if (Subtarget.isDarwinABI()) {
223 Reserved.set(PPC::R2);
226 // On PPC64, r13 is the thread pointer. Never allocate this register.
227 // Note that this is over conservative, as it also prevents allocation of R31
228 // when the FP is not needed.
229 if (Subtarget.isPPC64()) {
230 Reserved.set(PPC::R13);
231 Reserved.set(PPC::R31);
233 Reserved.set(PPC::X0);
234 Reserved.set(PPC::X1);
235 Reserved.set(PPC::X13);
236 Reserved.set(PPC::X31);
238 // The 64-bit SVR4 ABI reserves r2 for the TOC pointer.
239 if (Subtarget.isSVR4ABI()) {
240 Reserved.set(PPC::X2);
242 // Reserve X2 on Darwin to hack around the problem of save/restore of CR
243 // when the stack frame is too big to address directly; we need two regs.
245 if (Subtarget.isDarwinABI()) {
246 Reserved.set(PPC::X2);
250 if (PPCFI->needsFP(MF))
251 Reserved.set(PPC::R31);
257 PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
258 MachineFunction &MF) const {
259 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
260 const unsigned DefaultSafety = 1;
262 switch (RC->getID()) {
265 case PPC::G8RCRegClassID:
266 case PPC::GPRCRegClassID: {
267 unsigned FP = TFI->hasFP(MF) ? 1 : 0;
268 return 32 - FP - DefaultSafety;
270 case PPC::F8RCRegClassID:
271 case PPC::F4RCRegClassID:
272 case PPC::VRRCRegClassID:
273 return 32 - DefaultSafety;
274 case PPC::CRRCRegClassID:
275 return 8 - DefaultSafety;
279 //===----------------------------------------------------------------------===//
280 // Stack Frame Processing methods
281 //===----------------------------------------------------------------------===//
283 void PPCRegisterInfo::
284 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
285 MachineBasicBlock::iterator I) const {
286 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
287 I->getOpcode() == PPC::ADJCALLSTACKUP) {
288 // Add (actually subtract) back the amount the callee popped on return.
289 if (int CalleeAmt = I->getOperand(1).getImm()) {
290 bool is64Bit = Subtarget.isPPC64();
292 unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1;
293 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0;
294 unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI;
295 unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4;
296 unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS;
297 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI;
298 MachineInstr *MI = I;
299 DebugLoc dl = MI->getDebugLoc();
301 if (isInt<16>(CalleeAmt)) {
302 BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg)
303 .addReg(StackReg, RegState::Kill)
306 MachineBasicBlock::iterator MBBI = I;
307 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
308 .addImm(CalleeAmt >> 16);
309 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
310 .addReg(TmpReg, RegState::Kill)
311 .addImm(CalleeAmt & 0xFFFF);
312 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr), StackReg)
313 .addReg(StackReg, RegState::Kill)
318 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
322 /// findScratchRegister - Find a 'free' PPC register. Try for a call-clobbered
323 /// register first and then a spilled callee-saved register if that fails.
325 unsigned findScratchRegister(MachineBasicBlock::iterator II, RegScavenger *RS,
326 const TargetRegisterClass *RC, int SPAdj) {
327 assert(RS && "Register scavenging must be on");
328 unsigned Reg = RS->FindUnusedReg(RC);
329 // FIXME: move ARM callee-saved reg scan to target independent code, then
330 // search for already spilled CS register here.
332 Reg = RS->scavengeRegister(RC, II, SPAdj);
336 /// lowerDynamicAlloc - Generate the code for allocating an object in the
337 /// current frame. The sequence of code with be in the general form
339 /// addi R0, SP, \#frameSize ; get the address of the previous frame
340 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size
341 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation
343 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II,
344 int SPAdj, RegScavenger *RS) const {
345 // Get the instruction.
346 MachineInstr &MI = *II;
347 // Get the instruction's basic block.
348 MachineBasicBlock &MBB = *MI.getParent();
349 // Get the basic block's function.
350 MachineFunction &MF = *MBB.getParent();
351 // Get the frame info.
352 MachineFrameInfo *MFI = MF.getFrameInfo();
353 // Determine whether 64-bit pointers are used.
354 bool LP64 = Subtarget.isPPC64();
355 DebugLoc dl = MI.getDebugLoc();
357 // Get the maximum call stack size.
358 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
359 // Get the total frame size.
360 unsigned FrameSize = MFI->getStackSize();
362 // Get stack alignments.
363 unsigned TargetAlign = MF.getTarget().getFrameLowering()->getStackAlignment();
364 unsigned MaxAlign = MFI->getMaxAlignment();
365 if (MaxAlign > TargetAlign)
366 report_fatal_error("Dynamic alloca with large aligns not supported");
368 // Determine the previous frame's address. If FrameSize can't be
369 // represented as 16 bits or we need special alignment, then we load the
370 // previous frame's address from 0(SP). Why not do an addis of the hi?
371 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
372 // Constructing the constant and adding would take 3 instructions.
373 // Fortunately, a frame greater than 32K is rare.
374 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
375 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
376 const TargetRegisterClass *RC = LP64 ? G8RC : GPRC;
378 // FIXME (64-bit): Use "findScratchRegister"
380 if (requiresRegisterScavenging(MF))
381 Reg = findScratchRegister(II, RS, RC, SPAdj);
385 if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) {
386 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg)
390 if (requiresRegisterScavenging(MF)) // FIXME (64-bit): Use "true" part.
391 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg)
395 BuildMI(MBB, II, dl, TII.get(PPC::LD), PPC::X0)
399 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg)
404 // Grow the stack and update the stack pointer link, then determine the
405 // address of new allocated space.
407 if (requiresRegisterScavenging(MF)) // FIXME (64-bit): Use "true" part.
408 BuildMI(MBB, II, dl, TII.get(PPC::STDUX))
409 .addReg(Reg, RegState::Kill)
410 .addReg(PPC::X1, RegState::Define)
411 .addReg(MI.getOperand(1).getReg());
413 BuildMI(MBB, II, dl, TII.get(PPC::STDUX))
414 .addReg(PPC::X0, RegState::Kill)
415 .addReg(PPC::X1, RegState::Define)
416 .addReg(MI.getOperand(1).getReg());
418 if (!MI.getOperand(1).isKill())
419 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
421 .addImm(maxCallFrameSize);
423 // Implicitly kill the register.
424 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
426 .addImm(maxCallFrameSize)
427 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill);
429 BuildMI(MBB, II, dl, TII.get(PPC::STWUX))
430 .addReg(Reg, RegState::Kill)
431 .addReg(PPC::R1, RegState::Define)
432 .addReg(MI.getOperand(1).getReg());
434 if (!MI.getOperand(1).isKill())
435 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
437 .addImm(maxCallFrameSize);
439 // Implicitly kill the register.
440 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
442 .addImm(maxCallFrameSize)
443 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill);
446 // Discard the DYNALLOC instruction.
450 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of
451 /// reserving a whole register (R0), we scrounge for one here. This generates
454 /// mfcr rA ; Move the conditional register into GPR rA.
455 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot.
456 /// stw rA, FI ; Store rA to the frame.
458 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II,
459 unsigned FrameIndex, int SPAdj,
460 RegScavenger *RS) const {
461 // Get the instruction.
462 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>
463 // Get the instruction's basic block.
464 MachineBasicBlock &MBB = *MI.getParent();
465 DebugLoc dl = MI.getDebugLoc();
467 // FIXME: Once LLVM supports creating virtual registers here, or the register
468 // scavenger can return multiple registers, stop using reserved registers
473 bool LP64 = Subtarget.isPPC64();
474 unsigned Reg = Subtarget.isDarwinABI() ? (LP64 ? PPC::X2 : PPC::R2) :
475 (LP64 ? PPC::X0 : PPC::R0);
476 unsigned SrcReg = MI.getOperand(0).getReg();
478 // We need to store the CR in the low 4-bits of the saved value. First, issue
479 // an MFCRpsued to save all of the CRBits and, if needed, kill the SrcReg.
480 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFCR8pseud : PPC::MFCRpseud), Reg)
481 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
483 // If the saved register wasn't CR0, shift the bits left so that they are in
485 if (SrcReg != PPC::CR0)
486 // rlwinm rA, rA, ShiftBits, 0, 31.
487 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
488 .addReg(Reg, RegState::Kill)
489 .addImm(getPPCRegisterNumbering(SrcReg) * 4)
493 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW))
494 .addReg(Reg, getKillRegState(MI.getOperand(1).getImm())),
497 // Discard the pseudo instruction.
501 void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II,
502 unsigned FrameIndex, int SPAdj,
503 RegScavenger *RS) const {
504 // Get the instruction.
505 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset>
506 // Get the instruction's basic block.
507 MachineBasicBlock &MBB = *MI.getParent();
508 DebugLoc dl = MI.getDebugLoc();
510 // FIXME: Once LLVM supports creating virtual registers here, or the register
511 // scavenger can return multiple registers, stop using reserved registers
516 bool LP64 = Subtarget.isPPC64();
517 unsigned Reg = Subtarget.isDarwinABI() ? (LP64 ? PPC::X2 : PPC::R2) :
518 (LP64 ? PPC::X0 : PPC::R0);
519 unsigned DestReg = MI.getOperand(0).getReg();
520 assert(MI.definesRegister(DestReg) &&
521 "RESTORE_CR does not define its destination");
523 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ),
526 // If the reloaded register isn't CR0, shift the bits right so that they are
527 // in the right CR's slot.
528 if (DestReg != PPC::CR0) {
529 unsigned ShiftBits = getPPCRegisterNumbering(DestReg)*4;
530 // rlwinm r11, r11, 32-ShiftBits, 0, 31.
531 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
532 .addReg(Reg).addImm(32-ShiftBits).addImm(0)
536 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTCRF8 : PPC::MTCRF), DestReg)
539 // Discard the pseudo instruction.
544 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
545 int SPAdj, RegScavenger *RS) const {
546 assert(SPAdj == 0 && "Unexpected");
548 // Get the instruction.
549 MachineInstr &MI = *II;
550 // Get the instruction's basic block.
551 MachineBasicBlock &MBB = *MI.getParent();
552 // Get the basic block's function.
553 MachineFunction &MF = *MBB.getParent();
554 // Get the frame info.
555 MachineFrameInfo *MFI = MF.getFrameInfo();
556 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
557 DebugLoc dl = MI.getDebugLoc();
559 // Find out which operand is the frame index.
560 unsigned FIOperandNo = 0;
561 while (!MI.getOperand(FIOperandNo).isFI()) {
563 assert(FIOperandNo != MI.getNumOperands() &&
564 "Instr doesn't have FrameIndex operand!");
566 // Take into account whether it's an add or mem instruction
567 unsigned OffsetOperandNo = (FIOperandNo == 2) ? 1 : 2;
568 if (MI.isInlineAsm())
569 OffsetOperandNo = FIOperandNo-1;
571 // Get the frame index.
572 int FrameIndex = MI.getOperand(FIOperandNo).getIndex();
574 // Get the frame pointer save index. Users of this index are primarily
575 // DYNALLOC instructions.
576 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
577 int FPSI = FI->getFramePointerSaveIndex();
578 // Get the instruction opcode.
579 unsigned OpC = MI.getOpcode();
581 // Special case for dynamic alloca.
582 if (FPSI && FrameIndex == FPSI &&
583 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
584 lowerDynamicAlloc(II, SPAdj, RS);
588 // Special case for pseudo-ops SPILL_CR and RESTORE_CR.
589 if (requiresRegisterScavenging(MF)) {
590 if (OpC == PPC::SPILL_CR) {
591 lowerCRSpilling(II, FrameIndex, SPAdj, RS);
593 } else if (OpC == PPC::RESTORE_CR) {
594 lowerCRRestore(II, FrameIndex, SPAdj, RS);
599 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
601 bool is64Bit = Subtarget.isPPC64();
602 MI.getOperand(FIOperandNo).ChangeToRegister(TFI->hasFP(MF) ?
603 (is64Bit ? PPC::X31 : PPC::R31) :
604 (is64Bit ? PPC::X1 : PPC::R1),
607 // Figure out if the offset in the instruction is shifted right two bits. This
608 // is true for instructions like "STD", which the machine implicitly adds two
610 bool isIXAddr = false;
620 // Now add the frame object offset to the offset from r1.
621 int Offset = MFI->getObjectOffset(FrameIndex);
623 Offset += MI.getOperand(OffsetOperandNo).getImm();
625 Offset += MI.getOperand(OffsetOperandNo).getImm() << 2;
627 // If we're not using a Frame Pointer that has been set to the value of the
628 // SP before having the stack size subtracted from it, then add the stack size
629 // to Offset to get the correct offset.
630 // Naked functions have stack size 0, although getStackSize may not reflect that
631 // because we didn't call all the pieces that compute it for naked functions.
632 if (!MF.getFunction()->hasFnAttr(Attribute::Naked))
633 Offset += MFI->getStackSize();
635 // If we can, encode the offset directly into the instruction. If this is a
636 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If
637 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits
638 // clear can be encoded. This is extremely uncommon, because normally you
639 // only "std" to a stack slot that is at least 4-byte aligned, but it can
640 // happen in invalid code.
641 if (isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0)) {
643 Offset >>= 2; // The actual encoded value has the low two bits zero.
644 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
648 // The offset doesn't fit into a single register, scavenge one to build the
652 if (requiresRegisterScavenging(MF)) {
653 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
654 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
655 SReg = findScratchRegister(II, RS, is64Bit ? G8RC : GPRC, SPAdj);
657 SReg = is64Bit ? PPC::X0 : PPC::R0;
659 // Insert a set of rA with the full offset value before the ld, st, or add
660 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SReg)
661 .addImm(Offset >> 16);
662 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg)
663 .addReg(SReg, RegState::Kill)
666 // Convert into indexed form of the instruction:
668 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
669 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
670 unsigned OperandBase;
672 if (OpC != TargetOpcode::INLINEASM) {
673 assert(ImmToIdxMap.count(OpC) &&
674 "No indexed form of load or store available!");
675 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second;
676 MI.setDesc(TII.get(NewOpcode));
679 OperandBase = OffsetOperandNo;
682 unsigned StackReg = MI.getOperand(FIOperandNo).getReg();
683 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false);
684 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true);
687 unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
688 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
690 if (!Subtarget.isPPC64())
691 return TFI->hasFP(MF) ? PPC::R31 : PPC::R1;
693 return TFI->hasFP(MF) ? PPC::X31 : PPC::X1;
696 unsigned PPCRegisterInfo::getEHExceptionRegister() const {
697 return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3;
700 unsigned PPCRegisterInfo::getEHHandlerRegister() const {
701 return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4;