1 //===- PPC32RegisterInfo.cpp - PowerPC32 Register Information ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC32 implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "reginfo"
16 #include "PowerPCInstrBuilder.h"
17 #include "PPC32RegisterInfo.h"
18 #include "llvm/Constants.h"
19 #include "llvm/Type.h"
20 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/Target/TargetFrameInfo.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/ADT/STLExtras.h"
35 // Switch toggling compilation for AIX
36 extern cl::opt<bool> AIX;
39 PPC32RegisterInfo::PPC32RegisterInfo()
40 : PPC32GenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP) {
41 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
42 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
43 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
44 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
45 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
46 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
47 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
48 ImmToIdxMap[PPC::ADDI] = PPC::ADD;
51 static const TargetRegisterClass *getClass(unsigned SrcReg) {
52 if (PPC32::FPRCRegisterClass->contains(SrcReg))
53 return PPC32::FPRCRegisterClass;
54 assert(PPC32::GPRCRegisterClass->contains(SrcReg) && "Reg not FPR or GPR");
55 return PPC32::GPRCRegisterClass;
58 static unsigned getIdx(const TargetRegisterClass *RC) {
59 if (RC == PPC32::GPRCRegisterClass) {
60 switch (RC->getSize()) {
61 default: assert(0 && "Invalid data size!");
66 } else if (RC == PPC32::FPRCRegisterClass) {
67 switch (RC->getSize()) {
68 default: assert(0 && "Invalid data size!");
73 std::cerr << "Invalid register class to getIdx()!\n";
78 PPC32RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
79 MachineBasicBlock::iterator MI,
80 unsigned SrcReg, int FrameIdx) const {
81 static const unsigned Opcode[] = {
82 PPC::STB, PPC::STH, PPC::STW, PPC::STFS, PPC::STFD
84 unsigned OC = Opcode[getIdx(getClass(SrcReg))];
85 if (SrcReg == PPC::LR) {
86 BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11).addReg(PPC::LR);
87 BuildMI(MBB, MI, PPC::IMPLICIT_DEF, 0, PPC::R0);
88 addFrameReference(BuildMI(MBB, MI, OC, 3).addReg(PPC::R11),FrameIdx);
90 BuildMI(MBB, MI, PPC::IMPLICIT_DEF, 0, PPC::R0);
91 addFrameReference(BuildMI(MBB, MI, OC, 3).addReg(SrcReg),FrameIdx);
96 PPC32RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
97 MachineBasicBlock::iterator MI,
98 unsigned DestReg, int FrameIdx) const{
99 static const unsigned Opcode[] = {
100 PPC::LBZ, PPC::LHZ, PPC::LWZ, PPC::LFS, PPC::LFD
102 unsigned OC = Opcode[getIdx(getClass(DestReg))];
103 if (DestReg == PPC::LR) {
104 BuildMI(MBB, MI, PPC::IMPLICIT_DEF, 0, PPC::R0);
105 addFrameReference(BuildMI(MBB, MI, OC, 2, PPC::R11), FrameIdx);
106 BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11);
108 BuildMI(MBB, MI, PPC::IMPLICIT_DEF, 0, PPC::R0);
109 addFrameReference(BuildMI(MBB, MI, OC, 2, DestReg), FrameIdx);
113 void PPC32RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
114 MachineBasicBlock::iterator MI,
115 unsigned DestReg, unsigned SrcReg,
116 const TargetRegisterClass *RC) const {
119 if (RC == PPC32::GPRCRegisterClass) {
120 BuildMI(MBB, MI, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
121 } else if (RC == PPC32::FPRCRegisterClass) {
122 BuildMI(MBB, MI, PPC::FMR, 1, DestReg).addReg(SrcReg);
124 std::cerr << "Attempt to copy register that is not GPR or FPR";
129 //===----------------------------------------------------------------------===//
130 // Stack Frame Processing methods
131 //===----------------------------------------------------------------------===//
133 // hasFP - Return true if the specified function should have a dedicated frame
134 // pointer register. This is true if the function has variable sized allocas or
135 // if frame pointer elimination is disabled.
137 static bool hasFP(MachineFunction &MF) {
138 MachineFrameInfo *MFI = MF.getFrameInfo();
139 return MFI->hasVarSizedObjects();
142 void PPC32RegisterInfo::
143 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
144 MachineBasicBlock::iterator I) const {
146 // If we have a frame pointer, convert as follows:
147 // ADJCALLSTACKDOWN -> addi, r1, r1, -amount
148 // ADJCALLSTACKUP -> addi, r1, r1, amount
149 MachineInstr *Old = I;
150 unsigned Amount = Old->getOperand(0).getImmedValue();
152 // We need to keep the stack aligned properly. To do this, we round the
153 // amount of space needed for the outgoing arguments up to the next
154 // alignment boundary.
155 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
156 Amount = (Amount+Align-1)/Align*Align;
158 // Replace the pseudo instruction with a new instruction...
159 if (Old->getOpcode() == PPC::ADJCALLSTACKDOWN) {
160 MBB.insert(I, BuildMI(PPC::ADDI, 2, PPC::R1).addReg(PPC::R1)
163 assert(Old->getOpcode() == PPC::ADJCALLSTACKUP);
164 MBB.insert(I, BuildMI(PPC::ADDI, 2, PPC::R1).addReg(PPC::R1)
173 PPC32RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
175 MachineInstr &MI = *II;
176 MachineBasicBlock &MBB = *MI.getParent();
177 MachineFunction &MF = *MBB.getParent();
179 while (!MI.getOperand(i).isFrameIndex()) {
181 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
184 int FrameIndex = MI.getOperand(i).getFrameIndex();
186 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
187 MI.SetMachineOperandReg(i, hasFP(MF) ? PPC::R31 : PPC::R1);
189 // Take into account whether it's an add or mem instruction
190 unsigned OffIdx = (i == 2) ? 1 : 2;
192 // Now add the frame object offset to the offset from r1.
193 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
194 MI.getOperand(OffIdx).getImmedValue();
196 // If we're not using a Frame Pointer that has been set to the value of the
197 // SP before having the stack size subtracted from it, then add the stack size
198 // to Offset to get the correct offset.
199 Offset += MF.getFrameInfo()->getStackSize();
201 if (Offset > 32767 || Offset < -32768) {
202 // Insert a set of r0 with the full offset value before the ld, st, or add
203 MachineBasicBlock *MBB = MI.getParent();
204 MBB->insert(II, BuildMI(PPC::LIS, 1, PPC::R0).addSImm(Offset >> 16));
205 MBB->insert(II, BuildMI(PPC::ORI, 2, PPC::R0).addReg(PPC::R0)
207 // convert into indexed form of the instruction
208 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
209 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
210 unsigned NewOpcode = const_cast<std::map<unsigned, unsigned>& >(ImmToIdxMap)[MI.getOpcode()];
211 assert(NewOpcode && "No indexed form of load or store available!");
212 MI.setOpcode(NewOpcode);
213 MI.SetMachineOperandReg(1, MI.getOperand(i).getReg());
214 MI.SetMachineOperandReg(2, PPC::R0);
216 MI.SetMachineOperandConst(OffIdx,MachineOperand::MO_SignExtendedImmed,Offset);
221 void PPC32RegisterInfo::emitPrologue(MachineFunction &MF) const {
222 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
223 MachineBasicBlock::iterator MBBI = MBB.begin();
224 MachineFrameInfo *MFI = MF.getFrameInfo();
227 // Get the number of bytes to allocate from the FrameInfo
228 unsigned NumBytes = MFI->getStackSize();
230 // If we have calls, we cannot use the red zone to store callee save registers
231 // and we must set up a stack frame, so calculate the necessary size here.
232 if (MFI->hasCalls()) {
233 // We reserve argument space for call sites in the function immediately on
234 // entry to the current function. This eliminates the need for add/sub
235 // brackets around call sites.
236 NumBytes += MFI->getMaxCallFrameSize();
239 // Do we need to allocate space on the stack?
240 if (NumBytes == 0) return;
242 // Add the size of R1 to NumBytes size for the store of R1 to the bottom
243 // of the stack and round the size to a multiple of the alignment.
244 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
245 unsigned GPRSize = getSpillSize(PPC::R1)/8;
246 unsigned Size = hasFP(MF) ? GPRSize + GPRSize : GPRSize;
247 NumBytes = (NumBytes+Size+Align-1)/Align*Align;
249 // Update frame info to pretend that this is part of the stack...
250 MFI->setStackSize(NumBytes);
252 // adjust stack pointer: r1 -= numbytes
253 if (NumBytes <= 32768) {
254 MI=BuildMI(PPC::STWU,3).addReg(PPC::R1).addSImm(-NumBytes).addReg(PPC::R1);
255 MBB.insert(MBBI, MI);
257 int NegNumbytes = -NumBytes;
258 MI = BuildMI(PPC::LIS, 1, PPC::R0).addSImm(NegNumbytes >> 16);
259 MBB.insert(MBBI, MI);
260 MI = BuildMI(PPC::ORI, 2, PPC::R0).addReg(PPC::R0)
261 .addImm(NegNumbytes & 0xFFFF);
262 MBB.insert(MBBI, MI);
263 MI = BuildMI(PPC::STWUX, 3).addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
264 MBB.insert(MBBI, MI);
268 MI = BuildMI(PPC::STW, 3).addReg(PPC::R31).addSImm(GPRSize).addReg(PPC::R1);
269 MBB.insert(MBBI, MI);
270 MI = BuildMI(PPC::OR, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1);
271 MBB.insert(MBBI, MI);
275 void PPC32RegisterInfo::emitEpilogue(MachineFunction &MF,
276 MachineBasicBlock &MBB) const {
277 const MachineFrameInfo *MFI = MF.getFrameInfo();
278 MachineBasicBlock::iterator MBBI = prior(MBB.end());
280 assert(MBBI->getOpcode() == PPC::BLR &&
281 "Can only insert epilog into returning blocks");
283 // Get the number of bytes allocated from the FrameInfo...
284 unsigned NumBytes = MFI->getStackSize();
285 unsigned GPRSize = getSpillSize(PPC::R31)/8;
289 MI = BuildMI(PPC::OR, 2, PPC::R1).addReg(PPC::R31).addReg(PPC::R31);
290 MBB.insert(MBBI, MI);
291 MI = BuildMI(PPC::LWZ, 2, PPC::R31).addSImm(GPRSize).addReg(PPC::R31);
292 MBB.insert(MBBI, MI);
294 MI = BuildMI(PPC::LWZ, 2, PPC::R1).addSImm(0).addReg(PPC::R1);
295 MBB.insert(MBBI, MI);
299 #include "PPC32GenRegisterInfo.inc"
301 const TargetRegisterClass*
302 PPC32RegisterInfo::getRegClassForType(const Type* Ty) const {
303 switch (Ty->getTypeID()) {
304 default: assert(0 && "Invalid type to getClass!");
306 case Type::ULongTyID: assert(0 && "Long values can't fit in registers!");
308 case Type::SByteTyID:
309 case Type::UByteTyID:
310 case Type::ShortTyID:
311 case Type::UShortTyID:
314 case Type::PointerTyID: return &GPRCInstance;
316 case Type::FloatTyID:
317 case Type::DoubleTyID: return &FPRCInstance;