1 //===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetRegisterInfo
13 //===----------------------------------------------------------------------===//
15 #include "PPCRegisterInfo.h"
17 #include "PPCFrameLowering.h"
18 #include "PPCInstrBuilder.h"
19 #include "PPCMachineFunctionInfo.h"
20 #include "PPCSubtarget.h"
21 #include "PPCTargetMachine.h"
22 #include "llvm/ADT/BitVector.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineModuleInfo.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/RegisterScavenging.h"
30 #include "llvm/IR/CallingConv.h"
31 #include "llvm/IR/Constants.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/IR/Type.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include "llvm/Target/TargetFrameLowering.h"
40 #include "llvm/Target/TargetInstrInfo.h"
41 #include "llvm/Target/TargetMachine.h"
42 #include "llvm/Target/TargetOptions.h"
47 #define DEBUG_TYPE "reginfo"
49 #define GET_REGINFO_TARGET_DESC
50 #include "PPCGenRegisterInfo.inc"
53 EnableBasePointer("ppc-use-base-pointer", cl::Hidden, cl::init(true),
54 cl::desc("Enable use of a base pointer for complex stack frames"));
57 AlwaysBasePointer("ppc-always-use-base-pointer", cl::Hidden, cl::init(false),
58 cl::desc("Force the use of a base pointer in every function"));
60 PPCRegisterInfo::PPCRegisterInfo(const PPCTargetMachine &TM)
61 : PPCGenRegisterInfo(TM.isPPC64() ? PPC::LR8 : PPC::LR,
63 TM.isPPC64() ? 0 : 1),
65 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
66 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
67 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
68 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
69 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
70 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
71 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
72 ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
73 ImmToIdxMap[PPC::LWA_32] = PPC::LWAX_32;
76 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8;
77 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8;
78 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8;
79 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX;
80 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8;
83 /// getPointerRegClass - Return the register class to use to hold pointers.
84 /// This is used for addressing modes.
85 const TargetRegisterClass *
86 PPCRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
88 // Note that PPCInstrInfo::FoldImmediate also directly uses this Kind value
89 // when it checks for ZERO folding.
92 return &PPC::G8RC_NOX0RegClass;
93 return &PPC::GPRC_NOR0RegClass;
97 return &PPC::G8RCRegClass;
98 return &PPC::GPRCRegClass;
102 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
103 const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>();
104 if (MF->getFunction()->getCallingConv() == CallingConv::AnyReg) {
105 if (Subtarget.hasVSX())
106 return CSR_64_AllRegs_VSX_SaveList;
107 if (Subtarget.hasAltivec())
108 return CSR_64_AllRegs_Altivec_SaveList;
109 return CSR_64_AllRegs_SaveList;
112 if (Subtarget.isDarwinABI())
114 ? (Subtarget.hasAltivec() ? CSR_Darwin64_Altivec_SaveList
115 : CSR_Darwin64_SaveList)
116 : (Subtarget.hasAltivec() ? CSR_Darwin32_Altivec_SaveList
117 : CSR_Darwin32_SaveList);
119 // On PPC64, we might need to save r2 (but only if it is not reserved).
120 bool SaveR2 = MF->getRegInfo().isAllocatable(PPC::X2);
123 ? (Subtarget.hasAltivec()
124 ? (SaveR2 ? CSR_SVR464_R2_Altivec_SaveList
125 : CSR_SVR464_Altivec_SaveList)
126 : (SaveR2 ? CSR_SVR464_R2_SaveList : CSR_SVR464_SaveList))
127 : (Subtarget.hasAltivec() ? CSR_SVR432_Altivec_SaveList
128 : CSR_SVR432_SaveList);
132 PPCRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
133 CallingConv::ID CC) const {
134 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
135 if (CC == CallingConv::AnyReg) {
136 if (Subtarget.hasVSX())
137 return CSR_64_AllRegs_VSX_RegMask;
138 if (Subtarget.hasAltivec())
139 return CSR_64_AllRegs_Altivec_RegMask;
140 return CSR_64_AllRegs_RegMask;
143 if (Subtarget.isDarwinABI())
144 return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_Darwin64_Altivec_RegMask
145 : CSR_Darwin64_RegMask)
146 : (Subtarget.hasAltivec() ? CSR_Darwin32_Altivec_RegMask
147 : CSR_Darwin32_RegMask);
149 return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_SVR464_Altivec_RegMask
150 : CSR_SVR464_RegMask)
151 : (Subtarget.hasAltivec() ? CSR_SVR432_Altivec_RegMask
152 : CSR_SVR432_RegMask);
156 PPCRegisterInfo::getNoPreservedMask() const {
157 return CSR_NoRegs_RegMask;
160 void PPCRegisterInfo::adjustStackMapLiveOutMask(uint32_t *Mask) const {
161 for (unsigned PseudoReg : {PPC::ZERO, PPC::ZERO8, PPC::RM})
162 Mask[PseudoReg / 32] &= ~(1u << (PseudoReg % 32));
165 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
166 BitVector Reserved(getNumRegs());
167 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
168 const PPCFrameLowering *PPCFI =
169 static_cast<const PPCFrameLowering *>(Subtarget.getFrameLowering());
171 // The ZERO register is not really a register, but the representation of r0
172 // when used in instructions that treat r0 as the constant 0.
173 Reserved.set(PPC::ZERO);
174 Reserved.set(PPC::ZERO8);
176 // The FP register is also not really a register, but is the representation
177 // of the frame pointer register used by ISD::FRAMEADDR.
178 Reserved.set(PPC::FP);
179 Reserved.set(PPC::FP8);
181 // The BP register is also not really a register, but is the representation
182 // of the base pointer register used by setjmp.
183 Reserved.set(PPC::BP);
184 Reserved.set(PPC::BP8);
186 // The counter registers must be reserved so that counter-based loops can
187 // be correctly formed (and the mtctr instructions are not DCE'd).
188 Reserved.set(PPC::CTR);
189 Reserved.set(PPC::CTR8);
191 Reserved.set(PPC::R1);
192 Reserved.set(PPC::LR);
193 Reserved.set(PPC::LR8);
194 Reserved.set(PPC::RM);
196 if (!Subtarget.isDarwinABI() || !Subtarget.hasAltivec())
197 Reserved.set(PPC::VRSAVE);
199 // The SVR4 ABI reserves r2 and r13
200 if (Subtarget.isSVR4ABI()) {
201 Reserved.set(PPC::R2); // System-reserved register
202 Reserved.set(PPC::R13); // Small Data Area pointer register
205 // On PPC64, r13 is the thread pointer. Never allocate this register.
207 Reserved.set(PPC::R13);
209 Reserved.set(PPC::X1);
210 Reserved.set(PPC::X13);
212 if (PPCFI->needsFP(MF))
213 Reserved.set(PPC::X31);
215 if (hasBasePointer(MF))
216 Reserved.set(PPC::X30);
218 // The 64-bit SVR4 ABI reserves r2 for the TOC pointer.
219 if (Subtarget.isSVR4ABI()) {
220 // We only reserve r2 if we need to use the TOC pointer. If we have no
221 // explicit uses of the TOC pointer (meaning we're a leaf function with
222 // no constant-pool loads, etc.) and we have no potential uses inside an
223 // inline asm block, then we can treat r2 has an ordinary callee-saved
225 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
226 if (FuncInfo->usesTOCBasePtr() || MF.hasInlineAsm())
227 Reserved.set(PPC::X2);
229 Reserved.reset(PPC::R2);
233 if (PPCFI->needsFP(MF))
234 Reserved.set(PPC::R31);
236 if (hasBasePointer(MF)) {
237 if (Subtarget.isSVR4ABI() && !TM.isPPC64() &&
238 TM.getRelocationModel() == Reloc::PIC_)
239 Reserved.set(PPC::R29);
241 Reserved.set(PPC::R30);
244 if (Subtarget.isSVR4ABI() && !TM.isPPC64() &&
245 TM.getRelocationModel() == Reloc::PIC_)
246 Reserved.set(PPC::R30);
248 // Reserve Altivec registers when Altivec is unavailable.
249 if (!Subtarget.hasAltivec())
250 for (TargetRegisterClass::iterator I = PPC::VRRCRegClass.begin(),
251 IE = PPC::VRRCRegClass.end(); I != IE; ++I)
257 unsigned PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
258 MachineFunction &MF) const {
259 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
260 const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
261 const unsigned DefaultSafety = 1;
263 switch (RC->getID()) {
266 case PPC::G8RC_NOX0RegClassID:
267 case PPC::GPRC_NOR0RegClassID:
268 case PPC::G8RCRegClassID:
269 case PPC::GPRCRegClassID: {
270 unsigned FP = TFI->hasFP(MF) ? 1 : 0;
271 return 32 - FP - DefaultSafety;
273 case PPC::F8RCRegClassID:
274 case PPC::F4RCRegClassID:
275 case PPC::QFRCRegClassID:
276 case PPC::QSRCRegClassID:
277 case PPC::QBRCRegClassID:
278 case PPC::VRRCRegClassID:
279 case PPC::VFRCRegClassID:
280 case PPC::VSLRCRegClassID:
281 case PPC::VSHRCRegClassID:
282 return 32 - DefaultSafety;
283 case PPC::VSRCRegClassID:
284 case PPC::VSFRCRegClassID:
285 case PPC::VSSRCRegClassID:
286 return 64 - DefaultSafety;
287 case PPC::CRRCRegClassID:
288 return 8 - DefaultSafety;
292 const TargetRegisterClass *
293 PPCRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
294 const MachineFunction &MF) const {
295 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
296 if (Subtarget.hasVSX()) {
297 // With VSX, we can inflate various sub-register classes to the full VSX
300 if (RC == &PPC::F8RCRegClass)
301 return &PPC::VSFRCRegClass;
302 else if (RC == &PPC::VRRCRegClass)
303 return &PPC::VSRCRegClass;
304 else if (RC == &PPC::F4RCRegClass && Subtarget.hasP8Vector())
305 return &PPC::VSSRCRegClass;
308 return TargetRegisterInfo::getLargestLegalSuperClass(RC, MF);
311 //===----------------------------------------------------------------------===//
312 // Stack Frame Processing methods
313 //===----------------------------------------------------------------------===//
315 /// lowerDynamicAlloc - Generate the code for allocating an object in the
316 /// current frame. The sequence of code with be in the general form
318 /// addi R0, SP, \#frameSize ; get the address of the previous frame
319 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size
320 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation
322 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const {
323 // Get the instruction.
324 MachineInstr &MI = *II;
325 // Get the instruction's basic block.
326 MachineBasicBlock &MBB = *MI.getParent();
327 // Get the basic block's function.
328 MachineFunction &MF = *MBB.getParent();
329 // Get the frame info.
330 MachineFrameInfo *MFI = MF.getFrameInfo();
331 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
332 // Get the instruction info.
333 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
334 // Determine whether 64-bit pointers are used.
335 bool LP64 = TM.isPPC64();
336 DebugLoc dl = MI.getDebugLoc();
338 // Get the maximum call stack size.
339 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
340 // Get the total frame size.
341 unsigned FrameSize = MFI->getStackSize();
343 // Get stack alignments.
344 unsigned TargetAlign = Subtarget.getFrameLowering()->getStackAlignment();
345 unsigned MaxAlign = MFI->getMaxAlignment();
346 assert((maxCallFrameSize & (MaxAlign-1)) == 0 &&
347 "Maximum call-frame size not sufficiently aligned");
349 // Determine the previous frame's address. If FrameSize can't be
350 // represented as 16 bits or we need special alignment, then we load the
351 // previous frame's address from 0(SP). Why not do an addis of the hi?
352 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
353 // Constructing the constant and adding would take 3 instructions.
354 // Fortunately, a frame greater than 32K is rare.
355 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
356 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
357 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
359 if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) {
360 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg)
364 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg)
368 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg)
373 bool KillNegSizeReg = MI.getOperand(1).isKill();
374 unsigned NegSizeReg = MI.getOperand(1).getReg();
376 // Grow the stack and update the stack pointer link, then determine the
377 // address of new allocated space.
379 if (MaxAlign > TargetAlign) {
380 unsigned UnalNegSizeReg = NegSizeReg;
381 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC);
383 // Unfortunately, there is no andi, only andi., and we can't insert that
384 // here because we might clobber cr0 while it is live.
385 BuildMI(MBB, II, dl, TII.get(PPC::LI8), NegSizeReg)
386 .addImm(~(MaxAlign-1));
388 unsigned NegSizeReg1 = NegSizeReg;
389 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC);
390 BuildMI(MBB, II, dl, TII.get(PPC::AND8), NegSizeReg)
391 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg))
392 .addReg(NegSizeReg1, RegState::Kill);
393 KillNegSizeReg = true;
396 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1)
397 .addReg(Reg, RegState::Kill)
399 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg));
400 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
402 .addImm(maxCallFrameSize);
404 if (MaxAlign > TargetAlign) {
405 unsigned UnalNegSizeReg = NegSizeReg;
406 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC);
408 // Unfortunately, there is no andi, only andi., and we can't insert that
409 // here because we might clobber cr0 while it is live.
410 BuildMI(MBB, II, dl, TII.get(PPC::LI), NegSizeReg)
411 .addImm(~(MaxAlign-1));
413 unsigned NegSizeReg1 = NegSizeReg;
414 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC);
415 BuildMI(MBB, II, dl, TII.get(PPC::AND), NegSizeReg)
416 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg))
417 .addReg(NegSizeReg1, RegState::Kill);
418 KillNegSizeReg = true;
421 BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1)
422 .addReg(Reg, RegState::Kill)
424 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg));
425 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
427 .addImm(maxCallFrameSize);
430 // Discard the DYNALLOC instruction.
434 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of
435 /// reserving a whole register (R0), we scrounge for one here. This generates
438 /// mfcr rA ; Move the conditional register into GPR rA.
439 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot.
440 /// stw rA, FI ; Store rA to the frame.
442 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II,
443 unsigned FrameIndex) const {
444 // Get the instruction.
445 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>
446 // Get the instruction's basic block.
447 MachineBasicBlock &MBB = *MI.getParent();
448 MachineFunction &MF = *MBB.getParent();
449 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
450 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
451 DebugLoc dl = MI.getDebugLoc();
453 bool LP64 = TM.isPPC64();
454 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
455 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
457 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
458 unsigned SrcReg = MI.getOperand(0).getReg();
460 // We need to store the CR in the low 4-bits of the saved value. First, issue
461 // an MFOCRF to save all of the CRBits and, if needed, kill the SrcReg.
462 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg)
463 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
465 // If the saved register wasn't CR0, shift the bits left so that they are in
467 if (SrcReg != PPC::CR0) {
469 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
471 // rlwinm rA, rA, ShiftBits, 0, 31.
472 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
473 .addReg(Reg1, RegState::Kill)
474 .addImm(getEncodingValue(SrcReg) * 4)
479 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW))
480 .addReg(Reg, RegState::Kill),
483 // Discard the pseudo instruction.
487 void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II,
488 unsigned FrameIndex) const {
489 // Get the instruction.
490 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset>
491 // Get the instruction's basic block.
492 MachineBasicBlock &MBB = *MI.getParent();
493 MachineFunction &MF = *MBB.getParent();
494 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
495 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
496 DebugLoc dl = MI.getDebugLoc();
498 bool LP64 = TM.isPPC64();
499 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
500 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
502 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
503 unsigned DestReg = MI.getOperand(0).getReg();
504 assert(MI.definesRegister(DestReg) &&
505 "RESTORE_CR does not define its destination");
507 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ),
510 // If the reloaded register isn't CR0, shift the bits right so that they are
511 // in the right CR's slot.
512 if (DestReg != PPC::CR0) {
514 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
516 unsigned ShiftBits = getEncodingValue(DestReg)*4;
517 // rlwinm r11, r11, 32-ShiftBits, 0, 31.
518 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
519 .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0)
523 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), DestReg)
524 .addReg(Reg, RegState::Kill);
526 // Discard the pseudo instruction.
530 void PPCRegisterInfo::lowerCRBitSpilling(MachineBasicBlock::iterator II,
531 unsigned FrameIndex) const {
532 // Get the instruction.
533 MachineInstr &MI = *II; // ; SPILL_CRBIT <SrcReg>, <offset>
534 // Get the instruction's basic block.
535 MachineBasicBlock &MBB = *MI.getParent();
536 MachineFunction &MF = *MBB.getParent();
537 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
538 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
539 DebugLoc dl = MI.getDebugLoc();
541 bool LP64 = TM.isPPC64();
542 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
543 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
545 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
546 unsigned SrcReg = MI.getOperand(0).getReg();
548 BuildMI(MBB, II, dl, TII.get(TargetOpcode::KILL),
549 getCRFromCRBit(SrcReg))
550 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
552 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg)
553 .addReg(getCRFromCRBit(SrcReg));
555 // If the saved register wasn't CR0LT, shift the bits left so that the bit to
556 // store is the first one. Mask all but that bit.
558 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
560 // rlwinm rA, rA, ShiftBits, 0, 0.
561 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
562 .addReg(Reg1, RegState::Kill)
563 .addImm(getEncodingValue(SrcReg))
564 .addImm(0).addImm(0);
566 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW))
567 .addReg(Reg, RegState::Kill),
570 // Discard the pseudo instruction.
574 void PPCRegisterInfo::lowerCRBitRestore(MachineBasicBlock::iterator II,
575 unsigned FrameIndex) const {
576 // Get the instruction.
577 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CRBIT <offset>
578 // Get the instruction's basic block.
579 MachineBasicBlock &MBB = *MI.getParent();
580 MachineFunction &MF = *MBB.getParent();
581 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
582 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
583 DebugLoc dl = MI.getDebugLoc();
585 bool LP64 = TM.isPPC64();
586 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
587 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
589 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
590 unsigned DestReg = MI.getOperand(0).getReg();
591 assert(MI.definesRegister(DestReg) &&
592 "RESTORE_CRBIT does not define its destination");
594 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ),
597 BuildMI(MBB, II, dl, TII.get(TargetOpcode::IMPLICIT_DEF), DestReg);
599 unsigned RegO = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
600 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), RegO)
601 .addReg(getCRFromCRBit(DestReg));
603 unsigned ShiftBits = getEncodingValue(DestReg);
604 // rlwimi r11, r10, 32-ShiftBits, ..., ...
605 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWIMI8 : PPC::RLWIMI), RegO)
606 .addReg(RegO, RegState::Kill).addReg(Reg, RegState::Kill)
607 .addImm(ShiftBits ? 32-ShiftBits : 0)
608 .addImm(ShiftBits).addImm(ShiftBits);
610 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF),
611 getCRFromCRBit(DestReg))
612 .addReg(RegO, RegState::Kill)
613 // Make sure we have a use dependency all the way through this
614 // sequence of instructions. We can't have the other bits in the CR
615 // modified in between the mfocrf and the mtocrf.
616 .addReg(getCRFromCRBit(DestReg), RegState::Implicit);
618 // Discard the pseudo instruction.
622 void PPCRegisterInfo::lowerVRSAVESpilling(MachineBasicBlock::iterator II,
623 unsigned FrameIndex) const {
624 // Get the instruction.
625 MachineInstr &MI = *II; // ; SPILL_VRSAVE <SrcReg>, <offset>
626 // Get the instruction's basic block.
627 MachineBasicBlock &MBB = *MI.getParent();
628 MachineFunction &MF = *MBB.getParent();
629 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
630 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
631 DebugLoc dl = MI.getDebugLoc();
633 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
634 unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC);
635 unsigned SrcReg = MI.getOperand(0).getReg();
637 BuildMI(MBB, II, dl, TII.get(PPC::MFVRSAVEv), Reg)
638 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
640 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::STW))
641 .addReg(Reg, RegState::Kill),
644 // Discard the pseudo instruction.
648 void PPCRegisterInfo::lowerVRSAVERestore(MachineBasicBlock::iterator II,
649 unsigned FrameIndex) const {
650 // Get the instruction.
651 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_VRSAVE <offset>
652 // Get the instruction's basic block.
653 MachineBasicBlock &MBB = *MI.getParent();
654 MachineFunction &MF = *MBB.getParent();
655 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
656 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
657 DebugLoc dl = MI.getDebugLoc();
659 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
660 unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC);
661 unsigned DestReg = MI.getOperand(0).getReg();
662 assert(MI.definesRegister(DestReg) &&
663 "RESTORE_VRSAVE does not define its destination");
665 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::LWZ),
668 BuildMI(MBB, II, dl, TII.get(PPC::MTVRSAVEv), DestReg)
669 .addReg(Reg, RegState::Kill);
671 // Discard the pseudo instruction.
676 PPCRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
677 unsigned Reg, int &FrameIdx) const {
678 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
679 // For the nonvolatile condition registers (CR2, CR3, CR4) in an SVR4
680 // ABI, return true to prevent allocating an additional frame slot.
681 // For 64-bit, the CR save area is at SP+8; the value of FrameIdx = 0
682 // is arbitrary and will be subsequently ignored. For 32-bit, we have
683 // previously created the stack slot if needed, so return its FrameIdx.
684 if (Subtarget.isSVR4ABI() && PPC::CR2 <= Reg && Reg <= PPC::CR4) {
688 const PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
689 FrameIdx = FI->getCRSpillFrameIndex();
696 // Figure out if the offset in the instruction must be a multiple of 4.
697 // This is true for instructions like "STD".
698 static bool usesIXAddr(const MachineInstr &MI) {
699 unsigned OpC = MI.getOpcode();
712 // Return the OffsetOperandNo given the FIOperandNum (and the instruction).
713 static unsigned getOffsetONFromFION(const MachineInstr &MI,
714 unsigned FIOperandNum) {
715 // Take into account whether it's an add or mem instruction
716 unsigned OffsetOperandNo = (FIOperandNum == 2) ? 1 : 2;
717 if (MI.isInlineAsm())
718 OffsetOperandNo = FIOperandNum - 1;
719 else if (MI.getOpcode() == TargetOpcode::STACKMAP ||
720 MI.getOpcode() == TargetOpcode::PATCHPOINT)
721 OffsetOperandNo = FIOperandNum + 1;
723 return OffsetOperandNo;
727 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
728 int SPAdj, unsigned FIOperandNum,
729 RegScavenger *RS) const {
730 assert(SPAdj == 0 && "Unexpected");
732 // Get the instruction.
733 MachineInstr &MI = *II;
734 // Get the instruction's basic block.
735 MachineBasicBlock &MBB = *MI.getParent();
736 // Get the basic block's function.
737 MachineFunction &MF = *MBB.getParent();
738 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
739 // Get the instruction info.
740 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
741 // Get the frame info.
742 MachineFrameInfo *MFI = MF.getFrameInfo();
743 DebugLoc dl = MI.getDebugLoc();
745 unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum);
747 // Get the frame index.
748 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
750 // Get the frame pointer save index. Users of this index are primarily
751 // DYNALLOC instructions.
752 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
753 int FPSI = FI->getFramePointerSaveIndex();
754 // Get the instruction opcode.
755 unsigned OpC = MI.getOpcode();
757 // Special case for dynamic alloca.
758 if (FPSI && FrameIndex == FPSI &&
759 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
760 lowerDynamicAlloc(II);
764 // Special case for pseudo-ops SPILL_CR and RESTORE_CR, etc.
765 if (OpC == PPC::SPILL_CR) {
766 lowerCRSpilling(II, FrameIndex);
768 } else if (OpC == PPC::RESTORE_CR) {
769 lowerCRRestore(II, FrameIndex);
771 } else if (OpC == PPC::SPILL_CRBIT) {
772 lowerCRBitSpilling(II, FrameIndex);
774 } else if (OpC == PPC::RESTORE_CRBIT) {
775 lowerCRBitRestore(II, FrameIndex);
777 } else if (OpC == PPC::SPILL_VRSAVE) {
778 lowerVRSAVESpilling(II, FrameIndex);
780 } else if (OpC == PPC::RESTORE_VRSAVE) {
781 lowerVRSAVERestore(II, FrameIndex);
785 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
786 MI.getOperand(FIOperandNum).ChangeToRegister(
787 FrameIndex < 0 ? getBaseRegister(MF) : getFrameRegister(MF), false);
789 // Figure out if the offset in the instruction is shifted right two bits.
790 bool isIXAddr = usesIXAddr(MI);
792 // If the instruction is not present in ImmToIdxMap, then it has no immediate
793 // form (and must be r+r).
794 bool noImmForm = !MI.isInlineAsm() && OpC != TargetOpcode::STACKMAP &&
795 OpC != TargetOpcode::PATCHPOINT && !ImmToIdxMap.count(OpC);
797 // Now add the frame object offset to the offset from r1.
798 int Offset = MFI->getObjectOffset(FrameIndex);
799 Offset += MI.getOperand(OffsetOperandNo).getImm();
801 // If we're not using a Frame Pointer that has been set to the value of the
802 // SP before having the stack size subtracted from it, then add the stack size
803 // to Offset to get the correct offset.
804 // Naked functions have stack size 0, although getStackSize may not reflect that
805 // because we didn't call all the pieces that compute it for naked functions.
806 if (!MF.getFunction()->hasFnAttribute(Attribute::Naked)) {
807 if (!(hasBasePointer(MF) && FrameIndex < 0))
808 Offset += MFI->getStackSize();
811 // If we can, encode the offset directly into the instruction. If this is a
812 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If
813 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits
814 // clear can be encoded. This is extremely uncommon, because normally you
815 // only "std" to a stack slot that is at least 4-byte aligned, but it can
816 // happen in invalid code.
817 assert(OpC != PPC::DBG_VALUE &&
818 "This should be handled in a target-independent way");
819 if (!noImmForm && ((isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0)) ||
820 OpC == TargetOpcode::STACKMAP ||
821 OpC == TargetOpcode::PATCHPOINT)) {
822 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
826 // The offset doesn't fit into a single register, scavenge one to build the
829 bool is64Bit = TM.isPPC64();
830 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
831 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
832 const TargetRegisterClass *RC = is64Bit ? G8RC : GPRC;
833 unsigned SRegHi = MF.getRegInfo().createVirtualRegister(RC),
834 SReg = MF.getRegInfo().createVirtualRegister(RC);
836 // Insert a set of rA with the full offset value before the ld, st, or add
837 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SRegHi)
838 .addImm(Offset >> 16);
839 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg)
840 .addReg(SRegHi, RegState::Kill)
843 // Convert into indexed form of the instruction:
845 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
846 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
847 unsigned OperandBase;
851 else if (OpC != TargetOpcode::INLINEASM) {
852 assert(ImmToIdxMap.count(OpC) &&
853 "No indexed form of load or store available!");
854 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second;
855 MI.setDesc(TII.get(NewOpcode));
858 OperandBase = OffsetOperandNo;
861 unsigned StackReg = MI.getOperand(FIOperandNum).getReg();
862 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false);
863 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true);
866 unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
867 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
868 const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
871 return TFI->hasFP(MF) ? PPC::R31 : PPC::R1;
873 return TFI->hasFP(MF) ? PPC::X31 : PPC::X1;
876 unsigned PPCRegisterInfo::getBaseRegister(const MachineFunction &MF) const {
877 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
878 if (!hasBasePointer(MF))
879 return getFrameRegister(MF);
884 if (Subtarget.isSVR4ABI() &&
885 TM.getRelocationModel() == Reloc::PIC_)
891 bool PPCRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
892 if (!EnableBasePointer)
894 if (AlwaysBasePointer)
897 // If we need to realign the stack, then the stack pointer can no longer
898 // serve as an offset into the caller's stack space. As a result, we need a
900 return needsStackRealignment(MF);
903 bool PPCRegisterInfo::canRealignStack(const MachineFunction &MF) const {
904 if (MF.getFunction()->hasFnAttribute("no-realign-stack"))
910 bool PPCRegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
911 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
912 const MachineFrameInfo *MFI = MF.getFrameInfo();
913 const Function *F = MF.getFunction();
914 unsigned StackAlign = Subtarget.getFrameLowering()->getStackAlignment();
915 bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) ||
916 F->hasFnAttribute(Attribute::StackAlignment));
918 return requiresRealignment && canRealignStack(MF);
921 /// Returns true if the instruction's frame index
922 /// reference would be better served by a base register other than FP
923 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
924 /// references it should create new base registers for.
925 bool PPCRegisterInfo::
926 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
927 assert(Offset < 0 && "Local offset must be negative");
929 // It's the load/store FI references that cause issues, as it can be difficult
930 // to materialize the offset if it won't fit in the literal field. Estimate
931 // based on the size of the local frame and some conservative assumptions
932 // about the rest of the stack frame (note, this is pre-regalloc, so
933 // we don't know everything for certain yet) whether this offset is likely
934 // to be out of range of the immediate. Return true if so.
936 // We only generate virtual base registers for loads and stores that have
937 // an r+i form. Return false for everything else.
938 unsigned OpC = MI->getOpcode();
939 if (!ImmToIdxMap.count(OpC))
942 // Don't generate a new virtual base register just to add zero to it.
943 if ((OpC == PPC::ADDI || OpC == PPC::ADDI8) &&
944 MI->getOperand(2).getImm() == 0)
947 MachineBasicBlock &MBB = *MI->getParent();
948 MachineFunction &MF = *MBB.getParent();
949 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
950 const PPCFrameLowering *PPCFI =
951 static_cast<const PPCFrameLowering *>(Subtarget.getFrameLowering());
953 PPCFI->determineFrameLayout(MF, false, true);
955 // If we likely don't need a stack frame, then we probably don't need a
956 // virtual base register either.
960 // Estimate an offset from the stack pointer.
961 // The incoming offset is relating to the SP at the start of the function,
962 // but when we access the local it'll be relative to the SP after local
963 // allocation, so adjust our SP-relative offset by that allocation size.
966 // The frame pointer will point to the end of the stack, so estimate the
967 // offset as the difference between the object offset and the FP location.
968 return !isFrameOffsetLegal(MI, getBaseRegister(MF), Offset);
971 /// Insert defining instruction(s) for BaseReg to
972 /// be a pointer to FrameIdx at the beginning of the basic block.
973 void PPCRegisterInfo::
974 materializeFrameBaseRegister(MachineBasicBlock *MBB,
975 unsigned BaseReg, int FrameIdx,
976 int64_t Offset) const {
977 unsigned ADDriOpc = TM.isPPC64() ? PPC::ADDI8 : PPC::ADDI;
979 MachineBasicBlock::iterator Ins = MBB->begin();
980 DebugLoc DL; // Defaults to "unknown"
981 if (Ins != MBB->end())
982 DL = Ins->getDebugLoc();
984 const MachineFunction &MF = *MBB->getParent();
985 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
986 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
987 const MCInstrDesc &MCID = TII.get(ADDriOpc);
988 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
989 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
991 BuildMI(*MBB, Ins, DL, MCID, BaseReg)
992 .addFrameIndex(FrameIdx).addImm(Offset);
995 void PPCRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
996 int64_t Offset) const {
997 unsigned FIOperandNum = 0;
998 while (!MI.getOperand(FIOperandNum).isFI()) {
1000 assert(FIOperandNum < MI.getNumOperands() &&
1001 "Instr doesn't have FrameIndex operand!");
1004 MI.getOperand(FIOperandNum).ChangeToRegister(BaseReg, false);
1005 unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum);
1006 Offset += MI.getOperand(OffsetOperandNo).getImm();
1007 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
1009 MachineBasicBlock &MBB = *MI.getParent();
1010 MachineFunction &MF = *MBB.getParent();
1011 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1012 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1013 const MCInstrDesc &MCID = MI.getDesc();
1014 MachineRegisterInfo &MRI = MF.getRegInfo();
1015 MRI.constrainRegClass(BaseReg,
1016 TII.getRegClass(MCID, FIOperandNum, this, MF));
1019 bool PPCRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
1021 int64_t Offset) const {
1022 unsigned FIOperandNum = 0;
1023 while (!MI->getOperand(FIOperandNum).isFI()) {
1025 assert(FIOperandNum < MI->getNumOperands() &&
1026 "Instr doesn't have FrameIndex operand!");
1029 unsigned OffsetOperandNo = getOffsetONFromFION(*MI, FIOperandNum);
1030 Offset += MI->getOperand(OffsetOperandNo).getImm();
1032 return MI->getOpcode() == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm
1033 MI->getOpcode() == TargetOpcode::STACKMAP ||
1034 MI->getOpcode() == TargetOpcode::PATCHPOINT ||
1035 (isInt<16>(Offset) && (!usesIXAddr(*MI) || (Offset & 3) == 0));