1 //===- PPC32RegisterInfo.cpp - PowerPC32 Register Information ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC32 implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "reginfo"
16 #include "PowerPCInstrBuilder.h"
17 #include "PPC32RegisterInfo.h"
18 #include "llvm/Constants.h"
19 #include "llvm/Type.h"
20 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/Target/TargetFrameInfo.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/ADT/STLExtras.h"
35 // Switch toggling compilation for AIX
36 extern cl::opt<bool> AIX;
39 PPC32RegisterInfo::PPC32RegisterInfo()
40 : PPC32GenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP) {
41 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
42 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
43 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
44 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
45 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
46 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
47 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
48 ImmToIdxMap[PPC::ADDI] = PPC::ADD;
51 static const TargetRegisterClass *getClass(unsigned SrcReg) {
52 if (PPC32::FPRCRegisterClass->contains(SrcReg))
53 return PPC32::FPRCRegisterClass;
54 assert(PPC32::GPRCRegisterClass->contains(SrcReg) && "Reg not FPR or GPR");
55 return PPC32::GPRCRegisterClass;
58 static unsigned getIdx(const TargetRegisterClass *RC) {
59 if (RC == PPC32::GPRCRegisterClass) {
60 switch (RC->getSize()) {
61 default: assert(0 && "Invalid data size!");
66 } else if (RC == PPC32::FPRCRegisterClass) {
67 switch (RC->getSize()) {
68 default: assert(0 && "Invalid data size!");
72 } else if (RC == PPC32::CRRCRegisterClass) {
73 switch (RC->getSize()) {
74 default: assert(0 && "Invalid data size!");
78 std::cerr << "Invalid register class to getIdx()!\n";
83 PPC32RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
84 MachineBasicBlock::iterator MI,
85 unsigned SrcReg, int FrameIdx) const {
86 static const unsigned Opcode[] = {
87 PPC::STB, PPC::STH, PPC::STW, PPC::STFS, PPC::STFD
89 unsigned OC = Opcode[getIdx(getClass(SrcReg))];
90 if (SrcReg == PPC::LR) {
91 BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11).addReg(PPC::LR);
92 addFrameReference(BuildMI(MBB, MI, OC, 3).addReg(PPC::R11),FrameIdx);
93 } else if (PPC32::CRRCRegisterClass == getClass(SrcReg)) {
94 BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R11);
95 addFrameReference(BuildMI(MBB, MI, OC, 3).addReg(PPC::R11),FrameIdx);
97 addFrameReference(BuildMI(MBB, MI, OC, 3).addReg(SrcReg),FrameIdx);
102 PPC32RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
103 MachineBasicBlock::iterator MI,
104 unsigned DestReg, int FrameIdx) const{
105 static const unsigned Opcode[] = {
106 PPC::LBZ, PPC::LHZ, PPC::LWZ, PPC::LFS, PPC::LFD
108 unsigned OC = Opcode[getIdx(getClass(DestReg))];
109 if (DestReg == PPC::LR) {
110 addFrameReference(BuildMI(MBB, MI, OC, 2, PPC::R11), FrameIdx);
111 BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11);
112 } else if (PPC32::CRRCRegisterClass == getClass(DestReg)) {
113 addFrameReference(BuildMI(MBB, MI, OC, 2, PPC::R11), FrameIdx);
114 BuildMI(MBB, MI, PPC::MTCRF, 1, DestReg).addReg(PPC::R11);
116 addFrameReference(BuildMI(MBB, MI, OC, 2, DestReg), FrameIdx);
120 void PPC32RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
121 MachineBasicBlock::iterator MI,
122 unsigned DestReg, unsigned SrcReg,
123 const TargetRegisterClass *RC) const {
126 if (RC == PPC32::GPRCRegisterClass) {
127 BuildMI(MBB, MI, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
128 } else if (RC == PPC32::FPRCRegisterClass) {
129 BuildMI(MBB, MI, PPC::FMR, 1, DestReg).addReg(SrcReg);
130 } else if (RC == PPC32::CRRCRegisterClass) {
131 BuildMI(MBB, MI, PPC::MCRF, 1, DestReg).addReg(SrcReg);
133 std::cerr << "Attempt to copy register that is not GPR or FPR";
138 //===----------------------------------------------------------------------===//
139 // Stack Frame Processing methods
140 //===----------------------------------------------------------------------===//
142 // hasFP - Return true if the specified function should have a dedicated frame
143 // pointer register. This is true if the function has variable sized allocas or
144 // if frame pointer elimination is disabled.
146 static bool hasFP(MachineFunction &MF) {
147 MachineFrameInfo *MFI = MF.getFrameInfo();
148 return MFI->hasVarSizedObjects();
151 void PPC32RegisterInfo::
152 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
153 MachineBasicBlock::iterator I) const {
155 // If we have a frame pointer, convert as follows:
156 // ADJCALLSTACKDOWN -> addi, r1, r1, -amount
157 // ADJCALLSTACKUP -> addi, r1, r1, amount
158 MachineInstr *Old = I;
159 unsigned Amount = Old->getOperand(0).getImmedValue();
161 // We need to keep the stack aligned properly. To do this, we round the
162 // amount of space needed for the outgoing arguments up to the next
163 // alignment boundary.
164 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
165 Amount = (Amount+Align-1)/Align*Align;
167 // Replace the pseudo instruction with a new instruction...
168 if (Old->getOpcode() == PPC::ADJCALLSTACKDOWN) {
169 MBB.insert(I, BuildMI(PPC::ADDI, 2, PPC::R1).addReg(PPC::R1)
172 assert(Old->getOpcode() == PPC::ADJCALLSTACKUP);
173 MBB.insert(I, BuildMI(PPC::ADDI, 2, PPC::R1).addReg(PPC::R1)
182 PPC32RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
184 MachineInstr &MI = *II;
185 MachineBasicBlock &MBB = *MI.getParent();
186 MachineFunction &MF = *MBB.getParent();
188 while (!MI.getOperand(i).isFrameIndex()) {
190 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
193 int FrameIndex = MI.getOperand(i).getFrameIndex();
195 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
196 MI.SetMachineOperandReg(i, hasFP(MF) ? PPC::R31 : PPC::R1);
198 // Take into account whether it's an add or mem instruction
199 unsigned OffIdx = (i == 2) ? 1 : 2;
201 // Now add the frame object offset to the offset from r1.
202 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
203 MI.getOperand(OffIdx).getImmedValue();
205 // If we're not using a Frame Pointer that has been set to the value of the
206 // SP before having the stack size subtracted from it, then add the stack size
207 // to Offset to get the correct offset.
208 Offset += MF.getFrameInfo()->getStackSize();
210 if (Offset > 32767 || Offset < -32768) {
211 // Insert a set of r0 with the full offset value before the ld, st, or add
212 MachineBasicBlock *MBB = MI.getParent();
213 MBB->insert(II, BuildMI(PPC::LIS, 1, PPC::R0).addSImm(Offset >> 16));
214 MBB->insert(II, BuildMI(PPC::ORI, 2, PPC::R0).addReg(PPC::R0)
216 // convert into indexed form of the instruction
217 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
218 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
219 unsigned NewOpcode = const_cast<std::map<unsigned, unsigned>& >(ImmToIdxMap)[MI.getOpcode()];
220 assert(NewOpcode && "No indexed form of load or store available!");
221 MI.setOpcode(NewOpcode);
222 MI.SetMachineOperandReg(1, MI.getOperand(i).getReg());
223 MI.SetMachineOperandReg(2, PPC::R0);
225 MI.SetMachineOperandConst(OffIdx,MachineOperand::MO_SignExtendedImmed,Offset);
230 void PPC32RegisterInfo::emitPrologue(MachineFunction &MF) const {
231 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
232 MachineBasicBlock::iterator MBBI = MBB.begin();
233 MachineFrameInfo *MFI = MF.getFrameInfo();
236 // Get the number of bytes to allocate from the FrameInfo
237 unsigned NumBytes = MFI->getStackSize();
239 // If we have calls, we cannot use the red zone to store callee save registers
240 // and we must set up a stack frame, so calculate the necessary size here.
241 if (MFI->hasCalls()) {
242 // We reserve argument space for call sites in the function immediately on
243 // entry to the current function. This eliminates the need for add/sub
244 // brackets around call sites.
245 NumBytes += MFI->getMaxCallFrameSize();
248 // Do we need to allocate space on the stack?
249 if (NumBytes == 0) return;
251 // Add the size of R1 to NumBytes size for the store of R1 to the bottom
252 // of the stack and round the size to a multiple of the alignment.
253 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
254 unsigned GPRSize = getSpillSize(PPC::R1)/8;
255 unsigned Size = hasFP(MF) ? GPRSize + GPRSize : GPRSize;
256 NumBytes = (NumBytes+Size+Align-1)/Align*Align;
258 // Update frame info to pretend that this is part of the stack...
259 MFI->setStackSize(NumBytes);
261 // adjust stack pointer: r1 -= numbytes
262 if (NumBytes <= 32768) {
263 MI=BuildMI(PPC::STWU,3).addReg(PPC::R1).addSImm(-NumBytes).addReg(PPC::R1);
264 MBB.insert(MBBI, MI);
266 int NegNumbytes = -NumBytes;
267 MI = BuildMI(PPC::LIS, 1, PPC::R0).addSImm(NegNumbytes >> 16);
268 MBB.insert(MBBI, MI);
269 MI = BuildMI(PPC::ORI, 2, PPC::R0).addReg(PPC::R0)
270 .addImm(NegNumbytes & 0xFFFF);
271 MBB.insert(MBBI, MI);
272 MI = BuildMI(PPC::STWUX, 3).addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
273 MBB.insert(MBBI, MI);
277 MI = BuildMI(PPC::STW, 3).addReg(PPC::R31).addSImm(GPRSize).addReg(PPC::R1);
278 MBB.insert(MBBI, MI);
279 MI = BuildMI(PPC::OR, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1);
280 MBB.insert(MBBI, MI);
284 void PPC32RegisterInfo::emitEpilogue(MachineFunction &MF,
285 MachineBasicBlock &MBB) const {
286 const MachineFrameInfo *MFI = MF.getFrameInfo();
287 MachineBasicBlock::iterator MBBI = prior(MBB.end());
289 assert(MBBI->getOpcode() == PPC::BLR &&
290 "Can only insert epilog into returning blocks");
292 // Get the number of bytes allocated from the FrameInfo...
293 unsigned NumBytes = MFI->getStackSize();
294 unsigned GPRSize = getSpillSize(PPC::R31)/8;
298 MI = BuildMI(PPC::LWZ, 2, PPC::R31).addSImm(GPRSize).addReg(PPC::R31);
299 MBB.insert(MBBI, MI);
301 MI = BuildMI(PPC::LWZ, 2, PPC::R1).addSImm(0).addReg(PPC::R1);
302 MBB.insert(MBBI, MI);
306 #include "PPC32GenRegisterInfo.inc"
308 const TargetRegisterClass*
309 PPC32RegisterInfo::getRegClassForType(const Type* Ty) const {
310 switch (Ty->getTypeID()) {
311 default: assert(0 && "Invalid type to getClass!");
313 case Type::ULongTyID: assert(0 && "Long values can't fit in registers!");
315 case Type::SByteTyID:
316 case Type::UByteTyID:
317 case Type::ShortTyID:
318 case Type::UShortTyID:
321 case Type::PointerTyID: return &GPRCInstance;
323 case Type::FloatTyID:
324 case Type::DoubleTyID: return &FPRCInstance;