1 //===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetRegisterInfo
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "reginfo"
16 #include "PPCRegisterInfo.h"
18 #include "PPCFrameLowering.h"
19 #include "PPCInstrBuilder.h"
20 #include "PPCMachineFunctionInfo.h"
21 #include "PPCSubtarget.h"
22 #include "llvm/ADT/BitVector.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineModuleInfo.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/RegisterScavenging.h"
30 #include "llvm/CodeGen/ValueTypes.h"
31 #include "llvm/IR/CallingConv.h"
32 #include "llvm/IR/Constants.h"
33 #include "llvm/IR/Function.h"
34 #include "llvm/IR/Type.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/ErrorHandling.h"
38 #include "llvm/Support/MathExtras.h"
39 #include "llvm/Support/raw_ostream.h"
40 #include "llvm/Target/TargetFrameLowering.h"
41 #include "llvm/Target/TargetInstrInfo.h"
42 #include "llvm/Target/TargetMachine.h"
43 #include "llvm/Target/TargetOptions.h"
46 #define GET_REGINFO_TARGET_DESC
47 #include "PPCGenRegisterInfo.inc"
51 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST,
52 const TargetInstrInfo &tii)
53 : PPCGenRegisterInfo(ST.isPPC64() ? PPC::LR8 : PPC::LR,
55 ST.isPPC64() ? 0 : 1),
56 Subtarget(ST), TII(tii) {
57 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
58 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
59 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
60 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
61 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
62 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
63 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
64 ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
67 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8;
68 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8;
69 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8;
70 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX;
71 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8;
74 /// getPointerRegClass - Return the register class to use to hold pointers.
75 /// This is used for addressing modes.
76 const TargetRegisterClass *
77 PPCRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
79 // Note that PPCInstrInfo::FoldImmediate also directly uses this Kind value
80 // when it checks for ZERO folding.
82 if (Subtarget.isPPC64())
83 return &PPC::G8RC_NOX0RegClass;
84 return &PPC::GPRC_NOR0RegClass;
87 if (Subtarget.isPPC64())
88 return &PPC::G8RCRegClass;
89 return &PPC::GPRCRegClass;
93 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
94 if (Subtarget.isDarwinABI())
95 return Subtarget.isPPC64() ? CSR_Darwin64_SaveList :
96 CSR_Darwin32_SaveList;
98 return Subtarget.isPPC64() ? CSR_SVR464_SaveList : CSR_SVR432_SaveList;
102 PPCRegisterInfo::getCallPreservedMask(CallingConv::ID CC) const {
103 if (Subtarget.isDarwinABI())
104 return Subtarget.isPPC64() ? CSR_Darwin64_RegMask :
105 CSR_Darwin32_RegMask;
107 return Subtarget.isPPC64() ? CSR_SVR464_RegMask : CSR_SVR432_RegMask;
111 PPCRegisterInfo::getNoPreservedMask() const {
112 // The naming here is inverted: The CSR_NoRegs_Altivec has the
113 // Altivec registers masked so that they're not saved and restored around
114 // instructions with this preserved mask.
116 if (!Subtarget.hasAltivec())
117 return CSR_NoRegs_Altivec_RegMask;
119 if (Subtarget.isDarwin())
120 return CSR_NoRegs_Darwin_RegMask;
121 return CSR_NoRegs_RegMask;
124 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
125 BitVector Reserved(getNumRegs());
126 const PPCFrameLowering *PPCFI =
127 static_cast<const PPCFrameLowering*>(MF.getTarget().getFrameLowering());
129 // The ZERO register is not really a register, but the representation of r0
130 // when used in instructions that treat r0 as the constant 0.
131 Reserved.set(PPC::ZERO);
132 Reserved.set(PPC::ZERO8);
134 // The FP register is also not really a register, but is the representation
135 // of the frame pointer register used by ISD::FRAMEADDR.
136 Reserved.set(PPC::FP);
137 Reserved.set(PPC::FP8);
139 // The counter registers must be reserved so that counter-based loops can
140 // be correctly formed (and the mtctr instructions are not DCE'd).
141 Reserved.set(PPC::CTR);
142 Reserved.set(PPC::CTR8);
144 Reserved.set(PPC::R1);
145 Reserved.set(PPC::LR);
146 Reserved.set(PPC::LR8);
147 Reserved.set(PPC::RM);
149 // The SVR4 ABI reserves r2 and r13
150 if (Subtarget.isSVR4ABI()) {
151 Reserved.set(PPC::R2); // System-reserved register
152 Reserved.set(PPC::R13); // Small Data Area pointer register
155 // On PPC64, r13 is the thread pointer. Never allocate this register.
156 if (Subtarget.isPPC64()) {
157 Reserved.set(PPC::R13);
159 Reserved.set(PPC::X1);
160 Reserved.set(PPC::X13);
162 if (PPCFI->needsFP(MF))
163 Reserved.set(PPC::X31);
165 // The 64-bit SVR4 ABI reserves r2 for the TOC pointer.
166 if (Subtarget.isSVR4ABI()) {
167 Reserved.set(PPC::X2);
171 if (PPCFI->needsFP(MF))
172 Reserved.set(PPC::R31);
178 PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
179 MachineFunction &MF) const {
180 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
181 const unsigned DefaultSafety = 1;
183 switch (RC->getID()) {
186 case PPC::G8RC_NOX0RegClassID:
187 case PPC::GPRC_NOR0RegClassID:
188 case PPC::G8RCRegClassID:
189 case PPC::GPRCRegClassID: {
190 unsigned FP = TFI->hasFP(MF) ? 1 : 0;
191 return 32 - FP - DefaultSafety;
193 case PPC::F8RCRegClassID:
194 case PPC::F4RCRegClassID:
195 case PPC::VRRCRegClassID:
196 return 32 - DefaultSafety;
197 case PPC::CRRCRegClassID:
198 return 8 - DefaultSafety;
202 //===----------------------------------------------------------------------===//
203 // Stack Frame Processing methods
204 //===----------------------------------------------------------------------===//
206 /// lowerDynamicAlloc - Generate the code for allocating an object in the
207 /// current frame. The sequence of code with be in the general form
209 /// addi R0, SP, \#frameSize ; get the address of the previous frame
210 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size
211 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation
213 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const {
214 // Get the instruction.
215 MachineInstr &MI = *II;
216 // Get the instruction's basic block.
217 MachineBasicBlock &MBB = *MI.getParent();
218 // Get the basic block's function.
219 MachineFunction &MF = *MBB.getParent();
220 // Get the frame info.
221 MachineFrameInfo *MFI = MF.getFrameInfo();
222 // Determine whether 64-bit pointers are used.
223 bool LP64 = Subtarget.isPPC64();
224 DebugLoc dl = MI.getDebugLoc();
226 // Get the maximum call stack size.
227 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
228 // Get the total frame size.
229 unsigned FrameSize = MFI->getStackSize();
231 // Get stack alignments.
232 unsigned TargetAlign = MF.getTarget().getFrameLowering()->getStackAlignment();
233 unsigned MaxAlign = MFI->getMaxAlignment();
234 if (MaxAlign > TargetAlign)
235 report_fatal_error("Dynamic alloca with large aligns not supported");
237 // Determine the previous frame's address. If FrameSize can't be
238 // represented as 16 bits or we need special alignment, then we load the
239 // previous frame's address from 0(SP). Why not do an addis of the hi?
240 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
241 // Constructing the constant and adding would take 3 instructions.
242 // Fortunately, a frame greater than 32K is rare.
243 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
244 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
245 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
247 if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) {
248 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg)
252 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg)
256 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg)
261 // Grow the stack and update the stack pointer link, then determine the
262 // address of new allocated space.
264 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1)
265 .addReg(Reg, RegState::Kill)
267 .addReg(MI.getOperand(1).getReg());
268 if (!MI.getOperand(1).isKill())
269 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
271 .addImm(maxCallFrameSize);
273 // Implicitly kill the register.
274 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
276 .addImm(maxCallFrameSize)
277 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill);
279 BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1)
280 .addReg(Reg, RegState::Kill)
282 .addReg(MI.getOperand(1).getReg());
284 if (!MI.getOperand(1).isKill())
285 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
287 .addImm(maxCallFrameSize);
289 // Implicitly kill the register.
290 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
292 .addImm(maxCallFrameSize)
293 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill);
296 // Discard the DYNALLOC instruction.
300 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of
301 /// reserving a whole register (R0), we scrounge for one here. This generates
304 /// mfcr rA ; Move the conditional register into GPR rA.
305 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot.
306 /// stw rA, FI ; Store rA to the frame.
308 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II,
309 unsigned FrameIndex) const {
310 // Get the instruction.
311 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>
312 // Get the instruction's basic block.
313 MachineBasicBlock &MBB = *MI.getParent();
314 MachineFunction &MF = *MBB.getParent();
315 DebugLoc dl = MI.getDebugLoc();
317 bool LP64 = Subtarget.isPPC64();
318 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
319 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
321 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
322 unsigned SrcReg = MI.getOperand(0).getReg();
324 // We need to store the CR in the low 4-bits of the saved value. First, issue
325 // an MFCRpsued to save all of the CRBits and, if needed, kill the SrcReg.
326 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFCR8pseud : PPC::MFCRpseud), Reg)
327 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
329 // If the saved register wasn't CR0, shift the bits left so that they are in
331 if (SrcReg != PPC::CR0) {
333 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
335 // rlwinm rA, rA, ShiftBits, 0, 31.
336 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
337 .addReg(Reg1, RegState::Kill)
338 .addImm(getEncodingValue(SrcReg) * 4)
343 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW))
344 .addReg(Reg, RegState::Kill),
347 // Discard the pseudo instruction.
351 void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II,
352 unsigned FrameIndex) const {
353 // Get the instruction.
354 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset>
355 // Get the instruction's basic block.
356 MachineBasicBlock &MBB = *MI.getParent();
357 MachineFunction &MF = *MBB.getParent();
358 DebugLoc dl = MI.getDebugLoc();
360 bool LP64 = Subtarget.isPPC64();
361 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
362 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
364 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
365 unsigned DestReg = MI.getOperand(0).getReg();
366 assert(MI.definesRegister(DestReg) &&
367 "RESTORE_CR does not define its destination");
369 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ),
372 // If the reloaded register isn't CR0, shift the bits right so that they are
373 // in the right CR's slot.
374 if (DestReg != PPC::CR0) {
376 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
378 unsigned ShiftBits = getEncodingValue(DestReg)*4;
379 // rlwinm r11, r11, 32-ShiftBits, 0, 31.
380 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
381 .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0)
385 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTCRF8 : PPC::MTCRF), DestReg)
386 .addReg(Reg, RegState::Kill);
388 // Discard the pseudo instruction.
392 void PPCRegisterInfo::lowerVRSAVESpilling(MachineBasicBlock::iterator II,
393 unsigned FrameIndex) const {
394 // Get the instruction.
395 MachineInstr &MI = *II; // ; SPILL_VRSAVE <SrcReg>, <offset>
396 // Get the instruction's basic block.
397 MachineBasicBlock &MBB = *MI.getParent();
398 MachineFunction &MF = *MBB.getParent();
399 DebugLoc dl = MI.getDebugLoc();
401 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
402 unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC);
403 unsigned SrcReg = MI.getOperand(0).getReg();
405 BuildMI(MBB, II, dl, TII.get(PPC::MFVRSAVEv), Reg)
406 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
408 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::STW))
409 .addReg(Reg, RegState::Kill),
412 // Discard the pseudo instruction.
416 void PPCRegisterInfo::lowerVRSAVERestore(MachineBasicBlock::iterator II,
417 unsigned FrameIndex) const {
418 // Get the instruction.
419 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_VRSAVE <offset>
420 // Get the instruction's basic block.
421 MachineBasicBlock &MBB = *MI.getParent();
422 MachineFunction &MF = *MBB.getParent();
423 DebugLoc dl = MI.getDebugLoc();
425 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
426 unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC);
427 unsigned DestReg = MI.getOperand(0).getReg();
428 assert(MI.definesRegister(DestReg) &&
429 "RESTORE_VRSAVE does not define its destination");
431 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::LWZ),
434 BuildMI(MBB, II, dl, TII.get(PPC::MTVRSAVEv), DestReg)
435 .addReg(Reg, RegState::Kill);
437 // Discard the pseudo instruction.
442 PPCRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
443 unsigned Reg, int &FrameIdx) const {
445 // For the nonvolatile condition registers (CR2, CR3, CR4) in an SVR4
446 // ABI, return true to prevent allocating an additional frame slot.
447 // For 64-bit, the CR save area is at SP+8; the value of FrameIdx = 0
448 // is arbitrary and will be subsequently ignored. For 32-bit, we have
449 // previously created the stack slot if needed, so return its FrameIdx.
450 if (Subtarget.isSVR4ABI() && PPC::CR2 <= Reg && Reg <= PPC::CR4) {
451 if (Subtarget.isPPC64())
454 const PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
455 FrameIdx = FI->getCRSpillFrameIndex();
462 // Figure out if the offset in the instruction is shifted right two bits. This
463 // is true for instructions like "STD", which the machine implicitly adds two
465 static bool usesIXAddr(const MachineInstr &MI) {
466 unsigned OpC = MI.getOpcode();
478 // Return the OffsetOperandNo given the FIOperandNum (and the instruction).
479 static unsigned getOffsetONFromFION(const MachineInstr &MI,
480 unsigned FIOperandNum) {
481 // Take into account whether it's an add or mem instruction
482 unsigned OffsetOperandNo = (FIOperandNum == 2) ? 1 : 2;
483 if (MI.isInlineAsm())
484 OffsetOperandNo = FIOperandNum-1;
486 return OffsetOperandNo;
490 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
491 int SPAdj, unsigned FIOperandNum,
492 RegScavenger *RS) const {
493 assert(SPAdj == 0 && "Unexpected");
495 // Get the instruction.
496 MachineInstr &MI = *II;
497 // Get the instruction's basic block.
498 MachineBasicBlock &MBB = *MI.getParent();
499 // Get the basic block's function.
500 MachineFunction &MF = *MBB.getParent();
501 // Get the frame info.
502 MachineFrameInfo *MFI = MF.getFrameInfo();
503 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
504 DebugLoc dl = MI.getDebugLoc();
506 unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum);
508 // Get the frame index.
509 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
511 // Get the frame pointer save index. Users of this index are primarily
512 // DYNALLOC instructions.
513 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
514 int FPSI = FI->getFramePointerSaveIndex();
515 // Get the instruction opcode.
516 unsigned OpC = MI.getOpcode();
518 // Special case for dynamic alloca.
519 if (FPSI && FrameIndex == FPSI &&
520 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
521 lowerDynamicAlloc(II);
525 // Special case for pseudo-ops SPILL_CR and RESTORE_CR, etc.
526 if (OpC == PPC::SPILL_CR) {
527 lowerCRSpilling(II, FrameIndex);
529 } else if (OpC == PPC::RESTORE_CR) {
530 lowerCRRestore(II, FrameIndex);
532 } else if (OpC == PPC::SPILL_VRSAVE) {
533 lowerVRSAVESpilling(II, FrameIndex);
535 } else if (OpC == PPC::RESTORE_VRSAVE) {
536 lowerVRSAVERestore(II, FrameIndex);
540 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
542 bool is64Bit = Subtarget.isPPC64();
543 MI.getOperand(FIOperandNum).ChangeToRegister(TFI->hasFP(MF) ?
544 (is64Bit ? PPC::X31 : PPC::R31) :
545 (is64Bit ? PPC::X1 : PPC::R1),
548 // Figure out if the offset in the instruction is shifted right two bits.
549 bool isIXAddr = usesIXAddr(MI);
551 // If the instruction is not present in ImmToIdxMap, then it has no immediate
552 // form (and must be r+r).
553 bool noImmForm = !MI.isInlineAsm() && !ImmToIdxMap.count(OpC);
555 // Now add the frame object offset to the offset from r1.
556 int Offset = MFI->getObjectOffset(FrameIndex);
558 Offset += MI.getOperand(OffsetOperandNo).getImm();
560 Offset += MI.getOperand(OffsetOperandNo).getImm() << 2;
562 // If we're not using a Frame Pointer that has been set to the value of the
563 // SP before having the stack size subtracted from it, then add the stack size
564 // to Offset to get the correct offset.
565 // Naked functions have stack size 0, although getStackSize may not reflect that
566 // because we didn't call all the pieces that compute it for naked functions.
567 if (!MF.getFunction()->getAttributes().
568 hasAttribute(AttributeSet::FunctionIndex, Attribute::Naked))
569 Offset += MFI->getStackSize();
571 // If we can, encode the offset directly into the instruction. If this is a
572 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If
573 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits
574 // clear can be encoded. This is extremely uncommon, because normally you
575 // only "std" to a stack slot that is at least 4-byte aligned, but it can
576 // happen in invalid code.
577 if (OpC == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm
579 isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0))) {
581 Offset >>= 2; // The actual encoded value has the low two bits zero.
582 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
586 // The offset doesn't fit into a single register, scavenge one to build the
589 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
590 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
591 const TargetRegisterClass *RC = is64Bit ? G8RC : GPRC;
592 unsigned SRegHi = MF.getRegInfo().createVirtualRegister(RC),
593 SReg = MF.getRegInfo().createVirtualRegister(RC);
595 // Insert a set of rA with the full offset value before the ld, st, or add
596 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SRegHi)
597 .addImm(Offset >> 16);
598 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg)
599 .addReg(SRegHi, RegState::Kill)
602 // Convert into indexed form of the instruction:
604 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
605 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
606 unsigned OperandBase;
610 else if (OpC != TargetOpcode::INLINEASM) {
611 assert(ImmToIdxMap.count(OpC) &&
612 "No indexed form of load or store available!");
613 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second;
614 MI.setDesc(TII.get(NewOpcode));
617 OperandBase = OffsetOperandNo;
620 unsigned StackReg = MI.getOperand(FIOperandNum).getReg();
621 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false);
622 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true);
625 unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
626 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
628 if (!Subtarget.isPPC64())
629 return TFI->hasFP(MF) ? PPC::R31 : PPC::R1;
631 return TFI->hasFP(MF) ? PPC::X31 : PPC::X1;
634 unsigned PPCRegisterInfo::getEHExceptionRegister() const {
635 return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3;
638 unsigned PPCRegisterInfo::getEHHandlerRegister() const {
639 return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4;
642 /// Returns true if the instruction's frame index
643 /// reference would be better served by a base register other than FP
644 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
645 /// references it should create new base registers for.
646 bool PPCRegisterInfo::
647 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
648 assert(Offset < 0 && "Local offset must be negative");
650 unsigned FIOperandNum = 0;
651 while (!MI->getOperand(FIOperandNum).isFI()) {
653 assert(FIOperandNum < MI->getNumOperands() &&
654 "Instr doesn't have FrameIndex operand!");
657 unsigned OffsetOperandNo = getOffsetONFromFION(*MI, FIOperandNum);
659 if (!usesIXAddr(*MI))
660 Offset += MI->getOperand(OffsetOperandNo).getImm();
662 Offset += MI->getOperand(OffsetOperandNo).getImm() << 2;
664 // It's the load/store FI references that cause issues, as it can be difficult
665 // to materialize the offset if it won't fit in the literal field. Estimate
666 // based on the size of the local frame and some conservative assumptions
667 // about the rest of the stack frame (note, this is pre-regalloc, so
668 // we don't know everything for certain yet) whether this offset is likely
669 // to be out of range of the immediate. Return true if so.
671 // We only generate virtual base registers for loads and stores that have
672 // an r+i form. Return false for everything else.
673 unsigned OpC = MI->getOpcode();
674 if (!ImmToIdxMap.count(OpC))
677 // Don't generate a new virtual base register just to add zero to it.
678 if ((OpC == PPC::ADDI || OpC == PPC::ADDI8) &&
679 MI->getOperand(2).getImm() == 0)
682 MachineBasicBlock &MBB = *MI->getParent();
683 MachineFunction &MF = *MBB.getParent();
685 const PPCFrameLowering *PPCFI =
686 static_cast<const PPCFrameLowering*>(MF.getTarget().getFrameLowering());
688 PPCFI->determineFrameLayout(MF, false, true);
690 // If we likely don't need a stack frame, then we probably don't need a
691 // virtual base register either.
695 // Estimate an offset from the stack pointer.
696 // The incoming offset is relating to the SP at the start of the function,
697 // but when we access the local it'll be relative to the SP after local
698 // allocation, so adjust our SP-relative offset by that allocation size.
701 // The frame pointer will point to the end of the stack, so estimate the
702 // offset as the difference between the object offset and the FP location.
703 return !isFrameOffsetLegal(MI, Offset);
706 /// Insert defining instruction(s) for BaseReg to
707 /// be a pointer to FrameIdx at the beginning of the basic block.
708 void PPCRegisterInfo::
709 materializeFrameBaseRegister(MachineBasicBlock *MBB,
710 unsigned BaseReg, int FrameIdx,
711 int64_t Offset) const {
712 unsigned ADDriOpc = Subtarget.isPPC64() ? PPC::ADDI8 : PPC::ADDI;
714 MachineBasicBlock::iterator Ins = MBB->begin();
715 DebugLoc DL; // Defaults to "unknown"
716 if (Ins != MBB->end())
717 DL = Ins->getDebugLoc();
719 const MCInstrDesc &MCID = TII.get(ADDriOpc);
720 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
721 const MachineFunction &MF = *MBB->getParent();
722 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
724 BuildMI(*MBB, Ins, DL, MCID, BaseReg)
725 .addFrameIndex(FrameIdx).addImm(Offset);
729 PPCRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I,
730 unsigned BaseReg, int64_t Offset) const {
731 MachineInstr &MI = *I;
733 unsigned FIOperandNum = 0;
734 while (!MI.getOperand(FIOperandNum).isFI()) {
736 assert(FIOperandNum < MI.getNumOperands() &&
737 "Instr doesn't have FrameIndex operand!");
740 MI.getOperand(FIOperandNum).ChangeToRegister(BaseReg, false);
741 unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum);
743 bool isIXAddr = usesIXAddr(MI);
745 Offset += MI.getOperand(OffsetOperandNo).getImm();
747 Offset += MI.getOperand(OffsetOperandNo).getImm() << 2;
749 // Figure out if the offset in the instruction is shifted right two bits.
751 Offset >>= 2; // The actual encoded value has the low two bits zero.
753 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
756 bool PPCRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
757 int64_t Offset) const {
758 return MI->getOpcode() == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm
759 (isInt<16>(Offset) && (!usesIXAddr(*MI) || (Offset & 3) == 0));