1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "reginfo"
16 #include "PPCInstrBuilder.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "PPCRegisterInfo.h"
19 #include "PPCFrameInfo.h"
20 #include "PPCSubtarget.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Type.h"
23 #include "llvm/CodeGen/ValueTypes.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineDebugInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineLocation.h"
29 #include "llvm/CodeGen/SelectionDAGNodes.h"
30 #include "llvm/Target/TargetFrameInfo.h"
31 #include "llvm/Target/TargetInstrInfo.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Target/TargetOptions.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/ADT/STLExtras.h"
42 /// getRegisterNumbering - Given the enum value for some register, e.g.
43 /// PPC::F14, return the number that it corresponds to (e.g. 14).
44 unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
47 case R0 : case X0 : case F0 : case V0 : case CR0: return 0;
48 case R1 : case X1 : case F1 : case V1 : case CR1: return 1;
49 case R2 : case X2 : case F2 : case V2 : case CR2: return 2;
50 case R3 : case X3 : case F3 : case V3 : case CR3: return 3;
51 case R4 : case X4 : case F4 : case V4 : case CR4: return 4;
52 case R5 : case X5 : case F5 : case V5 : case CR5: return 5;
53 case R6 : case X6 : case F6 : case V6 : case CR6: return 6;
54 case R7 : case X7 : case F7 : case V7 : case CR7: return 7;
55 case R8 : case X8 : case F8 : case V8 : return 8;
56 case R9 : case X9 : case F9 : case V9 : return 9;
57 case R10: case X10: case F10: case V10: return 10;
58 case R11: case X11: case F11: case V11: return 11;
59 case R12: case X12: case F12: case V12: return 12;
60 case R13: case X13: case F13: case V13: return 13;
61 case R14: case X14: case F14: case V14: return 14;
62 case R15: case X15: case F15: case V15: return 15;
63 case R16: case X16: case F16: case V16: return 16;
64 case R17: case X17: case F17: case V17: return 17;
65 case R18: case X18: case F18: case V18: return 18;
66 case R19: case X19: case F19: case V19: return 19;
67 case R20: case X20: case F20: case V20: return 20;
68 case R21: case X21: case F21: case V21: return 21;
69 case R22: case X22: case F22: case V22: return 22;
70 case R23: case X23: case F23: case V23: return 23;
71 case R24: case X24: case F24: case V24: return 24;
72 case R25: case X25: case F25: case V25: return 25;
73 case R26: case X26: case F26: case V26: return 26;
74 case R27: case X27: case F27: case V27: return 27;
75 case R28: case X28: case F28: case V28: return 28;
76 case R29: case X29: case F29: case V29: return 29;
77 case R30: case X30: case F30: case V30: return 30;
78 case R31: case X31: case F31: case V31: return 31;
80 std::cerr << "Unhandled reg in PPCRegisterInfo::getRegisterNumbering!\n";
85 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST,
86 const TargetInstrInfo &tii)
87 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
88 Subtarget(ST), TII(tii) {
89 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
90 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
91 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
92 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
93 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
94 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
95 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
96 ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
100 PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
101 MachineBasicBlock::iterator MI,
102 unsigned SrcReg, int FrameIdx,
103 const TargetRegisterClass *RC) const {
104 if (RC == PPC::GPRCRegisterClass) {
105 if (SrcReg != PPC::LR) {
106 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(SrcReg),FrameIdx);
108 // FIXME: this spills LR immediately to memory in one step. To do this,
109 // we use R11, which we know cannot be used in the prolog/epilog. This is
111 BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11);
112 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11),
115 } else if (RC == PPC::G8RCRegisterClass) {
116 if (SrcReg != PPC::LR8) {
117 addFrameReference(BuildMI(MBB, MI, PPC::STD, 3).addReg(SrcReg), FrameIdx);
119 // FIXME: this spills LR immediately to memory in one step. To do this,
120 // we use R11, which we know cannot be used in the prolog/epilog. This is
122 BuildMI(MBB, MI, PPC::MFLR8, 1, PPC::X11);
123 addFrameReference(BuildMI(MBB, MI, PPC::STD, 3).addReg(PPC::X11),
126 } else if (RC == PPC::F8RCRegisterClass) {
127 addFrameReference(BuildMI(MBB, MI, PPC::STFD, 3).addReg(SrcReg),FrameIdx);
128 } else if (RC == PPC::F4RCRegisterClass) {
129 addFrameReference(BuildMI(MBB, MI, PPC::STFS, 3).addReg(SrcReg),FrameIdx);
130 } else if (RC == PPC::CRRCRegisterClass) {
131 // FIXME: We use R0 here, because it isn't available for RA.
132 // We need to store the CR in the low 4-bits of the saved value. First,
133 // issue a MFCR to save all of the CRBits.
134 BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R0);
136 // If the saved register wasn't CR0, shift the bits left so that they are in
138 if (SrcReg != PPC::CR0) {
139 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4;
140 // rlwinm r0, r0, ShiftBits, 0, 31.
141 BuildMI(MBB, MI, PPC::RLWINM, 4, PPC::R0)
142 .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31);
145 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R0), FrameIdx);
146 } else if (RC == PPC::VRRCRegisterClass) {
147 // We don't have indexed addressing for vector loads. Emit:
149 // Dest = LVX R0, R11
151 // FIXME: We use R0 here, because it isn't available for RA.
152 addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0);
153 BuildMI(MBB, MI, PPC::STVX, 3)
154 .addReg(SrcReg).addReg(PPC::R0).addReg(PPC::R0);
156 assert(0 && "Unknown regclass!");
162 PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
163 MachineBasicBlock::iterator MI,
164 unsigned DestReg, int FrameIdx,
165 const TargetRegisterClass *RC) const {
166 if (RC == PPC::GPRCRegisterClass) {
167 if (DestReg != PPC::LR) {
168 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, DestReg), FrameIdx);
170 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx);
171 BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11);
173 } else if (RC == PPC::G8RCRegisterClass) {
174 if (DestReg != PPC::LR8) {
175 addFrameReference(BuildMI(MBB, MI, PPC::LD, 2, DestReg), FrameIdx);
177 addFrameReference(BuildMI(MBB, MI, PPC::LD, 2, PPC::R11), FrameIdx);
178 BuildMI(MBB, MI, PPC::MTLR8, 1).addReg(PPC::R11);
180 } else if (RC == PPC::F8RCRegisterClass) {
181 addFrameReference(BuildMI(MBB, MI, PPC::LFD, 2, DestReg), FrameIdx);
182 } else if (RC == PPC::F4RCRegisterClass) {
183 addFrameReference(BuildMI(MBB, MI, PPC::LFS, 2, DestReg), FrameIdx);
184 } else if (RC == PPC::CRRCRegisterClass) {
185 // FIXME: We use R0 here, because it isn't available for RA.
186 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R0), FrameIdx);
188 // If the reloaded register isn't CR0, shift the bits right so that they are
189 // in the right CR's slot.
190 if (DestReg != PPC::CR0) {
191 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4;
192 // rlwinm r11, r11, 32-ShiftBits, 0, 31.
193 BuildMI(MBB, MI, PPC::RLWINM, 4, PPC::R0)
194 .addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31);
197 BuildMI(MBB, MI, PPC::MTCRF, 1, DestReg).addReg(PPC::R0);
198 } else if (RC == PPC::VRRCRegisterClass) {
199 // We don't have indexed addressing for vector loads. Emit:
201 // Dest = LVX R0, R11
203 // FIXME: We use R0 here, because it isn't available for RA.
204 addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0);
205 BuildMI(MBB, MI, PPC::LVX, 2, DestReg).addReg(PPC::R0).addReg(PPC::R0);
207 assert(0 && "Unknown regclass!");
212 void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
213 MachineBasicBlock::iterator MI,
214 unsigned DestReg, unsigned SrcReg,
215 const TargetRegisterClass *RC) const {
216 if (RC == PPC::GPRCRegisterClass) {
217 BuildMI(MBB, MI, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
218 } else if (RC == PPC::G8RCRegisterClass) {
219 BuildMI(MBB, MI, PPC::OR8, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
220 } else if (RC == PPC::F4RCRegisterClass) {
221 BuildMI(MBB, MI, PPC::FMRS, 1, DestReg).addReg(SrcReg);
222 } else if (RC == PPC::F8RCRegisterClass) {
223 BuildMI(MBB, MI, PPC::FMRD, 1, DestReg).addReg(SrcReg);
224 } else if (RC == PPC::CRRCRegisterClass) {
225 BuildMI(MBB, MI, PPC::MCRF, 1, DestReg).addReg(SrcReg);
226 } else if (RC == PPC::VRRCRegisterClass) {
227 BuildMI(MBB, MI, PPC::VOR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
229 std::cerr << "Attempt to copy register that is not GPR or FPR";
234 const unsigned* PPCRegisterInfo::getCalleeSaveRegs() const {
235 // 32-bit Darwin calling convention.
236 static const unsigned Darwin32_CalleeSaveRegs[] = {
237 PPC::R13, PPC::R14, PPC::R15,
238 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
239 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
240 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
241 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
243 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
244 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
245 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
246 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
249 PPC::CR2, PPC::CR3, PPC::CR4,
250 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
251 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
252 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
256 // 64-bit Darwin calling convention.
257 static const unsigned Darwin64_CalleeSaveRegs[] = {
259 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
260 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
261 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
262 PPC::X28, PPC::X29, PPC::X30, PPC::X31,
264 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
265 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
266 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
267 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
270 PPC::CR2, PPC::CR3, PPC::CR4,
271 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
272 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
273 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
278 return Subtarget.isPPC64() ? Darwin64_CalleeSaveRegs :
279 Darwin32_CalleeSaveRegs;
282 const TargetRegisterClass* const*
283 PPCRegisterInfo::getCalleeSaveRegClasses() const {
284 // 32-bit Darwin calling convention.
285 static const TargetRegisterClass * const Darwin32_CalleeSaveRegClasses[] = {
286 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
287 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
288 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
289 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
290 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
292 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
293 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
294 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
295 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
296 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
298 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
300 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
301 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
302 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
304 &PPC::GPRCRegClass, 0
307 // 64-bit Darwin calling convention.
308 static const TargetRegisterClass * const Darwin64_CalleeSaveRegClasses[] = {
309 &PPC::G8RCRegClass,&PPC::G8RCRegClass,
310 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
311 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
312 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
313 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
315 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
316 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
317 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
318 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
319 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
321 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
323 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
324 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
325 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
327 &PPC::G8RCRegClass, 0
330 return Subtarget.isPPC64() ? Darwin64_CalleeSaveRegClasses :
331 Darwin32_CalleeSaveRegClasses;
334 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
335 /// copy instructions, turning them into load/store instructions.
336 MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI,
338 int FrameIndex) const {
339 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
340 // it takes more than one instruction to store it.
341 unsigned Opc = MI->getOpcode();
343 MachineInstr *NewMI = NULL;
344 if ((Opc == PPC::OR &&
345 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
346 if (OpNum == 0) { // move -> store
347 unsigned InReg = MI->getOperand(1).getReg();
348 NewMI = addFrameReference(BuildMI(TII, PPC::STW,
349 3).addReg(InReg), FrameIndex);
350 } else { // move -> load
351 unsigned OutReg = MI->getOperand(0).getReg();
352 NewMI = addFrameReference(BuildMI(TII, PPC::LWZ, 2, OutReg), FrameIndex);
354 } else if ((Opc == PPC::OR8 &&
355 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
356 if (OpNum == 0) { // move -> store
357 unsigned InReg = MI->getOperand(1).getReg();
358 NewMI = addFrameReference(BuildMI(TII, PPC::STD,
359 3).addReg(InReg), FrameIndex);
360 } else { // move -> load
361 unsigned OutReg = MI->getOperand(0).getReg();
362 NewMI = addFrameReference(BuildMI(TII, PPC::LD, 2, OutReg), FrameIndex);
364 } else if (Opc == PPC::FMRD) {
365 if (OpNum == 0) { // move -> store
366 unsigned InReg = MI->getOperand(1).getReg();
367 NewMI = addFrameReference(BuildMI(TII, PPC::STFD,
368 3).addReg(InReg), FrameIndex);
369 } else { // move -> load
370 unsigned OutReg = MI->getOperand(0).getReg();
371 NewMI = addFrameReference(BuildMI(TII, PPC::LFD, 2, OutReg), FrameIndex);
373 } else if (Opc == PPC::FMRS) {
374 if (OpNum == 0) { // move -> store
375 unsigned InReg = MI->getOperand(1).getReg();
376 NewMI = addFrameReference(BuildMI(TII, PPC::STFS,
377 3).addReg(InReg), FrameIndex);
378 } else { // move -> load
379 unsigned OutReg = MI->getOperand(0).getReg();
380 NewMI = addFrameReference(BuildMI(TII, PPC::LFS, 2, OutReg), FrameIndex);
385 NewMI->copyKillDeadInfo(MI);
389 //===----------------------------------------------------------------------===//
390 // Stack Frame Processing methods
391 //===----------------------------------------------------------------------===//
393 // needsFP - Return true if the specified function should have a dedicated frame
394 // pointer register. This is true if the function has variable sized allocas or
395 // if frame pointer elimination is disabled.
397 static bool needsFP(const MachineFunction &MF) {
398 const MachineFrameInfo *MFI = MF.getFrameInfo();
399 return NoFramePointerElim || MFI->hasVarSizedObjects();
402 // hasFP - Return true if the specified function actually has a dedicated frame
403 // pointer register. This is true if the function needs a frame pointer and has
404 // a non-zero stack size.
405 static bool hasFP(const MachineFunction &MF) {
406 const MachineFrameInfo *MFI = MF.getFrameInfo();
407 return MFI->getStackSize() && needsFP(MF);
410 void PPCRegisterInfo::
411 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
412 MachineBasicBlock::iterator I) const {
413 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
417 /// LowerDynamicAlloc - Generate the code for allocating an object in the
418 /// current frame. The sequence of code with be in the general form
420 /// addi R0, SP, #frameSize ; get the address of the previous frame
421 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size
422 /// addi Rnew, SP, #maxCalFrameSize ; get the top of the allocation
424 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const {
425 // Get the instruction.
426 MachineInstr &MI = *II;
427 // Get the instruction's basic block.
428 MachineBasicBlock &MBB = *MI.getParent();
429 // Get the basic block's function.
430 MachineFunction &MF = *MBB.getParent();
431 // Get the frame info.
432 MachineFrameInfo *MFI = MF.getFrameInfo();
433 // Determine whether 64-bit pointers are used.
434 bool LP64 = Subtarget.isPPC64();
436 // Determine the maximum call stack size. maxCallFrameSize may be
437 // less than the minimum.
438 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
439 unsigned getMinCallFrameSize =
440 PPCFrameInfo::getMinCallFrameSize(LP64);
441 maxCallFrameSize = std::max(maxCallFrameSize, getMinCallFrameSize);
442 // Get the total frame size.
443 unsigned FrameSize = MFI->getStackSize();
445 // Get stack alignments.
446 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
447 unsigned MaxAlign = MFI->getMaxAlignment();
448 assert(MaxAlign <= TargetAlign &&
449 "Dynamic alloca with large aligns not supported");
451 // Determine the previous frame's address. If FrameSize can't be
452 // represented as 16 bits or we need special alignment, then we load the
453 // previous frame's address from 0(SP). Why not do an addis of the hi?
454 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
455 // Constructing the constant and adding would take 3 instructions.
456 // Fortunately, a frame greater than 32K is rare.
457 if (MaxAlign < TargetAlign && isInt16(FrameSize)) {
458 BuildMI(MBB, II, PPC::ADDI, 2, PPC::R0)
462 BuildMI(MBB, II, PPC::LD, 2, PPC::X0)
466 BuildMI(MBB, II, PPC::LWZ, 2, PPC::R0)
471 // Grow the stack and update the stack pointer link, then
472 // determine the address of new allocated space.
474 BuildMI(MBB, II, PPC::STDUX, 3)
477 .addReg(MI.getOperand(1).getReg());
478 BuildMI(MBB, II, PPC::ADDI8, 2, MI.getOperand(0).getReg())
480 .addImm(maxCallFrameSize);
482 BuildMI(MBB, II, PPC::STWUX, 3)
485 .addReg(MI.getOperand(1).getReg());
486 BuildMI(MBB, II, PPC::ADDI, 2, MI.getOperand(0).getReg())
488 .addImm(maxCallFrameSize);
491 // Discard the DYNALLOC instruction.
496 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
497 // Get the instruction.
498 MachineInstr &MI = *II;
499 // Get the instruction's basic block.
500 MachineBasicBlock &MBB = *MI.getParent();
501 // Get the basic block's function.
502 MachineFunction &MF = *MBB.getParent();
503 // Get the frame info.
504 MachineFrameInfo *MFI = MF.getFrameInfo();
506 // Find out which operand is the frame index.
508 while (!MI.getOperand(i).isFrameIndex()) {
510 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
512 // Take into account whether it's an add or mem instruction
513 unsigned OffIdx = (i == 2) ? 1 : 2;
514 // Get the frame index.
515 int FrameIndex = MI.getOperand(i).getFrameIndex();
517 // Get the frame pointer save index. Users of this index are primarily
518 // DYNALLOC instructions.
519 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
520 int FPSI = FI->getFramePointerSaveIndex();
521 // Get the instruction opcode.
522 unsigned OpC = MI.getOpcode();
524 // Special case for dynamic alloca.
525 if (FPSI && FrameIndex == FPSI &&
526 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
527 lowerDynamicAlloc(II);
531 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
532 MI.getOperand(i).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1, false);
534 // Figure out if the offset in the instruction is shifted right two bits. This
535 // is true for instructions like "STD", which the machine implicitly adds two
537 bool isIXAddr = false;
547 // Now add the frame object offset to the offset from r1.
548 int Offset = MFI->getObjectOffset(FrameIndex);
551 Offset += MI.getOperand(OffIdx).getImmedValue();
553 Offset += MI.getOperand(OffIdx).getImmedValue() << 2;
555 // If we're not using a Frame Pointer that has been set to the value of the
556 // SP before having the stack size subtracted from it, then add the stack size
557 // to Offset to get the correct offset.
558 Offset += MFI->getStackSize();
560 if (!isInt16(Offset)) {
561 // Insert a set of r0 with the full offset value before the ld, st, or add
562 BuildMI(MBB, II, PPC::LIS, 1, PPC::R0).addImm(Offset >> 16);
563 BuildMI(MBB, II, PPC::ORI, 2, PPC::R0).addReg(PPC::R0).addImm(Offset);
565 // convert into indexed form of the instruction
566 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
567 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
568 assert(ImmToIdxMap.count(OpC) &&
569 "No indexed form of load or store available!");
570 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second;
571 MI.setOpcode(NewOpcode);
572 MI.getOperand(1).ChangeToRegister(MI.getOperand(i).getReg(), false);
573 MI.getOperand(2).ChangeToRegister(PPC::R0, false);
576 assert((Offset & 3) == 0 && "Invalid frame offset!");
577 Offset >>= 2; // The actual encoded value has the low two bits zero.
579 MI.getOperand(OffIdx).ChangeToImmediate(Offset);
583 /// VRRegNo - Map from a numbered VR register to its enum value.
585 static const unsigned short VRRegNo[] = {
586 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
587 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
588 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
589 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
592 /// RemoveVRSaveCode - We have found that this function does not need any code
593 /// to manipulate the VRSAVE register, even though it uses vector registers.
594 /// This can happen when the only registers used are known to be live in or out
595 /// of the function. Remove all of the VRSAVE related code from the function.
596 static void RemoveVRSaveCode(MachineInstr *MI) {
597 MachineBasicBlock *Entry = MI->getParent();
598 MachineFunction *MF = Entry->getParent();
600 // We know that the MTVRSAVE instruction immediately follows MI. Remove it.
601 MachineBasicBlock::iterator MBBI = MI;
603 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
604 MBBI->eraseFromParent();
606 bool RemovedAllMTVRSAVEs = true;
607 // See if we can find and remove the MTVRSAVE instruction from all of the
609 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
610 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
611 // If last instruction is a return instruction, add an epilogue
612 if (!I->empty() && TII.isReturn(I->back().getOpcode())) {
613 bool FoundIt = false;
614 for (MBBI = I->end(); MBBI != I->begin(); ) {
616 if (MBBI->getOpcode() == PPC::MTVRSAVE) {
617 MBBI->eraseFromParent(); // remove it.
622 RemovedAllMTVRSAVEs &= FoundIt;
626 // If we found and removed all MTVRSAVE instructions, remove the read of
628 if (RemovedAllMTVRSAVEs) {
630 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
632 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
633 MBBI->eraseFromParent();
636 // Finally, nuke the UPDATE_VRSAVE.
637 MI->eraseFromParent();
640 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
641 // instruction selector. Based on the vector registers that have been used,
642 // transform this into the appropriate ORI instruction.
643 static void HandleVRSaveUpdate(MachineInstr *MI, const bool *UsedRegs) {
644 unsigned UsedRegMask = 0;
645 for (unsigned i = 0; i != 32; ++i)
646 if (UsedRegs[VRRegNo[i]])
647 UsedRegMask |= 1 << (31-i);
649 // Live in and live out values already must be in the mask, so don't bother
651 MachineFunction *MF = MI->getParent()->getParent();
652 for (MachineFunction::livein_iterator I =
653 MF->livein_begin(), E = MF->livein_end(); I != E; ++I) {
654 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first);
655 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg.
656 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
658 for (MachineFunction::liveout_iterator I =
659 MF->liveout_begin(), E = MF->liveout_end(); I != E; ++I) {
660 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I);
661 if (VRRegNo[RegNo] == *I) // If this really is a vector reg.
662 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
665 unsigned SrcReg = MI->getOperand(1).getReg();
666 unsigned DstReg = MI->getOperand(0).getReg();
667 // If no registers are used, turn this into a copy.
668 if (UsedRegMask == 0) {
669 // Remove all VRSAVE code.
670 RemoveVRSaveCode(MI);
672 } else if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
673 BuildMI(*MI->getParent(), MI, PPC::ORI, 2, DstReg)
674 .addReg(SrcReg).addImm(UsedRegMask);
675 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
676 BuildMI(*MI->getParent(), MI, PPC::ORIS, 2, DstReg)
677 .addReg(SrcReg).addImm(UsedRegMask >> 16);
679 BuildMI(*MI->getParent(), MI, PPC::ORIS, 2, DstReg)
680 .addReg(SrcReg).addImm(UsedRegMask >> 16);
681 BuildMI(*MI->getParent(), MI, PPC::ORI, 2, DstReg)
682 .addReg(DstReg).addImm(UsedRegMask & 0xFFFF);
685 // Remove the old UPDATE_VRSAVE instruction.
686 MI->eraseFromParent();
689 /// determineFrameLayout - Determine the size of the frame and maximum call
691 void PPCRegisterInfo::determineFrameLayout(MachineFunction &MF) const {
692 MachineFrameInfo *MFI = MF.getFrameInfo();
694 // Get the number of bytes to allocate from the FrameInfo
695 unsigned FrameSize = MFI->getStackSize();
697 // Get the alignments provided by the target, and the maximum alignment
698 // (if any) of the fixed frame objects.
699 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
700 unsigned MaxAlign = MFI->getMaxAlignment();
701 unsigned Align = std::max(TargetAlign, MaxAlign);
702 assert(isPowerOf2_32(Align) && "Alignment is not power of 2");
703 unsigned AlignMask = Align - 1; //
705 // If we are a leaf function, and use up to 224 bytes of stack space,
706 // don't have a frame pointer, calls, or dynamic alloca then we do not need
707 // to adjust the stack pointer (we fit in the Red Zone).
708 if (FrameSize <= 224 && // Fits in red zone.
709 !MFI->hasVarSizedObjects() && // No dynamic alloca.
710 !MFI->hasCalls() && // No calls.
711 MaxAlign <= TargetAlign) { // No special alignment.
713 MFI->setStackSize(0);
717 // Get the maximum call frame size of all the calls.
718 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
720 // Maximum call frame needs to be at least big enough for linkage and 8 args.
721 unsigned minCallFrameSize =
722 PPCFrameInfo::getMinCallFrameSize(Subtarget.isPPC64());
723 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
725 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
726 // that allocations will be aligned.
727 if (MFI->hasVarSizedObjects())
728 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
730 // Update maximum call frame size.
731 MFI->setMaxCallFrameSize(maxCallFrameSize);
733 // Include call frame size in total.
734 FrameSize += maxCallFrameSize;
736 // Make sure the frame is aligned.
737 FrameSize = (FrameSize + AlignMask) & ~AlignMask;
739 // Update frame info.
740 MFI->setStackSize(FrameSize);
743 void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
744 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
745 MachineBasicBlock::iterator MBBI = MBB.begin();
746 MachineFrameInfo *MFI = MF.getFrameInfo();
747 MachineDebugInfo *DebugInfo = MFI->getMachineDebugInfo();
749 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
751 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
752 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
753 HandleVRSaveUpdate(MBBI, MF.getUsedPhysregs());
758 // Move MBBI back to the beginning of the function.
761 // Work out frame sizes.
762 determineFrameLayout(MF);
763 unsigned FrameSize = MFI->getStackSize();
765 // Skip if a leaf routine.
766 if (!FrameSize) return;
768 int NegFrameSize = -FrameSize;
770 // Do we have a frame pointer for this function?
771 bool HasFP = hasFP(MF);
773 // If there is a frame pointer, copy R31 into TOC(SP)
775 int Offset = PPCFrameInfo::getFramePointerSaveOffset(Subtarget.isPPC64());
777 if (!Subtarget.isPPC64()) {
778 BuildMI(MBB, MBBI, PPC::STW, 3)
779 .addReg(PPC::R31).addImm(Offset).addReg(PPC::R1);
781 BuildMI(MBB, MBBI, PPC::STD, 3)
782 .addReg(PPC::X31).addImm(Offset/4).addReg(PPC::X1);
786 // Get stack alignments.
787 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
788 unsigned MaxAlign = MFI->getMaxAlignment();
790 // Adjust stack pointer: r1 += NegFrameSize.
791 // If there is a preferred stack alignment, align R1 now
792 if (!Subtarget.isPPC64()) {
794 if (MaxAlign > TargetAlign) {
795 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!");
796 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!");
797 BuildMI(MBB, MBBI, PPC::RLWINM, 4, PPC::R0)
798 .addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31);
799 BuildMI(MBB, MBBI, PPC::SUBFIC,2,PPC::R0).addReg(PPC::R0)
800 .addImm(NegFrameSize);
801 BuildMI(MBB, MBBI, PPC::STWUX, 3)
802 .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
803 } else if (isInt16(NegFrameSize)) {
804 BuildMI(MBB, MBBI, PPC::STWU, 3,
805 PPC::R1).addReg(PPC::R1).addImm(NegFrameSize).addReg(PPC::R1);
807 BuildMI(MBB, MBBI, PPC::LIS, 1, PPC::R0).addImm(NegFrameSize >> 16);
808 BuildMI(MBB, MBBI, PPC::ORI, 2, PPC::R0).addReg(PPC::R0)
809 .addImm(NegFrameSize & 0xFFFF);
810 BuildMI(MBB, MBBI, PPC::STWUX, 3).addReg(PPC::R1).addReg(PPC::R1)
814 if (MaxAlign > TargetAlign) {
815 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!");
816 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!");
817 BuildMI(MBB, MBBI, PPC::RLDICL, 3, PPC::X0)
818 .addReg(PPC::X1).addImm(0).addImm(64-Log2_32(MaxAlign));
819 BuildMI(MBB, MBBI, PPC::SUBFIC8, 2, PPC::X0).addReg(PPC::X0)
820 .addImm(NegFrameSize);
821 BuildMI(MBB, MBBI, PPC::STDUX, 3)
822 .addReg(PPC::X1).addReg(PPC::X1).addReg(PPC::X0);
823 } else if (isInt16(NegFrameSize)) {
824 BuildMI(MBB, MBBI, PPC::STDU, 3, PPC::X1)
825 .addReg(PPC::X1).addImm(NegFrameSize/4).addReg(PPC::X1);
827 BuildMI(MBB, MBBI, PPC::LIS8, 1, PPC::X0).addImm(NegFrameSize >> 16);
828 BuildMI(MBB, MBBI, PPC::ORI8, 2, PPC::X0).addReg(PPC::X0)
829 .addImm(NegFrameSize & 0xFFFF);
830 BuildMI(MBB, MBBI, PPC::STDUX, 3).addReg(PPC::X1).addReg(PPC::X1)
835 if (DebugInfo && DebugInfo->hasInfo()) {
836 std::vector<MachineMove *> &Moves = DebugInfo->getFrameMoves();
837 unsigned LabelID = DebugInfo->NextLabelID();
839 // Mark effective beginning of when frame pointer becomes valid.
840 BuildMI(MBB, MBBI, PPC::DWARF_LABEL, 1).addImm(LabelID);
842 // Show update of SP.
843 MachineLocation SPDst(MachineLocation::VirtualFP);
844 MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize);
845 Moves.push_back(new MachineMove(LabelID, SPDst, SPSrc));
847 // Add callee saved registers to move list.
848 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
849 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
850 MachineLocation CSDst(MachineLocation::VirtualFP,
851 MFI->getObjectOffset(CSI[I].getFrameIdx()));
852 MachineLocation CSSrc(CSI[I].getReg());
853 Moves.push_back(new MachineMove(LabelID, CSDst, CSSrc));
857 // If there is a frame pointer, copy R1 into R31
859 if (!Subtarget.isPPC64()) {
860 BuildMI(MBB, MBBI, PPC::OR, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1);
862 BuildMI(MBB, MBBI, PPC::OR8, 2, PPC::X31).addReg(PPC::X1).addReg(PPC::X1);
867 void PPCRegisterInfo::emitEpilogue(MachineFunction &MF,
868 MachineBasicBlock &MBB) const {
869 MachineBasicBlock::iterator MBBI = prior(MBB.end());
870 assert(MBBI->getOpcode() == PPC::BLR &&
871 "Can only insert epilog into returning blocks");
873 // Get alignment info so we know how to restore r1
874 const MachineFrameInfo *MFI = MF.getFrameInfo();
875 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
876 unsigned MaxAlign = MFI->getMaxAlignment();
878 // Get the number of bytes allocated from the FrameInfo.
879 unsigned FrameSize = MFI->getStackSize();
881 if (FrameSize != 0) {
882 // The loaded (or persistent) stack pointer value is offset by the 'stwu'
883 // on entry to the function. Add this offset back now.
884 if (!Subtarget.isPPC64()) {
885 if (isInt16(FrameSize) && TargetAlign >= MaxAlign &&
886 !MFI->hasVarSizedObjects()) {
887 BuildMI(MBB, MBBI, PPC::ADDI, 2, PPC::R1)
888 .addReg(PPC::R1).addImm(FrameSize);
890 BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R1).addImm(0).addReg(PPC::R1);
893 if (isInt16(FrameSize) && TargetAlign >= MaxAlign &&
894 !MFI->hasVarSizedObjects()) {
895 BuildMI(MBB, MBBI, PPC::ADDI8, 2, PPC::X1)
896 .addReg(PPC::X1).addImm(FrameSize);
898 BuildMI(MBB, MBBI, PPC::LD, 2, PPC::X1).addImm(0).addReg(PPC::X1);
902 // If this function has a frame pointer, load the saved frame pointer from
905 int Offset = PPCFrameInfo::getFramePointerSaveOffset(Subtarget.isPPC64());
907 if (!Subtarget.isPPC64()) {
908 BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R31)
909 .addImm(Offset).addReg(PPC::R1);
911 BuildMI(MBB, MBBI, PPC::LD, 2, PPC::X31)
912 .addImm(Offset/4).addReg(PPC::X1);
919 unsigned PPCRegisterInfo::getRARegister() const {
920 return !Subtarget.isPPC64() ? PPC::LR : PPC::LR8;
924 unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const {
925 if (!Subtarget.isPPC64())
926 return hasFP(MF) ? PPC::R31 : PPC::R1;
928 return hasFP(MF) ? PPC::X31 : PPC::X1;
931 void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove *> &Moves)
933 // Initial state of the frame pointer is R1.
934 MachineLocation Dst(MachineLocation::VirtualFP);
935 MachineLocation Src(PPC::R1, 0);
936 Moves.push_back(new MachineMove(0, Dst, Src));
939 #include "PPCGenRegisterInfo.inc"