1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetRegisterInfo
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "reginfo"
17 #include "PPCInstrBuilder.h"
18 #include "PPCMachineFunctionInfo.h"
19 #include "PPCRegisterInfo.h"
20 #include "PPCFrameInfo.h"
21 #include "PPCSubtarget.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Type.h"
24 #include "llvm/CodeGen/ValueTypes.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineModuleInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineLocation.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/RegisterScavenging.h"
32 #include "llvm/CodeGen/SelectionDAGNodes.h"
33 #include "llvm/Target/TargetFrameInfo.h"
34 #include "llvm/Target/TargetInstrInfo.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
37 #include "llvm/Support/CommandLine.h"
38 #include "llvm/Support/Debug.h"
39 #include "llvm/Support/MathExtras.h"
40 #include "llvm/ADT/BitVector.h"
41 #include "llvm/ADT/STLExtras.h"
45 // FIXME (64-bit): Eventually enable by default.
46 cl::opt<bool> EnablePPCRS("enable-ppc-regscavenger",
48 cl::desc("enable PPC register scavenger"),
51 // FIXME (64-bit): Should be inlined.
53 PPCRegisterInfo::requiresRegisterScavenging(const MachineFunction &) const {
57 /// getRegisterNumbering - Given the enum value for some register, e.g.
58 /// PPC::F14, return the number that it corresponds to (e.g. 14).
59 unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
63 case R0 : case X0 : case F0 : case V0 : case CR0: case CR0LT: return 0;
64 case R1 : case X1 : case F1 : case V1 : case CR1: case CR0GT: return 1;
65 case R2 : case X2 : case F2 : case V2 : case CR2: case CR0EQ: return 2;
66 case R3 : case X3 : case F3 : case V3 : case CR3: case CR0UN: return 3;
67 case R4 : case X4 : case F4 : case V4 : case CR4: case CR1LT: return 4;
68 case R5 : case X5 : case F5 : case V5 : case CR5: case CR1GT: return 5;
69 case R6 : case X6 : case F6 : case V6 : case CR6: case CR1EQ: return 6;
70 case R7 : case X7 : case F7 : case V7 : case CR7: case CR1UN: return 7;
71 case R8 : case X8 : case F8 : case V8 : case CR2LT: return 8;
72 case R9 : case X9 : case F9 : case V9 : case CR2GT: return 9;
73 case R10: case X10: case F10: case V10: case CR2EQ: return 10;
74 case R11: case X11: case F11: case V11: case CR2UN: return 11;
75 case R12: case X12: case F12: case V12: case CR3LT: return 12;
76 case R13: case X13: case F13: case V13: case CR3GT: return 13;
77 case R14: case X14: case F14: case V14: case CR3EQ: return 14;
78 case R15: case X15: case F15: case V15: case CR3UN: return 15;
79 case R16: case X16: case F16: case V16: case CR4LT: return 16;
80 case R17: case X17: case F17: case V17: case CR4GT: return 17;
81 case R18: case X18: case F18: case V18: case CR4EQ: return 18;
82 case R19: case X19: case F19: case V19: case CR4UN: return 19;
83 case R20: case X20: case F20: case V20: case CR5LT: return 20;
84 case R21: case X21: case F21: case V21: case CR5GT: return 21;
85 case R22: case X22: case F22: case V22: case CR5EQ: return 22;
86 case R23: case X23: case F23: case V23: case CR5UN: return 23;
87 case R24: case X24: case F24: case V24: case CR6LT: return 24;
88 case R25: case X25: case F25: case V25: case CR6GT: return 25;
89 case R26: case X26: case F26: case V26: case CR6EQ: return 26;
90 case R27: case X27: case F27: case V27: case CR6UN: return 27;
91 case R28: case X28: case F28: case V28: case CR7LT: return 28;
92 case R29: case X29: case F29: case V29: case CR7GT: return 29;
93 case R30: case X30: case F30: case V30: case CR7EQ: return 30;
94 case R31: case X31: case F31: case V31: case CR7UN: return 31;
96 cerr << "Unhandled reg in PPCRegisterInfo::getRegisterNumbering!\n";
101 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST,
102 const TargetInstrInfo &tii)
103 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
104 Subtarget(ST), TII(tii) {
105 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
106 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
107 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
108 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
109 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
110 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
111 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
112 ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
115 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8;
116 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8;
117 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8;
118 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX;
119 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32;
122 void PPCRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
123 MachineBasicBlock::iterator I,
125 const MachineInstr *Orig) const {
126 MachineInstr *MI = Orig->clone();
127 MI->getOperand(0).setReg(DestReg);
132 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
133 // 32-bit Darwin calling convention.
134 static const unsigned Macho32_CalleeSavedRegs[] = {
135 PPC::R13, PPC::R14, PPC::R15,
136 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
137 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
138 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
139 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
141 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
142 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
143 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
144 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
147 PPC::CR2, PPC::CR3, PPC::CR4,
148 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
149 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
150 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
152 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
153 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
154 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
159 static const unsigned ELF32_CalleeSavedRegs[] = {
160 PPC::R13, PPC::R14, PPC::R15,
161 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
162 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
163 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
164 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
167 PPC::F10, PPC::F11, PPC::F12, PPC::F13,
168 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
169 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
170 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
171 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
174 PPC::CR2, PPC::CR3, PPC::CR4,
175 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
176 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
177 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
179 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
180 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
181 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
185 // 64-bit Darwin calling convention.
186 static const unsigned Macho64_CalleeSavedRegs[] = {
188 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
189 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
190 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
191 PPC::X28, PPC::X29, PPC::X30, PPC::X31,
193 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
194 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
195 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
196 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
199 PPC::CR2, PPC::CR3, PPC::CR4,
200 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
201 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
202 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
204 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
205 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
206 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
211 if (Subtarget.isMachoABI())
212 return Subtarget.isPPC64() ? Macho64_CalleeSavedRegs :
213 Macho32_CalleeSavedRegs;
216 return ELF32_CalleeSavedRegs;
219 const TargetRegisterClass* const*
220 PPCRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
221 // 32-bit Macho calling convention.
222 static const TargetRegisterClass * const Macho32_CalleeSavedRegClasses[] = {
223 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
224 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
225 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
226 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
227 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
229 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
230 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
231 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
232 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
233 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
235 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
237 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
238 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
239 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
241 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
242 &PPC::CRBITRCRegClass,
243 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
244 &PPC::CRBITRCRegClass,
245 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
246 &PPC::CRBITRCRegClass,
248 &PPC::GPRCRegClass, 0
251 static const TargetRegisterClass * const ELF32_CalleeSavedRegClasses[] = {
252 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
253 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
254 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
255 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
256 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
259 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
260 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
261 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
262 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
263 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
264 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
266 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
268 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
269 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
270 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
272 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
273 &PPC::CRBITRCRegClass,
274 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
275 &PPC::CRBITRCRegClass,
276 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
277 &PPC::CRBITRCRegClass,
279 &PPC::GPRCRegClass, 0
282 // 64-bit Macho calling convention.
283 static const TargetRegisterClass * const Macho64_CalleeSavedRegClasses[] = {
284 &PPC::G8RCRegClass,&PPC::G8RCRegClass,
285 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
286 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
287 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
288 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
290 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
291 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
292 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
293 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
294 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
296 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
298 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
299 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
300 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
302 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
303 &PPC::CRBITRCRegClass,
304 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
305 &PPC::CRBITRCRegClass,
306 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
307 &PPC::CRBITRCRegClass,
309 &PPC::G8RCRegClass, 0
312 if (Subtarget.isMachoABI())
313 return Subtarget.isPPC64() ? Macho64_CalleeSavedRegClasses :
314 Macho32_CalleeSavedRegClasses;
317 return ELF32_CalleeSavedRegClasses;
320 // needsFP - Return true if the specified function should have a dedicated frame
321 // pointer register. This is true if the function has variable sized allocas or
322 // if frame pointer elimination is disabled.
324 static bool needsFP(const MachineFunction &MF) {
325 const MachineFrameInfo *MFI = MF.getFrameInfo();
326 return NoFramePointerElim || MFI->hasVarSizedObjects();
329 static bool spillsCR(const MachineFunction &MF) {
330 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
331 return FuncInfo->isCRSpilled();
334 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
335 BitVector Reserved(getNumRegs());
336 Reserved.set(PPC::R0);
337 Reserved.set(PPC::R1);
338 Reserved.set(PPC::LR);
339 Reserved.set(PPC::LR8);
341 // In Linux, r2 is reserved for the OS.
342 if (!Subtarget.isDarwin())
343 Reserved.set(PPC::R2);
345 // On PPC64, r13 is the thread pointer. Never allocate this register. Note
346 // that this is over conservative, as it also prevents allocation of R31 when
347 // the FP is not needed.
348 if (Subtarget.isPPC64()) {
349 Reserved.set(PPC::R13);
350 Reserved.set(PPC::R31);
353 Reserved.set(PPC::R0); // FIXME (64-bit): Remove
355 Reserved.set(PPC::X0);
356 Reserved.set(PPC::X1);
357 Reserved.set(PPC::X13);
358 Reserved.set(PPC::X31);
362 Reserved.set(PPC::R31);
367 //===----------------------------------------------------------------------===//
368 // Stack Frame Processing methods
369 //===----------------------------------------------------------------------===//
371 // hasFP - Return true if the specified function actually has a dedicated frame
372 // pointer register. This is true if the function needs a frame pointer and has
373 // a non-zero stack size.
374 bool PPCRegisterInfo::hasFP(const MachineFunction &MF) const {
375 const MachineFrameInfo *MFI = MF.getFrameInfo();
376 return MFI->getStackSize() && needsFP(MF);
379 /// MustSaveLR - Return true if this function requires that we save the LR
380 /// register onto the stack in the prolog and restore it in the epilog of the
382 static bool MustSaveLR(const MachineFunction &MF) {
383 const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>();
385 // We need an save/restore of LR if there is any use/def of LR explicitly, or
386 // if there is some use of the LR stack slot (e.g. for builtin_return_address.
387 return MFI->usesLR() || MFI->isLRStoreRequired() ||
388 // FIXME: Anything that has a call should clobber the LR register,
389 // isn't this redundant??
390 MF.getFrameInfo()->hasCalls();
393 void PPCRegisterInfo::
394 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
395 MachineBasicBlock::iterator I) const {
396 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
400 /// findScratchRegister - Find a 'free' PPC register. Try for a call-clobbered
401 /// register first and then a spilled callee-saved register if that fails.
403 unsigned findScratchRegister(MachineBasicBlock::iterator II, RegScavenger *RS,
404 const TargetRegisterClass *RC, int SPAdj) {
405 assert(RS && "Register scavenging must be on");
406 unsigned Reg = RS->FindUnusedReg(RC, true);
407 // FIXME: move ARM callee-saved reg scan to target independent code, then
408 // search for already spilled CS register here.
410 Reg = RS->scavengeRegister(RC, II, SPAdj);
414 /// lowerDynamicAlloc - Generate the code for allocating an object in the
415 /// current frame. The sequence of code with be in the general form
417 /// addi R0, SP, #frameSize ; get the address of the previous frame
418 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size
419 /// addi Rnew, SP, #maxCalFrameSize ; get the top of the allocation
421 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II,
422 int SPAdj, RegScavenger *RS) const {
423 // Get the instruction.
424 MachineInstr &MI = *II;
425 // Get the instruction's basic block.
426 MachineBasicBlock &MBB = *MI.getParent();
427 // Get the basic block's function.
428 MachineFunction &MF = *MBB.getParent();
429 // Get the frame info.
430 MachineFrameInfo *MFI = MF.getFrameInfo();
431 // Determine whether 64-bit pointers are used.
432 bool LP64 = Subtarget.isPPC64();
434 // Get the maximum call stack size.
435 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
436 // Get the total frame size.
437 unsigned FrameSize = MFI->getStackSize();
439 // Get stack alignments.
440 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
441 unsigned MaxAlign = MFI->getMaxAlignment();
442 assert(MaxAlign <= TargetAlign &&
443 "Dynamic alloca with large aligns not supported");
445 // Determine the previous frame's address. If FrameSize can't be
446 // represented as 16 bits or we need special alignment, then we load the
447 // previous frame's address from 0(SP). Why not do an addis of the hi?
448 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
449 // Constructing the constant and adding would take 3 instructions.
450 // Fortunately, a frame greater than 32K is rare.
451 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
452 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
453 const TargetRegisterClass *RC = LP64 ? G8RC : GPRC;
455 // FIXME (64-bit): Use "findScratchRegister"
458 Reg = findScratchRegister(II, RS, RC, SPAdj);
462 if (MaxAlign < TargetAlign && isInt16(FrameSize)) {
463 BuildMI(MBB, II, TII.get(PPC::ADDI), Reg)
467 if (EnablePPCRS) // FIXME (64-bit): Use "true" version.
468 BuildMI(MBB, II, TII.get(PPC::LD), Reg)
472 BuildMI(MBB, II, TII.get(PPC::LD), PPC::X0)
476 BuildMI(MBB, II, TII.get(PPC::LWZ), Reg)
481 // Grow the stack and update the stack pointer link, then determine the
482 // address of new allocated space.
484 if (EnablePPCRS) // FIXME (64-bit): Use "true" version.
485 BuildMI(MBB, II, TII.get(PPC::STDUX))
486 .addReg(Reg, false, false, true)
488 .addReg(MI.getOperand(1).getReg());
490 BuildMI(MBB, II, TII.get(PPC::STDUX))
491 .addReg(PPC::X0, false, false, true)
493 .addReg(MI.getOperand(1).getReg());
495 if (!MI.getOperand(1).isKill())
496 BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
498 .addImm(maxCallFrameSize);
500 // Implicitly kill the register.
501 BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
503 .addImm(maxCallFrameSize)
504 .addReg(MI.getOperand(1).getReg(), false, true, true);
506 BuildMI(MBB, II, TII.get(PPC::STWUX))
507 .addReg(Reg, false, false, true)
509 .addReg(MI.getOperand(1).getReg());
511 if (!MI.getOperand(1).isKill())
512 BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
514 .addImm(maxCallFrameSize);
516 // Implicitly kill the register.
517 BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
519 .addImm(maxCallFrameSize)
520 .addReg(MI.getOperand(1).getReg(), false, true, true);
523 // Discard the DYNALLOC instruction.
527 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of
528 /// reserving a whole register (R0), we scrounge for one here. This generates
531 /// mfcr rA ; Move the conditional register into GPR rA.
532 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot.
533 /// stw rA, FI ; Store rA to the frame.
535 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II,
536 unsigned FrameIndex, int SPAdj,
537 RegScavenger *RS) const {
538 // Get the instruction.
539 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>, <FI>
540 // Get the instruction's basic block.
541 MachineBasicBlock &MBB = *MI.getParent();
543 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
544 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
545 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC;
546 unsigned Reg = findScratchRegister(II, RS, RC, SPAdj);
548 // We need to store the CR in the low 4-bits of the saved value. First, issue
549 // an MFCR to save all of the CRBits. Add an implicit kill of the CR.
550 if (!MI.getOperand(0).isKill())
551 BuildMI(MBB, II, TII.get(PPC::MFCR), Reg);
553 // Implicitly kill the CR register.
554 BuildMI(MBB, II, TII.get(PPC::MFCR), Reg)
555 .addReg(MI.getOperand(0).getReg(), false, true, true);
557 // If the saved register wasn't CR0, shift the bits left so that they are in
559 unsigned SrcReg = MI.getOperand(0).getReg();
560 if (SrcReg != PPC::CR0)
561 // rlwinm rA, rA, ShiftBits, 0, 31.
562 BuildMI(MBB, II, TII.get(PPC::RLWINM), Reg)
563 .addReg(Reg, false, false, true)
564 .addImm(PPCRegisterInfo::getRegisterNumbering(SrcReg) * 4)
568 addFrameReference(BuildMI(MBB, II, TII.get(PPC::STW))
569 .addReg(Reg, false, false, MI.getOperand(1).getImm()),
572 // Discard the pseudo instruction.
576 void PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
577 int SPAdj, RegScavenger *RS) const {
578 assert(SPAdj == 0 && "Unexpected");
580 // Get the instruction.
581 MachineInstr &MI = *II;
582 // Get the instruction's basic block.
583 MachineBasicBlock &MBB = *MI.getParent();
584 // Get the basic block's function.
585 MachineFunction &MF = *MBB.getParent();
586 // Get the frame info.
587 MachineFrameInfo *MFI = MF.getFrameInfo();
589 // Find out which operand is the frame index.
590 unsigned FIOperandNo = 0;
591 while (!MI.getOperand(FIOperandNo).isFrameIndex()) {
593 assert(FIOperandNo != MI.getNumOperands() &&
594 "Instr doesn't have FrameIndex operand!");
596 // Take into account whether it's an add or mem instruction
597 unsigned OffsetOperandNo = (FIOperandNo == 2) ? 1 : 2;
598 if (MI.getOpcode() == TargetInstrInfo::INLINEASM)
599 OffsetOperandNo = FIOperandNo-1;
601 // Get the frame index.
602 int FrameIndex = MI.getOperand(FIOperandNo).getIndex();
604 // Get the frame pointer save index. Users of this index are primarily
605 // DYNALLOC instructions.
606 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
607 int FPSI = FI->getFramePointerSaveIndex();
608 // Get the instruction opcode.
609 unsigned OpC = MI.getOpcode();
611 // Special case for dynamic alloca.
612 if (FPSI && FrameIndex == FPSI &&
613 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
614 lowerDynamicAlloc(II, SPAdj, RS);
618 // Special case for pseudo-op SPILL_CR.
619 if (EnablePPCRS) // FIXME (64-bit): Enable by default
620 if (OpC == PPC::SPILL_CR) {
621 lowerCRSpilling(II, FrameIndex, SPAdj, RS);
625 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
626 MI.getOperand(FIOperandNo).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1,
629 // Figure out if the offset in the instruction is shifted right two bits. This
630 // is true for instructions like "STD", which the machine implicitly adds two
632 bool isIXAddr = false;
642 // Now add the frame object offset to the offset from r1.
643 int Offset = MFI->getObjectOffset(FrameIndex);
645 Offset += MI.getOperand(OffsetOperandNo).getImm();
647 Offset += MI.getOperand(OffsetOperandNo).getImm() << 2;
649 // If we're not using a Frame Pointer that has been set to the value of the
650 // SP before having the stack size subtracted from it, then add the stack size
651 // to Offset to get the correct offset.
652 Offset += MFI->getStackSize();
654 // If we can, encode the offset directly into the instruction. If this is a
655 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If
656 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits
657 // clear can be encoded. This is extremely uncommon, because normally you
658 // only "std" to a stack slot that is at least 4-byte aligned, but it can
659 // happen in invalid code.
660 if (isInt16(Offset) && (!isIXAddr || (Offset & 3) == 0)) {
662 Offset >>= 2; // The actual encoded value has the low two bits zero.
663 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
667 // The offset doesn't fit into a single register, scavenge one to build the
669 // FIXME: figure out what SPAdj is doing here.
671 // FIXME (64-bit): Use "findScratchRegister".
674 SReg = findScratchRegister(II, RS, &PPC::GPRCRegClass, SPAdj);
678 // Insert a set of rA with the full offset value before the ld, st, or add
679 BuildMI(MBB, II, TII.get(PPC::LIS), SReg)
680 .addImm(Offset >> 16);
681 BuildMI(MBB, II, TII.get(PPC::ORI), SReg)
682 .addReg(SReg, false, false, true)
685 // Convert into indexed form of the instruction:
687 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
688 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
689 unsigned OperandBase;
691 if (OpC != TargetInstrInfo::INLINEASM) {
692 assert(ImmToIdxMap.count(OpC) &&
693 "No indexed form of load or store available!");
694 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second;
695 MI.setDesc(TII.get(NewOpcode));
698 OperandBase = OffsetOperandNo;
701 unsigned StackReg = MI.getOperand(FIOperandNo).getReg();
702 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false);
703 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false);
706 /// VRRegNo - Map from a numbered VR register to its enum value.
708 static const unsigned short VRRegNo[] = {
709 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
710 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
711 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
712 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
715 /// RemoveVRSaveCode - We have found that this function does not need any code
716 /// to manipulate the VRSAVE register, even though it uses vector registers.
717 /// This can happen when the only registers used are known to be live in or out
718 /// of the function. Remove all of the VRSAVE related code from the function.
719 static void RemoveVRSaveCode(MachineInstr *MI) {
720 MachineBasicBlock *Entry = MI->getParent();
721 MachineFunction *MF = Entry->getParent();
723 // We know that the MTVRSAVE instruction immediately follows MI. Remove it.
724 MachineBasicBlock::iterator MBBI = MI;
726 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
727 MBBI->eraseFromParent();
729 bool RemovedAllMTVRSAVEs = true;
730 // See if we can find and remove the MTVRSAVE instruction from all of the
732 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
733 // If last instruction is a return instruction, add an epilogue
734 if (!I->empty() && I->back().getDesc().isReturn()) {
735 bool FoundIt = false;
736 for (MBBI = I->end(); MBBI != I->begin(); ) {
738 if (MBBI->getOpcode() == PPC::MTVRSAVE) {
739 MBBI->eraseFromParent(); // remove it.
744 RemovedAllMTVRSAVEs &= FoundIt;
748 // If we found and removed all MTVRSAVE instructions, remove the read of
750 if (RemovedAllMTVRSAVEs) {
752 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
754 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
755 MBBI->eraseFromParent();
758 // Finally, nuke the UPDATE_VRSAVE.
759 MI->eraseFromParent();
762 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
763 // instruction selector. Based on the vector registers that have been used,
764 // transform this into the appropriate ORI instruction.
765 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) {
766 MachineFunction *MF = MI->getParent()->getParent();
768 unsigned UsedRegMask = 0;
769 for (unsigned i = 0; i != 32; ++i)
770 if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i]))
771 UsedRegMask |= 1 << (31-i);
773 // Live in and live out values already must be in the mask, so don't bother
775 for (MachineRegisterInfo::livein_iterator
776 I = MF->getRegInfo().livein_begin(),
777 E = MF->getRegInfo().livein_end(); I != E; ++I) {
778 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first);
779 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg.
780 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
782 for (MachineRegisterInfo::liveout_iterator
783 I = MF->getRegInfo().liveout_begin(),
784 E = MF->getRegInfo().liveout_end(); I != E; ++I) {
785 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I);
786 if (VRRegNo[RegNo] == *I) // If this really is a vector reg.
787 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
790 // If no registers are used, turn this into a copy.
791 if (UsedRegMask == 0) {
792 // Remove all VRSAVE code.
793 RemoveVRSaveCode(MI);
797 unsigned SrcReg = MI->getOperand(1).getReg();
798 unsigned DstReg = MI->getOperand(0).getReg();
800 if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
801 if (DstReg != SrcReg)
802 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg)
804 .addImm(UsedRegMask);
806 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg)
807 .addReg(SrcReg, false, false, true)
808 .addImm(UsedRegMask);
809 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
810 if (DstReg != SrcReg)
811 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
813 .addImm(UsedRegMask >> 16);
815 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
816 .addReg(SrcReg, false, false, true)
817 .addImm(UsedRegMask >> 16);
819 if (DstReg != SrcReg)
820 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
822 .addImm(UsedRegMask >> 16);
824 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
825 .addReg(SrcReg, false, false, true)
826 .addImm(UsedRegMask >> 16);
828 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg)
829 .addReg(DstReg, false, false, true)
830 .addImm(UsedRegMask & 0xFFFF);
833 // Remove the old UPDATE_VRSAVE instruction.
834 MI->eraseFromParent();
837 /// determineFrameLayout - Determine the size of the frame and maximum call
839 void PPCRegisterInfo::determineFrameLayout(MachineFunction &MF) const {
840 MachineFrameInfo *MFI = MF.getFrameInfo();
842 // Get the number of bytes to allocate from the FrameInfo
843 unsigned FrameSize = MFI->getStackSize();
845 // Get the alignments provided by the target, and the maximum alignment
846 // (if any) of the fixed frame objects.
847 unsigned MaxAlign = MFI->getMaxAlignment();
848 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
849 unsigned AlignMask = TargetAlign - 1; //
851 // If we are a leaf function, and use up to 224 bytes of stack space,
852 // don't have a frame pointer, calls, or dynamic alloca then we do not need
853 // to adjust the stack pointer (we fit in the Red Zone).
854 if (FrameSize <= 224 && // Fits in red zone.
855 !MFI->hasVarSizedObjects() && // No dynamic alloca.
856 !MFI->hasCalls() && // No calls.
857 MaxAlign <= TargetAlign) { // No special alignment.
859 MFI->setStackSize(0);
863 // Get the maximum call frame size of all the calls.
864 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
866 // Maximum call frame needs to be at least big enough for linkage and 8 args.
867 unsigned minCallFrameSize =
868 PPCFrameInfo::getMinCallFrameSize(Subtarget.isPPC64(),
869 Subtarget.isMachoABI());
870 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
872 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
873 // that allocations will be aligned.
874 if (MFI->hasVarSizedObjects())
875 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
877 // Update maximum call frame size.
878 MFI->setMaxCallFrameSize(maxCallFrameSize);
880 // Include call frame size in total.
881 FrameSize += maxCallFrameSize;
883 // Make sure the frame is aligned.
884 FrameSize = (FrameSize + AlignMask) & ~AlignMask;
886 // Update frame info.
887 MFI->setStackSize(FrameSize);
891 PPCRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
892 RegScavenger *RS) const {
893 // Save and clear the LR state.
894 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
895 unsigned LR = getRARegister();
896 FI->setUsesLR(MF.getRegInfo().isPhysRegUsed(LR));
897 MF.getRegInfo().setPhysRegUnused(LR);
899 // Save R31 if necessary
900 int FPSI = FI->getFramePointerSaveIndex();
901 bool IsPPC64 = Subtarget.isPPC64();
902 bool IsELF32_ABI = Subtarget.isELF32_ABI();
903 bool IsMachoABI = Subtarget.isMachoABI();
904 MachineFrameInfo *MFI = MF.getFrameInfo();
906 // If the frame pointer save index hasn't been defined yet.
907 if (!FPSI && (NoFramePointerElim || MFI->hasVarSizedObjects()) &&
909 // Find out what the fix offset of the frame pointer save area.
910 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64,
912 // Allocate the frame index for frame pointer save area.
913 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset);
915 FI->setFramePointerSaveIndex(FPSI);
918 // Reserve a slot closest to SP or frame pointer if we have a dynalloc or
919 // a large stack, which will require scavenging a register to materialize a
921 // FIXME: this doesn't actually check stack size, so is a bit pessimistic
922 // FIXME: doesn't detect whether or not we need to spill vXX, which requires
925 if (EnablePPCRS) // FIXME (64-bit): Enable.
926 if (needsFP(MF) || spillsCR(MF)) {
927 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
928 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
929 const TargetRegisterClass *RC = IsPPC64 ? G8RC : GPRC;
930 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
931 RC->getAlignment()));
936 PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
937 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
938 MachineBasicBlock::iterator MBBI = MBB.begin();
939 MachineFrameInfo *MFI = MF.getFrameInfo();
940 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
942 // Prepare for frame info.
943 unsigned FrameLabelId = 0;
945 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
947 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
948 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
949 HandleVRSaveUpdate(MBBI, TII);
954 // Move MBBI back to the beginning of the function.
957 // Work out frame sizes.
958 determineFrameLayout(MF);
959 unsigned FrameSize = MFI->getStackSize();
961 int NegFrameSize = -FrameSize;
963 // Get processor type.
964 bool IsPPC64 = Subtarget.isPPC64();
965 // Get operating system
966 bool IsMachoABI = Subtarget.isMachoABI();
967 // Check if the link register (LR) has been used.
968 bool UsesLR = MustSaveLR(MF);
969 // Do we have a frame pointer for this function?
970 bool HasFP = hasFP(MF) && FrameSize;
972 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI);
973 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI);
977 BuildMI(MBB, MBBI, TII.get(PPC::MFLR8), PPC::X0);
980 BuildMI(MBB, MBBI, TII.get(PPC::STD))
986 BuildMI(MBB, MBBI, TII.get(PPC::STD))
988 .addImm(LROffset / 4)
992 BuildMI(MBB, MBBI, TII.get(PPC::MFLR), PPC::R0);
995 BuildMI(MBB, MBBI, TII.get(PPC::STW))
1001 BuildMI(MBB, MBBI, TII.get(PPC::STW))
1007 // Skip if a leaf routine.
1008 if (!FrameSize) return;
1010 // Get stack alignments.
1011 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
1012 unsigned MaxAlign = MFI->getMaxAlignment();
1014 if (MMI && MMI->needsFrameInfo()) {
1015 // Mark effective beginning of when frame pointer becomes valid.
1016 FrameLabelId = MMI->NextLabelID();
1017 BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(FrameLabelId).addImm(0);
1020 // Adjust stack pointer: r1 += NegFrameSize.
1021 // If there is a preferred stack alignment, align R1 now
1024 if (MaxAlign > TargetAlign) {
1025 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!");
1026 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!");
1028 BuildMI(MBB, MBBI, TII.get(PPC::RLWINM), PPC::R0)
1031 .addImm(32 - Log2_32(MaxAlign))
1033 BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC) ,PPC::R0)
1034 .addReg(PPC::R0, false, false, true)
1035 .addImm(NegFrameSize);
1036 BuildMI(MBB, MBBI, TII.get(PPC::STWUX))
1040 } else if (isInt16(NegFrameSize)) {
1041 BuildMI(MBB, MBBI, TII.get(PPC::STWU), PPC::R1)
1043 .addImm(NegFrameSize)
1046 BuildMI(MBB, MBBI, TII.get(PPC::LIS), PPC::R0)
1047 .addImm(NegFrameSize >> 16);
1048 BuildMI(MBB, MBBI, TII.get(PPC::ORI), PPC::R0)
1049 .addReg(PPC::R0, false, false, true)
1050 .addImm(NegFrameSize & 0xFFFF);
1051 BuildMI(MBB, MBBI, TII.get(PPC::STWUX))
1057 if (MaxAlign > TargetAlign) {
1058 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!");
1059 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!");
1061 BuildMI(MBB, MBBI, TII.get(PPC::RLDICL), PPC::X0)
1064 .addImm(64 - Log2_32(MaxAlign));
1065 BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC8), PPC::X0)
1067 .addImm(NegFrameSize);
1068 BuildMI(MBB, MBBI, TII.get(PPC::STDUX))
1072 } else if (isInt16(NegFrameSize)) {
1073 BuildMI(MBB, MBBI, TII.get(PPC::STDU), PPC::X1)
1075 .addImm(NegFrameSize / 4)
1078 BuildMI(MBB, MBBI, TII.get(PPC::LIS8), PPC::X0)
1079 .addImm(NegFrameSize >> 16);
1080 BuildMI(MBB, MBBI, TII.get(PPC::ORI8), PPC::X0)
1081 .addReg(PPC::X0, false, false, true)
1082 .addImm(NegFrameSize & 0xFFFF);
1083 BuildMI(MBB, MBBI, TII.get(PPC::STDUX))
1090 if (MMI && MMI->needsFrameInfo()) {
1091 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
1094 // Show update of SP.
1095 MachineLocation SPDst(MachineLocation::VirtualFP);
1096 MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize);
1097 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
1099 MachineLocation SP(IsPPC64 ? PPC::X31 : PPC::R31);
1100 Moves.push_back(MachineMove(FrameLabelId, SP, SP));
1104 MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset);
1105 MachineLocation FPSrc(IsPPC64 ? PPC::X31 : PPC::R31);
1106 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc));
1109 // Add callee saved registers to move list.
1110 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1111 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
1112 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
1113 unsigned Reg = CSI[I].getReg();
1114 if (Reg == PPC::LR || Reg == PPC::LR8) continue;
1115 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
1116 MachineLocation CSSrc(Reg);
1117 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
1120 MachineLocation LRDst(MachineLocation::VirtualFP, LROffset);
1121 MachineLocation LRSrc(IsPPC64 ? PPC::LR8 : PPC::LR);
1122 Moves.push_back(MachineMove(FrameLabelId, LRDst, LRSrc));
1124 // Mark effective beginning of when frame pointer is ready.
1125 unsigned ReadyLabelId = MMI->NextLabelID();
1126 BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(ReadyLabelId).addImm(0);
1128 MachineLocation FPDst(HasFP ? (IsPPC64 ? PPC::X31 : PPC::R31) :
1129 (IsPPC64 ? PPC::X1 : PPC::R1));
1130 MachineLocation FPSrc(MachineLocation::VirtualFP);
1131 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
1134 // If there is a frame pointer, copy R1 into R31
1137 BuildMI(MBB, MBBI, TII.get(PPC::OR), PPC::R31)
1141 BuildMI(MBB, MBBI, TII.get(PPC::OR8), PPC::X31)
1148 void PPCRegisterInfo::emitEpilogue(MachineFunction &MF,
1149 MachineBasicBlock &MBB) const {
1150 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1151 assert(MBBI->getOpcode() == PPC::BLR &&
1152 "Can only insert epilog into returning blocks");
1154 // Get alignment info so we know how to restore r1
1155 const MachineFrameInfo *MFI = MF.getFrameInfo();
1156 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
1157 unsigned MaxAlign = MFI->getMaxAlignment();
1159 // Get the number of bytes allocated from the FrameInfo.
1160 unsigned FrameSize = MFI->getStackSize();
1162 // Get processor type.
1163 bool IsPPC64 = Subtarget.isPPC64();
1164 // Get operating system
1165 bool IsMachoABI = Subtarget.isMachoABI();
1166 // Check if the link register (LR) has been used.
1167 bool UsesLR = MustSaveLR(MF);
1168 // Do we have a frame pointer for this function?
1169 bool HasFP = hasFP(MF) && FrameSize;
1171 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI);
1172 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI);
1175 // The loaded (or persistent) stack pointer value is offset by the 'stwu'
1176 // on entry to the function. Add this offset back now.
1177 if (!Subtarget.isPPC64()) {
1178 if (isInt16(FrameSize) && TargetAlign >= MaxAlign &&
1179 !MFI->hasVarSizedObjects()) {
1180 BuildMI(MBB, MBBI, TII.get(PPC::ADDI), PPC::R1)
1181 .addReg(PPC::R1).addImm(FrameSize);
1183 BuildMI(MBB, MBBI, TII.get(PPC::LWZ),PPC::R1).addImm(0).addReg(PPC::R1);
1186 if (isInt16(FrameSize) && TargetAlign >= MaxAlign &&
1187 !MFI->hasVarSizedObjects()) {
1188 BuildMI(MBB, MBBI, TII.get(PPC::ADDI8), PPC::X1)
1189 .addReg(PPC::X1).addImm(FrameSize);
1191 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X1).addImm(0).addReg(PPC::X1);
1198 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X0)
1199 .addImm(LROffset/4).addReg(PPC::X1);
1202 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X31)
1203 .addImm(FPOffset/4).addReg(PPC::X1);
1206 BuildMI(MBB, MBBI, TII.get(PPC::MTLR8)).addReg(PPC::X0);
1209 BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R0)
1210 .addImm(LROffset).addReg(PPC::R1);
1213 BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R31)
1214 .addImm(FPOffset).addReg(PPC::R1);
1217 BuildMI(MBB, MBBI, TII.get(PPC::MTLR)).addReg(PPC::R0);
1221 unsigned PPCRegisterInfo::getRARegister() const {
1222 return !Subtarget.isPPC64() ? PPC::LR : PPC::LR8;
1225 unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const {
1226 if (!Subtarget.isPPC64())
1227 return hasFP(MF) ? PPC::R31 : PPC::R1;
1229 return hasFP(MF) ? PPC::X31 : PPC::X1;
1232 void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
1234 // Initial state of the frame pointer is R1.
1235 MachineLocation Dst(MachineLocation::VirtualFP);
1236 MachineLocation Src(PPC::R1, 0);
1237 Moves.push_back(MachineMove(0, Dst, Src));
1240 unsigned PPCRegisterInfo::getEHExceptionRegister() const {
1241 return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3;
1244 unsigned PPCRegisterInfo::getEHHandlerRegister() const {
1245 return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4;
1248 int PPCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
1249 // FIXME: Most probably dwarf numbers differs for Linux and Darwin
1250 return PPCGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
1253 #include "PPCGenRegisterInfo.inc"