1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetRegisterInfo
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "reginfo"
17 #include "PPCInstrBuilder.h"
18 #include "PPCMachineFunctionInfo.h"
19 #include "PPCRegisterInfo.h"
20 #include "PPCFrameInfo.h"
21 #include "PPCSubtarget.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineModuleInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineLocation.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/RegisterScavenging.h"
33 #include "llvm/CodeGen/SelectionDAGNodes.h"
34 #include "llvm/Target/TargetFrameInfo.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/Support/CommandLine.h"
39 #include "llvm/Support/Debug.h"
40 #include "llvm/Support/MathExtras.h"
41 #include "llvm/ADT/BitVector.h"
42 #include "llvm/ADT/STLExtras.h"
46 // FIXME This disables some code that aligns the stack to a boundary
47 // bigger than the default (16 bytes on Darwin) when there is a stack local
48 // of greater alignment. This does not currently work, because the delta
49 // between old and new stack pointers is added to offsets that reference
50 // incoming parameters after the prolog is generated, and the code that
51 // does that doesn't handle a variable delta. You don't want to do that
52 // anyway; a better approach is to reserve another register that retains
53 // to the incoming stack pointer, and reference parameters relative to that.
56 // FIXME (64-bit): Eventually enable by default.
57 cl::opt<bool> EnablePPC32RS("enable-ppc32-regscavenger",
59 cl::desc("Enable PPC32 register scavenger"),
61 cl::opt<bool> EnablePPC64RS("enable-ppc64-regscavenger",
63 cl::desc("Enable PPC64 register scavenger"),
65 #define EnableRegisterScavenging \
66 ((EnablePPC32RS && !Subtarget.isPPC64()) || \
67 (EnablePPC64RS && Subtarget.isPPC64()))
69 // FIXME (64-bit): Should be inlined.
71 PPCRegisterInfo::requiresRegisterScavenging(const MachineFunction &) const {
72 return EnableRegisterScavenging;
75 /// getRegisterNumbering - Given the enum value for some register, e.g.
76 /// PPC::F14, return the number that it corresponds to (e.g. 14).
77 unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
81 case R0 : case X0 : case F0 : case V0 : case CR0: case CR0LT: return 0;
82 case R1 : case X1 : case F1 : case V1 : case CR1: case CR0GT: return 1;
83 case R2 : case X2 : case F2 : case V2 : case CR2: case CR0EQ: return 2;
84 case R3 : case X3 : case F3 : case V3 : case CR3: case CR0UN: return 3;
85 case R4 : case X4 : case F4 : case V4 : case CR4: case CR1LT: return 4;
86 case R5 : case X5 : case F5 : case V5 : case CR5: case CR1GT: return 5;
87 case R6 : case X6 : case F6 : case V6 : case CR6: case CR1EQ: return 6;
88 case R7 : case X7 : case F7 : case V7 : case CR7: case CR1UN: return 7;
89 case R8 : case X8 : case F8 : case V8 : case CR2LT: return 8;
90 case R9 : case X9 : case F9 : case V9 : case CR2GT: return 9;
91 case R10: case X10: case F10: case V10: case CR2EQ: return 10;
92 case R11: case X11: case F11: case V11: case CR2UN: return 11;
93 case R12: case X12: case F12: case V12: case CR3LT: return 12;
94 case R13: case X13: case F13: case V13: case CR3GT: return 13;
95 case R14: case X14: case F14: case V14: case CR3EQ: return 14;
96 case R15: case X15: case F15: case V15: case CR3UN: return 15;
97 case R16: case X16: case F16: case V16: case CR4LT: return 16;
98 case R17: case X17: case F17: case V17: case CR4GT: return 17;
99 case R18: case X18: case F18: case V18: case CR4EQ: return 18;
100 case R19: case X19: case F19: case V19: case CR4UN: return 19;
101 case R20: case X20: case F20: case V20: case CR5LT: return 20;
102 case R21: case X21: case F21: case V21: case CR5GT: return 21;
103 case R22: case X22: case F22: case V22: case CR5EQ: return 22;
104 case R23: case X23: case F23: case V23: case CR5UN: return 23;
105 case R24: case X24: case F24: case V24: case CR6LT: return 24;
106 case R25: case X25: case F25: case V25: case CR6GT: return 25;
107 case R26: case X26: case F26: case V26: case CR6EQ: return 26;
108 case R27: case X27: case F27: case V27: case CR6UN: return 27;
109 case R28: case X28: case F28: case V28: case CR7LT: return 28;
110 case R29: case X29: case F29: case V29: case CR7GT: return 29;
111 case R30: case X30: case F30: case V30: case CR7EQ: return 30;
112 case R31: case X31: case F31: case V31: case CR7UN: return 31;
114 cerr << "Unhandled reg in PPCRegisterInfo::getRegisterNumbering!\n";
119 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST,
120 const TargetInstrInfo &tii)
121 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
122 Subtarget(ST), TII(tii) {
123 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
124 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
125 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
126 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
127 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
128 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
129 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
130 ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
133 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8;
134 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8;
135 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8;
136 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX;
137 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32;
141 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
142 // 32-bit Darwin calling convention.
143 static const unsigned Macho32_CalleeSavedRegs[] = {
144 PPC::R13, PPC::R14, PPC::R15,
145 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
146 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
147 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
148 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
150 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
151 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
152 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
153 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
156 PPC::CR2, PPC::CR3, PPC::CR4,
157 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
158 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
159 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
161 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
162 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
163 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
168 static const unsigned ELF32_CalleeSavedRegs[] = {
169 PPC::R13, PPC::R14, PPC::R15,
170 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
171 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
172 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
173 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
176 PPC::F10, PPC::F11, PPC::F12, PPC::F13,
177 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
178 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
179 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
180 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
183 PPC::CR2, PPC::CR3, PPC::CR4,
184 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
185 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
186 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
188 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
189 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
190 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
194 // 64-bit Darwin calling convention.
195 static const unsigned Macho64_CalleeSavedRegs[] = {
197 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
198 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
199 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
200 PPC::X28, PPC::X29, PPC::X30, PPC::X31,
202 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
203 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
204 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
205 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
208 PPC::CR2, PPC::CR3, PPC::CR4,
209 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
210 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
211 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
213 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
214 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
215 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
220 if (Subtarget.isMachoABI())
221 return Subtarget.isPPC64() ? Macho64_CalleeSavedRegs :
222 Macho32_CalleeSavedRegs;
225 return ELF32_CalleeSavedRegs;
228 const TargetRegisterClass* const*
229 PPCRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
230 // 32-bit Macho calling convention.
231 static const TargetRegisterClass * const Macho32_CalleeSavedRegClasses[] = {
232 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
233 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
234 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
235 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
236 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
238 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
239 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
240 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
241 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
242 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
244 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
246 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
247 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
248 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
250 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
251 &PPC::CRBITRCRegClass,
252 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
253 &PPC::CRBITRCRegClass,
254 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
255 &PPC::CRBITRCRegClass,
257 &PPC::GPRCRegClass, 0
260 static const TargetRegisterClass * const ELF32_CalleeSavedRegClasses[] = {
261 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
262 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
263 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
264 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
265 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
268 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
269 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
270 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
271 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
272 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
273 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
275 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
277 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
278 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
279 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
281 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
282 &PPC::CRBITRCRegClass,
283 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
284 &PPC::CRBITRCRegClass,
285 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
286 &PPC::CRBITRCRegClass,
288 &PPC::GPRCRegClass, 0
291 // 64-bit Macho calling convention.
292 static const TargetRegisterClass * const Macho64_CalleeSavedRegClasses[] = {
293 &PPC::G8RCRegClass,&PPC::G8RCRegClass,
294 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
295 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
296 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
297 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
299 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
300 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
301 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
302 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
303 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
305 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
307 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
308 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
309 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
311 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
312 &PPC::CRBITRCRegClass,
313 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
314 &PPC::CRBITRCRegClass,
315 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
316 &PPC::CRBITRCRegClass,
318 &PPC::G8RCRegClass, 0
321 if (Subtarget.isMachoABI())
322 return Subtarget.isPPC64() ? Macho64_CalleeSavedRegClasses :
323 Macho32_CalleeSavedRegClasses;
326 return ELF32_CalleeSavedRegClasses;
329 // needsFP - Return true if the specified function should have a dedicated frame
330 // pointer register. This is true if the function has variable sized allocas or
331 // if frame pointer elimination is disabled.
333 static bool needsFP(const MachineFunction &MF) {
334 const MachineFrameInfo *MFI = MF.getFrameInfo();
335 return NoFramePointerElim || MFI->hasVarSizedObjects();
338 static bool spillsCR(const MachineFunction &MF) {
339 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
340 return FuncInfo->isCRSpilled();
343 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
344 BitVector Reserved(getNumRegs());
345 Reserved.set(PPC::R0);
346 Reserved.set(PPC::R1);
347 Reserved.set(PPC::LR);
348 Reserved.set(PPC::LR8);
350 // In Linux, r2 is reserved for the OS.
351 if (!Subtarget.isDarwin())
352 Reserved.set(PPC::R2);
354 // On PPC64, r13 is the thread pointer. Never allocate this register. Note
355 // that this is over conservative, as it also prevents allocation of R31 when
356 // the FP is not needed.
357 if (Subtarget.isPPC64()) {
358 Reserved.set(PPC::R13);
359 Reserved.set(PPC::R31);
361 if (!EnableRegisterScavenging)
362 Reserved.set(PPC::R0); // FIXME (64-bit): Remove
364 Reserved.set(PPC::X0);
365 Reserved.set(PPC::X1);
366 Reserved.set(PPC::X13);
367 Reserved.set(PPC::X31);
371 Reserved.set(PPC::R31);
376 //===----------------------------------------------------------------------===//
377 // Stack Frame Processing methods
378 //===----------------------------------------------------------------------===//
380 // hasFP - Return true if the specified function actually has a dedicated frame
381 // pointer register. This is true if the function needs a frame pointer and has
382 // a non-zero stack size.
383 bool PPCRegisterInfo::hasFP(const MachineFunction &MF) const {
384 const MachineFrameInfo *MFI = MF.getFrameInfo();
385 return MFI->getStackSize() && needsFP(MF);
388 /// MustSaveLR - Return true if this function requires that we save the LR
389 /// register onto the stack in the prolog and restore it in the epilog of the
391 static bool MustSaveLR(const MachineFunction &MF) {
392 const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>();
394 // We need an save/restore of LR if there is any use/def of LR explicitly, or
395 // if there is some use of the LR stack slot (e.g. for builtin_return_address.
396 return MFI->usesLR() || MFI->isLRStoreRequired() ||
397 // FIXME: Anything that has a call should clobber the LR register,
398 // isn't this redundant??
399 MF.getFrameInfo()->hasCalls();
402 void PPCRegisterInfo::
403 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
404 MachineBasicBlock::iterator I) const {
405 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
409 /// findScratchRegister - Find a 'free' PPC register. Try for a call-clobbered
410 /// register first and then a spilled callee-saved register if that fails.
412 unsigned findScratchRegister(MachineBasicBlock::iterator II, RegScavenger *RS,
413 const TargetRegisterClass *RC, int SPAdj) {
414 assert(RS && "Register scavenging must be on");
415 unsigned Reg = RS->FindUnusedReg(RC, true);
416 // FIXME: move ARM callee-saved reg scan to target independent code, then
417 // search for already spilled CS register here.
419 Reg = RS->scavengeRegister(RC, II, SPAdj);
423 /// lowerDynamicAlloc - Generate the code for allocating an object in the
424 /// current frame. The sequence of code with be in the general form
426 /// addi R0, SP, #frameSize ; get the address of the previous frame
427 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size
428 /// addi Rnew, SP, #maxCalFrameSize ; get the top of the allocation
430 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II,
431 int SPAdj, RegScavenger *RS) const {
432 // Get the instruction.
433 MachineInstr &MI = *II;
434 // Get the instruction's basic block.
435 MachineBasicBlock &MBB = *MI.getParent();
436 // Get the basic block's function.
437 MachineFunction &MF = *MBB.getParent();
438 // Get the frame info.
439 MachineFrameInfo *MFI = MF.getFrameInfo();
440 // Determine whether 64-bit pointers are used.
441 bool LP64 = Subtarget.isPPC64();
443 // Get the maximum call stack size.
444 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
445 // Get the total frame size.
446 unsigned FrameSize = MFI->getStackSize();
448 // Get stack alignments.
449 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
450 unsigned MaxAlign = MFI->getMaxAlignment();
451 assert(MaxAlign <= TargetAlign &&
452 "Dynamic alloca with large aligns not supported");
454 // Determine the previous frame's address. If FrameSize can't be
455 // represented as 16 bits or we need special alignment, then we load the
456 // previous frame's address from 0(SP). Why not do an addis of the hi?
457 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
458 // Constructing the constant and adding would take 3 instructions.
459 // Fortunately, a frame greater than 32K is rare.
460 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
461 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
462 const TargetRegisterClass *RC = LP64 ? G8RC : GPRC;
464 // FIXME (64-bit): Use "findScratchRegister"
466 if (EnableRegisterScavenging)
467 Reg = findScratchRegister(II, RS, RC, SPAdj);
471 if (MaxAlign < TargetAlign && isInt16(FrameSize)) {
472 BuildMI(MBB, II, TII.get(PPC::ADDI), Reg)
476 if (EnableRegisterScavenging) // FIXME (64-bit): Use "true" part.
477 BuildMI(MBB, II, TII.get(PPC::LD), Reg)
481 BuildMI(MBB, II, TII.get(PPC::LD), PPC::X0)
485 BuildMI(MBB, II, TII.get(PPC::LWZ), Reg)
490 // Grow the stack and update the stack pointer link, then determine the
491 // address of new allocated space.
493 if (EnableRegisterScavenging) // FIXME (64-bit): Use "true" part.
494 BuildMI(MBB, II, TII.get(PPC::STDUX))
495 .addReg(Reg, false, false, true)
497 .addReg(MI.getOperand(1).getReg());
499 BuildMI(MBB, II, TII.get(PPC::STDUX))
500 .addReg(PPC::X0, false, false, true)
502 .addReg(MI.getOperand(1).getReg());
504 if (!MI.getOperand(1).isKill())
505 BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
507 .addImm(maxCallFrameSize);
509 // Implicitly kill the register.
510 BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
512 .addImm(maxCallFrameSize)
513 .addReg(MI.getOperand(1).getReg(), false, true, true);
515 BuildMI(MBB, II, TII.get(PPC::STWUX))
516 .addReg(Reg, false, false, true)
518 .addReg(MI.getOperand(1).getReg());
520 if (!MI.getOperand(1).isKill())
521 BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
523 .addImm(maxCallFrameSize);
525 // Implicitly kill the register.
526 BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
528 .addImm(maxCallFrameSize)
529 .addReg(MI.getOperand(1).getReg(), false, true, true);
532 // Discard the DYNALLOC instruction.
536 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of
537 /// reserving a whole register (R0), we scrounge for one here. This generates
540 /// mfcr rA ; Move the conditional register into GPR rA.
541 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot.
542 /// stw rA, FI ; Store rA to the frame.
544 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II,
545 unsigned FrameIndex, int SPAdj,
546 RegScavenger *RS) const {
547 // Get the instruction.
548 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>, <FI>
549 // Get the instruction's basic block.
550 MachineBasicBlock &MBB = *MI.getParent();
552 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
553 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
554 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC;
555 unsigned Reg = findScratchRegister(II, RS, RC, SPAdj);
557 // We need to store the CR in the low 4-bits of the saved value. First, issue
558 // an MFCR to save all of the CRBits. Add an implicit kill of the CR.
559 if (!MI.getOperand(0).isKill())
560 BuildMI(MBB, II, TII.get(PPC::MFCR), Reg);
562 // Implicitly kill the CR register.
563 BuildMI(MBB, II, TII.get(PPC::MFCR), Reg)
564 .addReg(MI.getOperand(0).getReg(), false, true, true);
566 // If the saved register wasn't CR0, shift the bits left so that they are in
568 unsigned SrcReg = MI.getOperand(0).getReg();
569 if (SrcReg != PPC::CR0)
570 // rlwinm rA, rA, ShiftBits, 0, 31.
571 BuildMI(MBB, II, TII.get(PPC::RLWINM), Reg)
572 .addReg(Reg, false, false, true)
573 .addImm(PPCRegisterInfo::getRegisterNumbering(SrcReg) * 4)
577 addFrameReference(BuildMI(MBB, II, TII.get(PPC::STW))
578 .addReg(Reg, false, false, MI.getOperand(1).getImm()),
581 // Discard the pseudo instruction.
585 void PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
586 int SPAdj, RegScavenger *RS) const {
587 assert(SPAdj == 0 && "Unexpected");
589 // Get the instruction.
590 MachineInstr &MI = *II;
591 // Get the instruction's basic block.
592 MachineBasicBlock &MBB = *MI.getParent();
593 // Get the basic block's function.
594 MachineFunction &MF = *MBB.getParent();
595 // Get the frame info.
596 MachineFrameInfo *MFI = MF.getFrameInfo();
598 // Find out which operand is the frame index.
599 unsigned FIOperandNo = 0;
600 while (!MI.getOperand(FIOperandNo).isFrameIndex()) {
602 assert(FIOperandNo != MI.getNumOperands() &&
603 "Instr doesn't have FrameIndex operand!");
605 // Take into account whether it's an add or mem instruction
606 unsigned OffsetOperandNo = (FIOperandNo == 2) ? 1 : 2;
607 if (MI.getOpcode() == TargetInstrInfo::INLINEASM)
608 OffsetOperandNo = FIOperandNo-1;
610 // Get the frame index.
611 int FrameIndex = MI.getOperand(FIOperandNo).getIndex();
613 // Get the frame pointer save index. Users of this index are primarily
614 // DYNALLOC instructions.
615 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
616 int FPSI = FI->getFramePointerSaveIndex();
617 // Get the instruction opcode.
618 unsigned OpC = MI.getOpcode();
620 // Special case for dynamic alloca.
621 if (FPSI && FrameIndex == FPSI &&
622 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
623 lowerDynamicAlloc(II, SPAdj, RS);
627 // Special case for pseudo-op SPILL_CR.
628 if (EnableRegisterScavenging) // FIXME (64-bit): Enable by default.
629 if (OpC == PPC::SPILL_CR) {
630 lowerCRSpilling(II, FrameIndex, SPAdj, RS);
634 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
635 MI.getOperand(FIOperandNo).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1,
638 // Figure out if the offset in the instruction is shifted right two bits. This
639 // is true for instructions like "STD", which the machine implicitly adds two
641 bool isIXAddr = false;
651 // Now add the frame object offset to the offset from r1.
652 int Offset = MFI->getObjectOffset(FrameIndex);
654 Offset += MI.getOperand(OffsetOperandNo).getImm();
656 Offset += MI.getOperand(OffsetOperandNo).getImm() << 2;
658 // If we're not using a Frame Pointer that has been set to the value of the
659 // SP before having the stack size subtracted from it, then add the stack size
660 // to Offset to get the correct offset.
661 Offset += MFI->getStackSize();
663 // If we can, encode the offset directly into the instruction. If this is a
664 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If
665 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits
666 // clear can be encoded. This is extremely uncommon, because normally you
667 // only "std" to a stack slot that is at least 4-byte aligned, but it can
668 // happen in invalid code.
669 if (isInt16(Offset) && (!isIXAddr || (Offset & 3) == 0)) {
671 Offset >>= 2; // The actual encoded value has the low two bits zero.
672 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
676 // The offset doesn't fit into a single register, scavenge one to build the
678 // FIXME: figure out what SPAdj is doing here.
680 // FIXME (64-bit): Use "findScratchRegister".
682 if (EnableRegisterScavenging)
683 SReg = findScratchRegister(II, RS, &PPC::GPRCRegClass, SPAdj);
687 // Insert a set of rA with the full offset value before the ld, st, or add
688 BuildMI(MBB, II, TII.get(PPC::LIS), SReg)
689 .addImm(Offset >> 16);
690 BuildMI(MBB, II, TII.get(PPC::ORI), SReg)
691 .addReg(SReg, false, false, true)
694 // Convert into indexed form of the instruction:
696 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
697 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
698 unsigned OperandBase;
700 if (OpC != TargetInstrInfo::INLINEASM) {
701 assert(ImmToIdxMap.count(OpC) &&
702 "No indexed form of load or store available!");
703 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second;
704 MI.setDesc(TII.get(NewOpcode));
707 OperandBase = OffsetOperandNo;
710 unsigned StackReg = MI.getOperand(FIOperandNo).getReg();
711 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false);
712 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false);
715 /// VRRegNo - Map from a numbered VR register to its enum value.
717 static const unsigned short VRRegNo[] = {
718 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
719 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
720 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
721 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
724 /// RemoveVRSaveCode - We have found that this function does not need any code
725 /// to manipulate the VRSAVE register, even though it uses vector registers.
726 /// This can happen when the only registers used are known to be live in or out
727 /// of the function. Remove all of the VRSAVE related code from the function.
728 static void RemoveVRSaveCode(MachineInstr *MI) {
729 MachineBasicBlock *Entry = MI->getParent();
730 MachineFunction *MF = Entry->getParent();
732 // We know that the MTVRSAVE instruction immediately follows MI. Remove it.
733 MachineBasicBlock::iterator MBBI = MI;
735 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
736 MBBI->eraseFromParent();
738 bool RemovedAllMTVRSAVEs = true;
739 // See if we can find and remove the MTVRSAVE instruction from all of the
741 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
742 // If last instruction is a return instruction, add an epilogue
743 if (!I->empty() && I->back().getDesc().isReturn()) {
744 bool FoundIt = false;
745 for (MBBI = I->end(); MBBI != I->begin(); ) {
747 if (MBBI->getOpcode() == PPC::MTVRSAVE) {
748 MBBI->eraseFromParent(); // remove it.
753 RemovedAllMTVRSAVEs &= FoundIt;
757 // If we found and removed all MTVRSAVE instructions, remove the read of
759 if (RemovedAllMTVRSAVEs) {
761 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
763 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
764 MBBI->eraseFromParent();
767 // Finally, nuke the UPDATE_VRSAVE.
768 MI->eraseFromParent();
771 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
772 // instruction selector. Based on the vector registers that have been used,
773 // transform this into the appropriate ORI instruction.
774 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) {
775 MachineFunction *MF = MI->getParent()->getParent();
777 unsigned UsedRegMask = 0;
778 for (unsigned i = 0; i != 32; ++i)
779 if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i]))
780 UsedRegMask |= 1 << (31-i);
782 // Live in and live out values already must be in the mask, so don't bother
784 for (MachineRegisterInfo::livein_iterator
785 I = MF->getRegInfo().livein_begin(),
786 E = MF->getRegInfo().livein_end(); I != E; ++I) {
787 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first);
788 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg.
789 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
791 for (MachineRegisterInfo::liveout_iterator
792 I = MF->getRegInfo().liveout_begin(),
793 E = MF->getRegInfo().liveout_end(); I != E; ++I) {
794 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I);
795 if (VRRegNo[RegNo] == *I) // If this really is a vector reg.
796 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
799 // If no registers are used, turn this into a copy.
800 if (UsedRegMask == 0) {
801 // Remove all VRSAVE code.
802 RemoveVRSaveCode(MI);
806 unsigned SrcReg = MI->getOperand(1).getReg();
807 unsigned DstReg = MI->getOperand(0).getReg();
809 if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
810 if (DstReg != SrcReg)
811 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg)
813 .addImm(UsedRegMask);
815 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg)
816 .addReg(SrcReg, false, false, true)
817 .addImm(UsedRegMask);
818 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
819 if (DstReg != SrcReg)
820 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
822 .addImm(UsedRegMask >> 16);
824 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
825 .addReg(SrcReg, false, false, true)
826 .addImm(UsedRegMask >> 16);
828 if (DstReg != SrcReg)
829 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
831 .addImm(UsedRegMask >> 16);
833 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
834 .addReg(SrcReg, false, false, true)
835 .addImm(UsedRegMask >> 16);
837 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg)
838 .addReg(DstReg, false, false, true)
839 .addImm(UsedRegMask & 0xFFFF);
842 // Remove the old UPDATE_VRSAVE instruction.
843 MI->eraseFromParent();
846 /// determineFrameLayout - Determine the size of the frame and maximum call
848 void PPCRegisterInfo::determineFrameLayout(MachineFunction &MF) const {
849 MachineFrameInfo *MFI = MF.getFrameInfo();
851 // Get the number of bytes to allocate from the FrameInfo
852 unsigned FrameSize = MFI->getStackSize();
854 // Get the alignments provided by the target, and the maximum alignment
855 // (if any) of the fixed frame objects.
856 unsigned MaxAlign = MFI->getMaxAlignment();
857 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
858 unsigned AlignMask = TargetAlign - 1; //
860 // If we are a leaf function, and use up to 224 bytes of stack space,
861 // don't have a frame pointer, calls, or dynamic alloca then we do not need
862 // to adjust the stack pointer (we fit in the Red Zone).
863 if (FrameSize <= 224 && // Fits in red zone.
864 !MFI->hasVarSizedObjects() && // No dynamic alloca.
865 !MFI->hasCalls() && // No calls.
866 (!ALIGN_STACK || MaxAlign <= TargetAlign)) { // No special alignment.
868 MFI->setStackSize(0);
872 // Get the maximum call frame size of all the calls.
873 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
875 // Maximum call frame needs to be at least big enough for linkage and 8 args.
876 unsigned minCallFrameSize =
877 PPCFrameInfo::getMinCallFrameSize(Subtarget.isPPC64(),
878 Subtarget.isMachoABI());
879 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
881 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
882 // that allocations will be aligned.
883 if (MFI->hasVarSizedObjects())
884 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
886 // Update maximum call frame size.
887 MFI->setMaxCallFrameSize(maxCallFrameSize);
889 // Include call frame size in total.
890 FrameSize += maxCallFrameSize;
892 // Make sure the frame is aligned.
893 FrameSize = (FrameSize + AlignMask) & ~AlignMask;
895 // Update frame info.
896 MFI->setStackSize(FrameSize);
900 PPCRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
901 RegScavenger *RS) const {
902 // Save and clear the LR state.
903 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
904 unsigned LR = getRARegister();
905 FI->setUsesLR(MF.getRegInfo().isPhysRegUsed(LR));
906 MF.getRegInfo().setPhysRegUnused(LR);
908 // Save R31 if necessary
909 int FPSI = FI->getFramePointerSaveIndex();
910 bool IsPPC64 = Subtarget.isPPC64();
911 bool IsELF32_ABI = Subtarget.isELF32_ABI();
912 bool IsMachoABI = Subtarget.isMachoABI();
913 MachineFrameInfo *MFI = MF.getFrameInfo();
915 // If the frame pointer save index hasn't been defined yet.
916 if (!FPSI && (NoFramePointerElim || MFI->hasVarSizedObjects()) &&
918 // Find out what the fix offset of the frame pointer save area.
919 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64,
921 // Allocate the frame index for frame pointer save area.
922 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset);
924 FI->setFramePointerSaveIndex(FPSI);
927 // Reserve a slot closest to SP or frame pointer if we have a dynalloc or
928 // a large stack, which will require scavenging a register to materialize a
930 // FIXME: this doesn't actually check stack size, so is a bit pessimistic
931 // FIXME: doesn't detect whether or not we need to spill vXX, which requires
934 if (EnableRegisterScavenging) // FIXME (64-bit): Enable.
935 if (needsFP(MF) || spillsCR(MF)) {
936 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
937 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
938 const TargetRegisterClass *RC = IsPPC64 ? G8RC : GPRC;
939 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
940 RC->getAlignment()));
945 PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
946 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
947 MachineBasicBlock::iterator MBBI = MBB.begin();
948 MachineFrameInfo *MFI = MF.getFrameInfo();
949 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
950 bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) ||
951 !MF.getFunction()->doesNotThrow() ||
952 UnwindTablesMandatory;
954 // Prepare for frame info.
955 unsigned FrameLabelId = 0;
957 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
959 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
960 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
961 HandleVRSaveUpdate(MBBI, TII);
966 // Move MBBI back to the beginning of the function.
969 // Work out frame sizes.
970 determineFrameLayout(MF);
971 unsigned FrameSize = MFI->getStackSize();
973 int NegFrameSize = -FrameSize;
975 // Get processor type.
976 bool IsPPC64 = Subtarget.isPPC64();
977 // Get operating system
978 bool IsMachoABI = Subtarget.isMachoABI();
979 // Check if the link register (LR) has been used.
980 bool UsesLR = MustSaveLR(MF);
981 // Do we have a frame pointer for this function?
982 bool HasFP = hasFP(MF) && FrameSize;
984 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI);
985 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI);
989 BuildMI(MBB, MBBI, TII.get(PPC::MFLR8), PPC::X0);
992 BuildMI(MBB, MBBI, TII.get(PPC::STD))
998 BuildMI(MBB, MBBI, TII.get(PPC::STD))
1000 .addImm(LROffset / 4)
1004 BuildMI(MBB, MBBI, TII.get(PPC::MFLR), PPC::R0);
1007 BuildMI(MBB, MBBI, TII.get(PPC::STW))
1013 BuildMI(MBB, MBBI, TII.get(PPC::STW))
1019 // Skip if a leaf routine.
1020 if (!FrameSize) return;
1022 // Get stack alignments.
1023 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
1024 unsigned MaxAlign = MFI->getMaxAlignment();
1026 if (needsFrameMoves) {
1027 // Mark effective beginning of when frame pointer becomes valid.
1028 FrameLabelId = MMI->NextLabelID();
1029 BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(FrameLabelId).addImm(0);
1032 // Adjust stack pointer: r1 += NegFrameSize.
1033 // If there is a preferred stack alignment, align R1 now
1036 if (ALIGN_STACK && MaxAlign > TargetAlign) {
1037 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!");
1038 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!");
1040 BuildMI(MBB, MBBI, TII.get(PPC::RLWINM), PPC::R0)
1043 .addImm(32 - Log2_32(MaxAlign))
1045 BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC) ,PPC::R0)
1046 .addReg(PPC::R0, false, false, true)
1047 .addImm(NegFrameSize);
1048 BuildMI(MBB, MBBI, TII.get(PPC::STWUX))
1052 } else if (isInt16(NegFrameSize)) {
1053 BuildMI(MBB, MBBI, TII.get(PPC::STWU), PPC::R1)
1055 .addImm(NegFrameSize)
1058 BuildMI(MBB, MBBI, TII.get(PPC::LIS), PPC::R0)
1059 .addImm(NegFrameSize >> 16);
1060 BuildMI(MBB, MBBI, TII.get(PPC::ORI), PPC::R0)
1061 .addReg(PPC::R0, false, false, true)
1062 .addImm(NegFrameSize & 0xFFFF);
1063 BuildMI(MBB, MBBI, TII.get(PPC::STWUX))
1069 if (ALIGN_STACK && MaxAlign > TargetAlign) {
1070 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!");
1071 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!");
1073 BuildMI(MBB, MBBI, TII.get(PPC::RLDICL), PPC::X0)
1076 .addImm(64 - Log2_32(MaxAlign));
1077 BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC8), PPC::X0)
1079 .addImm(NegFrameSize);
1080 BuildMI(MBB, MBBI, TII.get(PPC::STDUX))
1084 } else if (isInt16(NegFrameSize)) {
1085 BuildMI(MBB, MBBI, TII.get(PPC::STDU), PPC::X1)
1087 .addImm(NegFrameSize / 4)
1090 BuildMI(MBB, MBBI, TII.get(PPC::LIS8), PPC::X0)
1091 .addImm(NegFrameSize >> 16);
1092 BuildMI(MBB, MBBI, TII.get(PPC::ORI8), PPC::X0)
1093 .addReg(PPC::X0, false, false, true)
1094 .addImm(NegFrameSize & 0xFFFF);
1095 BuildMI(MBB, MBBI, TII.get(PPC::STDUX))
1102 if (needsFrameMoves) {
1103 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
1106 // Show update of SP.
1107 MachineLocation SPDst(MachineLocation::VirtualFP);
1108 MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize);
1109 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
1111 MachineLocation SP(IsPPC64 ? PPC::X31 : PPC::R31);
1112 Moves.push_back(MachineMove(FrameLabelId, SP, SP));
1116 MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset);
1117 MachineLocation FPSrc(IsPPC64 ? PPC::X31 : PPC::R31);
1118 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc));
1121 // Add callee saved registers to move list.
1122 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1123 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
1124 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
1125 unsigned Reg = CSI[I].getReg();
1126 if (Reg == PPC::LR || Reg == PPC::LR8) continue;
1127 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
1128 MachineLocation CSSrc(Reg);
1129 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
1132 MachineLocation LRDst(MachineLocation::VirtualFP, LROffset);
1133 MachineLocation LRSrc(IsPPC64 ? PPC::LR8 : PPC::LR);
1134 Moves.push_back(MachineMove(FrameLabelId, LRDst, LRSrc));
1136 // Mark effective beginning of when frame pointer is ready.
1137 unsigned ReadyLabelId = MMI->NextLabelID();
1138 BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(ReadyLabelId).addImm(0);
1140 MachineLocation FPDst(HasFP ? (IsPPC64 ? PPC::X31 : PPC::R31) :
1141 (IsPPC64 ? PPC::X1 : PPC::R1));
1142 MachineLocation FPSrc(MachineLocation::VirtualFP);
1143 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
1146 // If there is a frame pointer, copy R1 into R31
1149 BuildMI(MBB, MBBI, TII.get(PPC::OR), PPC::R31)
1153 BuildMI(MBB, MBBI, TII.get(PPC::OR8), PPC::X31)
1160 void PPCRegisterInfo::emitEpilogue(MachineFunction &MF,
1161 MachineBasicBlock &MBB) const {
1162 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1163 assert(MBBI->getOpcode() == PPC::BLR &&
1164 "Can only insert epilog into returning blocks");
1166 // Get alignment info so we know how to restore r1
1167 const MachineFrameInfo *MFI = MF.getFrameInfo();
1168 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
1169 unsigned MaxAlign = MFI->getMaxAlignment();
1171 // Get the number of bytes allocated from the FrameInfo.
1172 unsigned FrameSize = MFI->getStackSize();
1174 // Get processor type.
1175 bool IsPPC64 = Subtarget.isPPC64();
1176 // Get operating system
1177 bool IsMachoABI = Subtarget.isMachoABI();
1178 // Check if the link register (LR) has been used.
1179 bool UsesLR = MustSaveLR(MF);
1180 // Do we have a frame pointer for this function?
1181 bool HasFP = hasFP(MF) && FrameSize;
1183 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI);
1184 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI);
1187 // The loaded (or persistent) stack pointer value is offset by the 'stwu'
1188 // on entry to the function. Add this offset back now.
1189 if (!Subtarget.isPPC64()) {
1190 if (isInt16(FrameSize) && (!ALIGN_STACK || TargetAlign >= MaxAlign) &&
1191 !MFI->hasVarSizedObjects()) {
1192 BuildMI(MBB, MBBI, TII.get(PPC::ADDI), PPC::R1)
1193 .addReg(PPC::R1).addImm(FrameSize);
1195 BuildMI(MBB, MBBI, TII.get(PPC::LWZ),PPC::R1).addImm(0).addReg(PPC::R1);
1198 if (isInt16(FrameSize) && TargetAlign >= MaxAlign &&
1199 !MFI->hasVarSizedObjects()) {
1200 BuildMI(MBB, MBBI, TII.get(PPC::ADDI8), PPC::X1)
1201 .addReg(PPC::X1).addImm(FrameSize);
1203 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X1).addImm(0).addReg(PPC::X1);
1210 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X0)
1211 .addImm(LROffset/4).addReg(PPC::X1);
1214 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X31)
1215 .addImm(FPOffset/4).addReg(PPC::X1);
1218 BuildMI(MBB, MBBI, TII.get(PPC::MTLR8)).addReg(PPC::X0);
1221 BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R0)
1222 .addImm(LROffset).addReg(PPC::R1);
1225 BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R31)
1226 .addImm(FPOffset).addReg(PPC::R1);
1229 BuildMI(MBB, MBBI, TII.get(PPC::MTLR)).addReg(PPC::R0);
1233 unsigned PPCRegisterInfo::getRARegister() const {
1234 return !Subtarget.isPPC64() ? PPC::LR : PPC::LR8;
1237 unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const {
1238 if (!Subtarget.isPPC64())
1239 return hasFP(MF) ? PPC::R31 : PPC::R1;
1241 return hasFP(MF) ? PPC::X31 : PPC::X1;
1244 void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
1246 // Initial state of the frame pointer is R1.
1247 MachineLocation Dst(MachineLocation::VirtualFP);
1248 MachineLocation Src(PPC::R1, 0);
1249 Moves.push_back(MachineMove(0, Dst, Src));
1252 unsigned PPCRegisterInfo::getEHExceptionRegister() const {
1253 return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3;
1256 unsigned PPCRegisterInfo::getEHHandlerRegister() const {
1257 return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4;
1260 int PPCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
1261 // FIXME: Most probably dwarf numbers differs for Linux and Darwin
1262 return PPCGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
1265 #include "PPCGenRegisterInfo.inc"