1 //===- PPC32RegisterInfo.cpp - PowerPC32 Register Information ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC32 implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "reginfo"
16 #include "PowerPCInstrBuilder.h"
17 #include "PPC32RegisterInfo.h"
18 #include "llvm/Constants.h"
19 #include "llvm/Type.h"
20 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/Target/TargetFrameInfo.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/ADT/STLExtras.h"
34 PPC32RegisterInfo::PPC32RegisterInfo()
35 : PPC32GenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP) {
36 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
37 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
38 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
39 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
40 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
41 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
42 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
43 ImmToIdxMap[PPC::ADDI] = PPC::ADD;
46 static const TargetRegisterClass *getClass(unsigned SrcReg) {
47 if (PPC32::GPRCRegisterClass->contains(SrcReg))
48 return PPC32::GPRCRegisterClass;
49 if (PPC32::FPRCRegisterClass->contains(SrcReg))
50 return PPC32::FPRCRegisterClass;
51 assert(PPC32::CRRCRegisterClass->contains(SrcReg) &&"Reg not FPR, GPR, CRRC");
52 return PPC32::CRRCRegisterClass;
55 static unsigned getIdx(const TargetRegisterClass *RC) {
56 if (RC == PPC32::GPRCRegisterClass) {
57 switch (RC->getSize()) {
58 default: assert(0 && "Invalid data size!");
63 } else if (RC == PPC32::FPRCRegisterClass) {
64 switch (RC->getSize()) {
65 default: assert(0 && "Invalid data size!");
69 } else if (RC == PPC32::CRRCRegisterClass) {
70 switch (RC->getSize()) {
71 default: assert(0 && "Invalid data size!");
75 std::cerr << "Invalid register class to getIdx()!\n";
80 PPC32RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
81 MachineBasicBlock::iterator MI,
82 unsigned SrcReg, int FrameIdx) const {
83 static const unsigned Opcode[] = {
84 PPC::STB, PPC::STH, PPC::STW, PPC::STFS, PPC::STFD
86 const TargetRegisterClass *RegClass = getClass(SrcReg);
87 unsigned OC = Opcode[getIdx(RegClass)];
88 if (SrcReg == PPC::LR) {
89 BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11);
90 addFrameReference(BuildMI(MBB, MI, OC, 3).addReg(PPC::R11),FrameIdx);
91 } else if (RegClass == PPC32::CRRCRegisterClass) {
92 BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R11);
93 addFrameReference(BuildMI(MBB, MI, OC, 3).addReg(PPC::R11),FrameIdx);
95 addFrameReference(BuildMI(MBB, MI, OC, 3).addReg(SrcReg),FrameIdx);
100 PPC32RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
101 MachineBasicBlock::iterator MI,
102 unsigned DestReg, int FrameIdx) const {
103 static const unsigned Opcode[] = {
104 PPC::LBZ, PPC::LHZ, PPC::LWZ, PPC::LFS, PPC::LFD
106 const TargetRegisterClass *RegClass = getClass(DestReg);
107 unsigned OC = Opcode[getIdx(RegClass)];
108 if (DestReg == PPC::LR) {
109 addFrameReference(BuildMI(MBB, MI, OC, 2, PPC::R11), FrameIdx);
110 BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11);
111 } else if (RegClass == PPC32::CRRCRegisterClass) {
112 addFrameReference(BuildMI(MBB, MI, OC, 2, PPC::R11), FrameIdx);
113 BuildMI(MBB, MI, PPC::MTCRF, 1, DestReg).addReg(PPC::R11);
115 addFrameReference(BuildMI(MBB, MI, OC, 2, DestReg), FrameIdx);
119 void PPC32RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
120 MachineBasicBlock::iterator MI,
121 unsigned DestReg, unsigned SrcReg,
122 const TargetRegisterClass *RC) const {
125 if (RC == PPC32::GPRCRegisterClass) {
126 BuildMI(MBB, MI, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
127 } else if (RC == PPC32::FPRCRegisterClass) {
128 BuildMI(MBB, MI, PPC::FMR, 1, DestReg).addReg(SrcReg);
129 } else if (RC == PPC32::CRRCRegisterClass) {
130 BuildMI(MBB, MI, PPC::MCRF, 1, DestReg).addReg(SrcReg);
132 std::cerr << "Attempt to copy register that is not GPR or FPR";
137 //===----------------------------------------------------------------------===//
138 // Stack Frame Processing methods
139 //===----------------------------------------------------------------------===//
141 // hasFP - Return true if the specified function should have a dedicated frame
142 // pointer register. This is true if the function has variable sized allocas or
143 // if frame pointer elimination is disabled.
145 static bool hasFP(MachineFunction &MF) {
146 return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
149 void PPC32RegisterInfo::
150 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
151 MachineBasicBlock::iterator I) const {
153 // If we have a frame pointer, convert as follows:
154 // ADJCALLSTACKDOWN -> addi, r1, r1, -amount
155 // ADJCALLSTACKUP -> addi, r1, r1, amount
156 MachineInstr *Old = I;
157 unsigned Amount = Old->getOperand(0).getImmedValue();
159 // We need to keep the stack aligned properly. To do this, we round the
160 // amount of space needed for the outgoing arguments up to the next
161 // alignment boundary.
162 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
163 Amount = (Amount+Align-1)/Align*Align;
165 // Replace the pseudo instruction with a new instruction...
166 if (Old->getOpcode() == PPC::ADJCALLSTACKDOWN) {
167 MBB.insert(I, BuildMI(PPC::ADDI, 2, PPC::R1).addReg(PPC::R1)
170 assert(Old->getOpcode() == PPC::ADJCALLSTACKUP);
171 MBB.insert(I, BuildMI(PPC::ADDI, 2, PPC::R1).addReg(PPC::R1)
180 PPC32RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
182 MachineInstr &MI = *II;
183 MachineBasicBlock &MBB = *MI.getParent();
184 MachineFunction &MF = *MBB.getParent();
186 while (!MI.getOperand(i).isFrameIndex()) {
188 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
191 int FrameIndex = MI.getOperand(i).getFrameIndex();
193 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
194 MI.SetMachineOperandReg(i, hasFP(MF) ? PPC::R31 : PPC::R1);
196 // Take into account whether it's an add or mem instruction
197 unsigned OffIdx = (i == 2) ? 1 : 2;
199 // Now add the frame object offset to the offset from r1.
200 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
201 MI.getOperand(OffIdx).getImmedValue();
203 // If we're not using a Frame Pointer that has been set to the value of the
204 // SP before having the stack size subtracted from it, then add the stack size
205 // to Offset to get the correct offset.
206 Offset += MF.getFrameInfo()->getStackSize();
208 if (Offset > 32767 || Offset < -32768) {
209 // Insert a set of r0 with the full offset value before the ld, st, or add
210 MachineBasicBlock *MBB = MI.getParent();
211 MBB->insert(II, BuildMI(PPC::LIS, 1, PPC::R0).addSImm(Offset >> 16));
212 MBB->insert(II, BuildMI(PPC::ORI, 2, PPC::R0).addReg(PPC::R0)
214 // convert into indexed form of the instruction
215 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
216 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
217 unsigned NewOpcode = const_cast<std::map<unsigned, unsigned>& >(ImmToIdxMap)[MI.getOpcode()];
218 assert(NewOpcode && "No indexed form of load or store available!");
219 MI.setOpcode(NewOpcode);
220 MI.SetMachineOperandReg(1, MI.getOperand(i).getReg());
221 MI.SetMachineOperandReg(2, PPC::R0);
223 MI.SetMachineOperandConst(OffIdx,MachineOperand::MO_SignExtendedImmed,Offset);
228 void PPC32RegisterInfo::emitPrologue(MachineFunction &MF) const {
229 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
230 MachineBasicBlock::iterator MBBI = MBB.begin();
231 MachineFrameInfo *MFI = MF.getFrameInfo();
234 // Get the number of bytes to allocate from the FrameInfo
235 unsigned NumBytes = MFI->getStackSize();
237 // If we have calls, we cannot use the red zone to store callee save registers
238 // and we must set up a stack frame, so calculate the necessary size here.
239 if (MFI->hasCalls()) {
240 // We reserve argument space for call sites in the function immediately on
241 // entry to the current function. This eliminates the need for add/sub
242 // brackets around call sites.
243 NumBytes += MFI->getMaxCallFrameSize();
246 // If we are a leaf function, and use up to 224 bytes of stack space,
247 // and don't have a frame pointer, then we do not need to adjust the stack
248 // pointer (we fit in the Red Zone).
249 if ((NumBytes == 0) || (NumBytes <= 224 && !hasFP(MF) && !MFI->hasCalls())) {
250 MFI->setStackSize(0);
254 // Add the size of R1 to NumBytes size for the store of R1 to the bottom
255 // of the stack and round the size to a multiple of the alignment.
256 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
257 unsigned GPRSize = getSpillSize(PPC::R1)/8;
258 unsigned Size = hasFP(MF) ? GPRSize + GPRSize : GPRSize;
259 NumBytes = (NumBytes+Size+Align-1)/Align*Align;
261 // Update frame info to pretend that this is part of the stack...
262 MFI->setStackSize(NumBytes);
264 // Adjust stack pointer: r1 -= numbytes.
265 if (NumBytes <= 32768) {
266 MI=BuildMI(PPC::STWU,3).addReg(PPC::R1).addSImm(-NumBytes).addReg(PPC::R1);
267 MBB.insert(MBBI, MI);
269 int NegNumbytes = -NumBytes;
270 MI = BuildMI(PPC::LIS, 1, PPC::R0).addSImm(NegNumbytes >> 16);
271 MBB.insert(MBBI, MI);
272 MI = BuildMI(PPC::ORI, 2, PPC::R0).addReg(PPC::R0)
273 .addImm(NegNumbytes & 0xFFFF);
274 MBB.insert(MBBI, MI);
275 MI = BuildMI(PPC::STWUX, 3).addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
276 MBB.insert(MBBI, MI);
280 MI = BuildMI(PPC::STW, 3).addReg(PPC::R31).addSImm(GPRSize).addReg(PPC::R1);
281 MBB.insert(MBBI, MI);
282 MI = BuildMI(PPC::OR, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1);
283 MBB.insert(MBBI, MI);
287 void PPC32RegisterInfo::emitEpilogue(MachineFunction &MF,
288 MachineBasicBlock &MBB) const {
289 const MachineFrameInfo *MFI = MF.getFrameInfo();
290 MachineBasicBlock::iterator MBBI = prior(MBB.end());
292 assert(MBBI->getOpcode() == PPC::BLR &&
293 "Can only insert epilog into returning blocks");
295 // Get the number of bytes allocated from the FrameInfo...
296 unsigned NumBytes = MFI->getStackSize();
297 unsigned GPRSize = getSpillSize(PPC::R31)/8;
301 MI = BuildMI(PPC::LWZ, 2, PPC::R31).addSImm(GPRSize).addReg(PPC::R31);
302 MBB.insert(MBBI, MI);
304 MI = BuildMI(PPC::LWZ, 2, PPC::R1).addSImm(0).addReg(PPC::R1);
305 MBB.insert(MBBI, MI);
309 #include "PPC32GenRegisterInfo.inc"