1 //===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetRegisterInfo
13 //===----------------------------------------------------------------------===//
15 #include "PPCRegisterInfo.h"
17 #include "PPCFrameLowering.h"
18 #include "PPCInstrBuilder.h"
19 #include "PPCMachineFunctionInfo.h"
20 #include "PPCSubtarget.h"
21 #include "llvm/ADT/BitVector.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineModuleInfo.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/RegisterScavenging.h"
29 #include "llvm/IR/CallingConv.h"
30 #include "llvm/IR/Constants.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/IR/Type.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/Support/raw_ostream.h"
38 #include "llvm/Target/TargetFrameLowering.h"
39 #include "llvm/Target/TargetInstrInfo.h"
40 #include "llvm/Target/TargetMachine.h"
41 #include "llvm/Target/TargetOptions.h"
46 #define DEBUG_TYPE "reginfo"
48 #define GET_REGINFO_TARGET_DESC
49 #include "PPCGenRegisterInfo.inc"
52 EnableBasePointer("ppc-use-base-pointer", cl::Hidden, cl::init(true),
53 cl::desc("Enable use of a base pointer for complex stack frames"));
56 AlwaysBasePointer("ppc-always-use-base-pointer", cl::Hidden, cl::init(false),
57 cl::desc("Force the use of a base pointer in every function"));
59 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST)
60 : PPCGenRegisterInfo(ST.isPPC64() ? PPC::LR8 : PPC::LR,
62 ST.isPPC64() ? 0 : 1),
64 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
65 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
66 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
67 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
68 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
69 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
70 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
71 ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
72 ImmToIdxMap[PPC::LWA_32] = PPC::LWAX_32;
75 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8;
76 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8;
77 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8;
78 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX;
79 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8;
82 /// getPointerRegClass - Return the register class to use to hold pointers.
83 /// This is used for addressing modes.
84 const TargetRegisterClass *
85 PPCRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
87 // Note that PPCInstrInfo::FoldImmediate also directly uses this Kind value
88 // when it checks for ZERO folding.
90 if (Subtarget.isPPC64())
91 return &PPC::G8RC_NOX0RegClass;
92 return &PPC::GPRC_NOR0RegClass;
95 if (Subtarget.isPPC64())
96 return &PPC::G8RCRegClass;
97 return &PPC::GPRCRegClass;
101 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
102 if (MF->getFunction()->getCallingConv() == CallingConv::AnyReg) {
103 if (Subtarget.hasVSX())
104 return CSR_64_AllRegs_VSX_SaveList;
105 if (Subtarget.hasAltivec())
106 return CSR_64_AllRegs_Altivec_SaveList;
107 return CSR_64_AllRegs_SaveList;
110 if (Subtarget.isDarwinABI())
111 return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ?
112 CSR_Darwin64_Altivec_SaveList :
113 CSR_Darwin64_SaveList) :
114 (Subtarget.hasAltivec() ?
115 CSR_Darwin32_Altivec_SaveList :
116 CSR_Darwin32_SaveList);
118 // On PPC64, we might need to save r2 (but only if it is not reserved).
119 bool SaveR2 = MF->getRegInfo().isAllocatable(PPC::X2);
121 return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ?
122 (SaveR2 ? CSR_SVR464_R2_Altivec_SaveList :
123 CSR_SVR464_Altivec_SaveList) :
124 (SaveR2 ? CSR_SVR464_R2_SaveList :
125 CSR_SVR464_SaveList)) :
126 (Subtarget.hasAltivec() ?
127 CSR_SVR432_Altivec_SaveList :
128 CSR_SVR432_SaveList);
132 PPCRegisterInfo::getCallPreservedMask(CallingConv::ID CC) const {
133 if (CC == CallingConv::AnyReg) {
134 if (Subtarget.hasVSX())
135 return CSR_64_AllRegs_VSX_RegMask;
136 if (Subtarget.hasAltivec())
137 return CSR_64_AllRegs_Altivec_RegMask;
138 return CSR_64_AllRegs_RegMask;
141 if (Subtarget.isDarwinABI())
142 return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ?
143 CSR_Darwin64_Altivec_RegMask :
144 CSR_Darwin64_RegMask) :
145 (Subtarget.hasAltivec() ?
146 CSR_Darwin32_Altivec_RegMask :
147 CSR_Darwin32_RegMask);
149 return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ?
150 CSR_SVR464_Altivec_RegMask :
151 CSR_SVR464_RegMask) :
152 (Subtarget.hasAltivec() ?
153 CSR_SVR432_Altivec_RegMask :
158 PPCRegisterInfo::getNoPreservedMask() const {
159 return CSR_NoRegs_RegMask;
162 void PPCRegisterInfo::adjustStackMapLiveOutMask(uint32_t *Mask) const {
163 unsigned PseudoRegs[] = { PPC::ZERO, PPC::ZERO8, PPC::RM };
164 for (unsigned i = 0, ie = array_lengthof(PseudoRegs); i != ie; ++i) {
165 unsigned Reg = PseudoRegs[i];
166 Mask[Reg / 32] &= ~(1u << (Reg % 32));
170 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
171 BitVector Reserved(getNumRegs());
172 const PPCFrameLowering *PPCFI =
173 static_cast<const PPCFrameLowering *>(Subtarget.getFrameLowering());
175 // The ZERO register is not really a register, but the representation of r0
176 // when used in instructions that treat r0 as the constant 0.
177 Reserved.set(PPC::ZERO);
178 Reserved.set(PPC::ZERO8);
180 // The FP register is also not really a register, but is the representation
181 // of the frame pointer register used by ISD::FRAMEADDR.
182 Reserved.set(PPC::FP);
183 Reserved.set(PPC::FP8);
185 // The BP register is also not really a register, but is the representation
186 // of the base pointer register used by setjmp.
187 Reserved.set(PPC::BP);
188 Reserved.set(PPC::BP8);
190 // The counter registers must be reserved so that counter-based loops can
191 // be correctly formed (and the mtctr instructions are not DCE'd).
192 Reserved.set(PPC::CTR);
193 Reserved.set(PPC::CTR8);
195 Reserved.set(PPC::R1);
196 Reserved.set(PPC::LR);
197 Reserved.set(PPC::LR8);
198 Reserved.set(PPC::RM);
200 if (!Subtarget.isDarwinABI() || !Subtarget.hasAltivec())
201 Reserved.set(PPC::VRSAVE);
203 // The SVR4 ABI reserves r2 and r13
204 if (Subtarget.isSVR4ABI()) {
205 Reserved.set(PPC::R2); // System-reserved register
206 Reserved.set(PPC::R13); // Small Data Area pointer register
209 // On PPC64, r13 is the thread pointer. Never allocate this register.
210 if (Subtarget.isPPC64()) {
211 Reserved.set(PPC::R13);
213 Reserved.set(PPC::X1);
214 Reserved.set(PPC::X13);
216 if (PPCFI->needsFP(MF))
217 Reserved.set(PPC::X31);
219 if (hasBasePointer(MF))
220 Reserved.set(PPC::X30);
222 // The 64-bit SVR4 ABI reserves r2 for the TOC pointer.
223 if (Subtarget.isSVR4ABI()) {
224 // We only reserve r2 if we need to use the TOC pointer. If we have no
225 // explicit uses of the TOC pointer (meaning we're a leaf function with
226 // no constant-pool loads, etc.) and we have no potential uses inside an
227 // inline asm block, then we can treat r2 has an ordinary callee-saved
229 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
230 if (FuncInfo->usesTOCBasePtr() || MF.hasInlineAsm())
231 Reserved.set(PPC::X2);
233 Reserved.reset(PPC::R2);
237 if (PPCFI->needsFP(MF))
238 Reserved.set(PPC::R31);
240 if (hasBasePointer(MF)) {
241 if (Subtarget.isSVR4ABI() && !Subtarget.isPPC64() &&
242 MF.getTarget().getRelocationModel() == Reloc::PIC_)
243 Reserved.set(PPC::R29);
245 Reserved.set(PPC::R30);
248 if (Subtarget.isSVR4ABI() && !Subtarget.isPPC64() &&
249 MF.getTarget().getRelocationModel() == Reloc::PIC_)
250 Reserved.set(PPC::R30);
252 // Reserve Altivec registers when Altivec is unavailable.
253 if (!Subtarget.hasAltivec())
254 for (TargetRegisterClass::iterator I = PPC::VRRCRegClass.begin(),
255 IE = PPC::VRRCRegClass.end(); I != IE; ++I)
261 unsigned PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
262 MachineFunction &MF) const {
263 const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
264 const unsigned DefaultSafety = 1;
266 switch (RC->getID()) {
269 case PPC::G8RC_NOX0RegClassID:
270 case PPC::GPRC_NOR0RegClassID:
271 case PPC::G8RCRegClassID:
272 case PPC::GPRCRegClassID: {
273 unsigned FP = TFI->hasFP(MF) ? 1 : 0;
274 return 32 - FP - DefaultSafety;
276 case PPC::F8RCRegClassID:
277 case PPC::F4RCRegClassID:
278 case PPC::QFRCRegClassID:
279 case PPC::QSRCRegClassID:
280 case PPC::QBRCRegClassID:
281 case PPC::VRRCRegClassID:
282 case PPC::VFRCRegClassID:
283 case PPC::VSLRCRegClassID:
284 case PPC::VSHRCRegClassID:
285 return 32 - DefaultSafety;
286 case PPC::VSRCRegClassID:
287 case PPC::VSFRCRegClassID:
288 return 64 - DefaultSafety;
289 case PPC::CRRCRegClassID:
290 return 8 - DefaultSafety;
294 const TargetRegisterClass *PPCRegisterInfo::getLargestLegalSuperClass(
295 const TargetRegisterClass *RC) const {
296 if (Subtarget.hasVSX()) {
297 // With VSX, we can inflate various sub-register classes to the full VSX
300 if (RC == &PPC::F8RCRegClass)
301 return &PPC::VSFRCRegClass;
302 else if (RC == &PPC::VRRCRegClass)
303 return &PPC::VSRCRegClass;
306 return TargetRegisterInfo::getLargestLegalSuperClass(RC);
309 //===----------------------------------------------------------------------===//
310 // Stack Frame Processing methods
311 //===----------------------------------------------------------------------===//
313 /// lowerDynamicAlloc - Generate the code for allocating an object in the
314 /// current frame. The sequence of code with be in the general form
316 /// addi R0, SP, \#frameSize ; get the address of the previous frame
317 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size
318 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation
320 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const {
321 // Get the instruction.
322 MachineInstr &MI = *II;
323 // Get the instruction's basic block.
324 MachineBasicBlock &MBB = *MI.getParent();
325 // Get the basic block's function.
326 MachineFunction &MF = *MBB.getParent();
327 // Get the frame info.
328 MachineFrameInfo *MFI = MF.getFrameInfo();
329 // Get the instruction info.
330 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
331 // Determine whether 64-bit pointers are used.
332 bool LP64 = Subtarget.isPPC64();
333 DebugLoc dl = MI.getDebugLoc();
335 // Get the maximum call stack size.
336 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
337 // Get the total frame size.
338 unsigned FrameSize = MFI->getStackSize();
340 // Get stack alignments.
341 unsigned TargetAlign = Subtarget.getFrameLowering()->getStackAlignment();
342 unsigned MaxAlign = MFI->getMaxAlignment();
343 assert((maxCallFrameSize & (MaxAlign-1)) == 0 &&
344 "Maximum call-frame size not sufficiently aligned");
346 // Determine the previous frame's address. If FrameSize can't be
347 // represented as 16 bits or we need special alignment, then we load the
348 // previous frame's address from 0(SP). Why not do an addis of the hi?
349 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
350 // Constructing the constant and adding would take 3 instructions.
351 // Fortunately, a frame greater than 32K is rare.
352 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
353 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
354 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
356 if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) {
357 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg)
361 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg)
365 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg)
370 bool KillNegSizeReg = MI.getOperand(1).isKill();
371 unsigned NegSizeReg = MI.getOperand(1).getReg();
373 // Grow the stack and update the stack pointer link, then determine the
374 // address of new allocated space.
376 if (MaxAlign > TargetAlign) {
377 unsigned UnalNegSizeReg = NegSizeReg;
378 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC);
380 // Unfortunately, there is no andi, only andi., and we can't insert that
381 // here because we might clobber cr0 while it is live.
382 BuildMI(MBB, II, dl, TII.get(PPC::LI8), NegSizeReg)
383 .addImm(~(MaxAlign-1));
385 unsigned NegSizeReg1 = NegSizeReg;
386 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC);
387 BuildMI(MBB, II, dl, TII.get(PPC::AND8), NegSizeReg)
388 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg))
389 .addReg(NegSizeReg1, RegState::Kill);
390 KillNegSizeReg = true;
393 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1)
394 .addReg(Reg, RegState::Kill)
396 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg));
397 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
399 .addImm(maxCallFrameSize);
401 if (MaxAlign > TargetAlign) {
402 unsigned UnalNegSizeReg = NegSizeReg;
403 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC);
405 // Unfortunately, there is no andi, only andi., and we can't insert that
406 // here because we might clobber cr0 while it is live.
407 BuildMI(MBB, II, dl, TII.get(PPC::LI), NegSizeReg)
408 .addImm(~(MaxAlign-1));
410 unsigned NegSizeReg1 = NegSizeReg;
411 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC);
412 BuildMI(MBB, II, dl, TII.get(PPC::AND), NegSizeReg)
413 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg))
414 .addReg(NegSizeReg1, RegState::Kill);
415 KillNegSizeReg = true;
418 BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1)
419 .addReg(Reg, RegState::Kill)
421 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg));
422 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
424 .addImm(maxCallFrameSize);
427 // Discard the DYNALLOC instruction.
431 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of
432 /// reserving a whole register (R0), we scrounge for one here. This generates
435 /// mfcr rA ; Move the conditional register into GPR rA.
436 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot.
437 /// stw rA, FI ; Store rA to the frame.
439 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II,
440 unsigned FrameIndex) const {
441 // Get the instruction.
442 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>
443 // Get the instruction's basic block.
444 MachineBasicBlock &MBB = *MI.getParent();
445 MachineFunction &MF = *MBB.getParent();
446 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
447 DebugLoc dl = MI.getDebugLoc();
449 bool LP64 = Subtarget.isPPC64();
450 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
451 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
453 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
454 unsigned SrcReg = MI.getOperand(0).getReg();
456 // We need to store the CR in the low 4-bits of the saved value. First, issue
457 // an MFOCRF to save all of the CRBits and, if needed, kill the SrcReg.
458 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg)
459 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
461 // If the saved register wasn't CR0, shift the bits left so that they are in
463 if (SrcReg != PPC::CR0) {
465 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
467 // rlwinm rA, rA, ShiftBits, 0, 31.
468 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
469 .addReg(Reg1, RegState::Kill)
470 .addImm(getEncodingValue(SrcReg) * 4)
475 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW))
476 .addReg(Reg, RegState::Kill),
479 // Discard the pseudo instruction.
483 void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II,
484 unsigned FrameIndex) const {
485 // Get the instruction.
486 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset>
487 // Get the instruction's basic block.
488 MachineBasicBlock &MBB = *MI.getParent();
489 MachineFunction &MF = *MBB.getParent();
490 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
491 DebugLoc dl = MI.getDebugLoc();
493 bool LP64 = Subtarget.isPPC64();
494 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
495 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
497 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
498 unsigned DestReg = MI.getOperand(0).getReg();
499 assert(MI.definesRegister(DestReg) &&
500 "RESTORE_CR does not define its destination");
502 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ),
505 // If the reloaded register isn't CR0, shift the bits right so that they are
506 // in the right CR's slot.
507 if (DestReg != PPC::CR0) {
509 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
511 unsigned ShiftBits = getEncodingValue(DestReg)*4;
512 // rlwinm r11, r11, 32-ShiftBits, 0, 31.
513 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
514 .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0)
518 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), DestReg)
519 .addReg(Reg, RegState::Kill);
521 // Discard the pseudo instruction.
525 static unsigned getCRFromCRBit(unsigned SrcReg) {
527 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
528 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
530 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
531 SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
533 else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT ||
534 SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN)
536 else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
537 SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
539 else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
540 SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
542 else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT ||
543 SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN)
545 else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
546 SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
548 else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
549 SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
552 assert(Reg != 0 && "Invalid CR bit register");
556 void PPCRegisterInfo::lowerCRBitSpilling(MachineBasicBlock::iterator II,
557 unsigned FrameIndex) const {
558 // Get the instruction.
559 MachineInstr &MI = *II; // ; SPILL_CRBIT <SrcReg>, <offset>
560 // Get the instruction's basic block.
561 MachineBasicBlock &MBB = *MI.getParent();
562 MachineFunction &MF = *MBB.getParent();
563 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
564 DebugLoc dl = MI.getDebugLoc();
566 bool LP64 = Subtarget.isPPC64();
567 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
568 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
570 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
571 unsigned SrcReg = MI.getOperand(0).getReg();
573 BuildMI(MBB, II, dl, TII.get(TargetOpcode::KILL),
574 getCRFromCRBit(SrcReg))
575 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
577 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg)
578 .addReg(getCRFromCRBit(SrcReg));
580 // If the saved register wasn't CR0LT, shift the bits left so that the bit to
581 // store is the first one. Mask all but that bit.
583 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
585 // rlwinm rA, rA, ShiftBits, 0, 0.
586 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
587 .addReg(Reg1, RegState::Kill)
588 .addImm(getEncodingValue(SrcReg))
589 .addImm(0).addImm(0);
591 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW))
592 .addReg(Reg, RegState::Kill),
595 // Discard the pseudo instruction.
599 void PPCRegisterInfo::lowerCRBitRestore(MachineBasicBlock::iterator II,
600 unsigned FrameIndex) const {
601 // Get the instruction.
602 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CRBIT <offset>
603 // Get the instruction's basic block.
604 MachineBasicBlock &MBB = *MI.getParent();
605 MachineFunction &MF = *MBB.getParent();
606 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
607 DebugLoc dl = MI.getDebugLoc();
609 bool LP64 = Subtarget.isPPC64();
610 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
611 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
613 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
614 unsigned DestReg = MI.getOperand(0).getReg();
615 assert(MI.definesRegister(DestReg) &&
616 "RESTORE_CRBIT does not define its destination");
618 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ),
621 BuildMI(MBB, II, dl, TII.get(TargetOpcode::IMPLICIT_DEF), DestReg);
623 unsigned RegO = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
624 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), RegO)
625 .addReg(getCRFromCRBit(DestReg));
627 unsigned ShiftBits = getEncodingValue(DestReg);
628 // rlwimi r11, r10, 32-ShiftBits, ..., ...
629 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWIMI8 : PPC::RLWIMI), RegO)
630 .addReg(RegO, RegState::Kill).addReg(Reg, RegState::Kill)
631 .addImm(ShiftBits ? 32-ShiftBits : 0)
632 .addImm(ShiftBits).addImm(ShiftBits);
634 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF),
635 getCRFromCRBit(DestReg))
636 .addReg(RegO, RegState::Kill)
637 // Make sure we have a use dependency all the way through this
638 // sequence of instructions. We can't have the other bits in the CR
639 // modified in between the mfocrf and the mtocrf.
640 .addReg(getCRFromCRBit(DestReg), RegState::Implicit);
642 // Discard the pseudo instruction.
646 void PPCRegisterInfo::lowerVRSAVESpilling(MachineBasicBlock::iterator II,
647 unsigned FrameIndex) const {
648 // Get the instruction.
649 MachineInstr &MI = *II; // ; SPILL_VRSAVE <SrcReg>, <offset>
650 // Get the instruction's basic block.
651 MachineBasicBlock &MBB = *MI.getParent();
652 MachineFunction &MF = *MBB.getParent();
653 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
654 DebugLoc dl = MI.getDebugLoc();
656 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
657 unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC);
658 unsigned SrcReg = MI.getOperand(0).getReg();
660 BuildMI(MBB, II, dl, TII.get(PPC::MFVRSAVEv), Reg)
661 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
663 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::STW))
664 .addReg(Reg, RegState::Kill),
667 // Discard the pseudo instruction.
671 void PPCRegisterInfo::lowerVRSAVERestore(MachineBasicBlock::iterator II,
672 unsigned FrameIndex) const {
673 // Get the instruction.
674 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_VRSAVE <offset>
675 // Get the instruction's basic block.
676 MachineBasicBlock &MBB = *MI.getParent();
677 MachineFunction &MF = *MBB.getParent();
678 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
679 DebugLoc dl = MI.getDebugLoc();
681 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
682 unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC);
683 unsigned DestReg = MI.getOperand(0).getReg();
684 assert(MI.definesRegister(DestReg) &&
685 "RESTORE_VRSAVE does not define its destination");
687 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::LWZ),
690 BuildMI(MBB, II, dl, TII.get(PPC::MTVRSAVEv), DestReg)
691 .addReg(Reg, RegState::Kill);
693 // Discard the pseudo instruction.
698 PPCRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
699 unsigned Reg, int &FrameIdx) const {
701 // For the nonvolatile condition registers (CR2, CR3, CR4) in an SVR4
702 // ABI, return true to prevent allocating an additional frame slot.
703 // For 64-bit, the CR save area is at SP+8; the value of FrameIdx = 0
704 // is arbitrary and will be subsequently ignored. For 32-bit, we have
705 // previously created the stack slot if needed, so return its FrameIdx.
706 if (Subtarget.isSVR4ABI() && PPC::CR2 <= Reg && Reg <= PPC::CR4) {
707 if (Subtarget.isPPC64())
710 const PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
711 FrameIdx = FI->getCRSpillFrameIndex();
718 // Figure out if the offset in the instruction must be a multiple of 4.
719 // This is true for instructions like "STD".
720 static bool usesIXAddr(const MachineInstr &MI) {
721 unsigned OpC = MI.getOpcode();
734 // Return the OffsetOperandNo given the FIOperandNum (and the instruction).
735 static unsigned getOffsetONFromFION(const MachineInstr &MI,
736 unsigned FIOperandNum) {
737 // Take into account whether it's an add or mem instruction
738 unsigned OffsetOperandNo = (FIOperandNum == 2) ? 1 : 2;
739 if (MI.isInlineAsm())
740 OffsetOperandNo = FIOperandNum - 1;
741 else if (MI.getOpcode() == TargetOpcode::STACKMAP ||
742 MI.getOpcode() == TargetOpcode::PATCHPOINT)
743 OffsetOperandNo = FIOperandNum + 1;
745 return OffsetOperandNo;
749 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
750 int SPAdj, unsigned FIOperandNum,
751 RegScavenger *RS) const {
752 assert(SPAdj == 0 && "Unexpected");
754 // Get the instruction.
755 MachineInstr &MI = *II;
756 // Get the instruction's basic block.
757 MachineBasicBlock &MBB = *MI.getParent();
758 // Get the basic block's function.
759 MachineFunction &MF = *MBB.getParent();
760 // Get the instruction info.
761 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
762 // Get the frame info.
763 MachineFrameInfo *MFI = MF.getFrameInfo();
764 DebugLoc dl = MI.getDebugLoc();
766 unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum);
768 // Get the frame index.
769 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
771 // Get the frame pointer save index. Users of this index are primarily
772 // DYNALLOC instructions.
773 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
774 int FPSI = FI->getFramePointerSaveIndex();
775 // Get the instruction opcode.
776 unsigned OpC = MI.getOpcode();
778 // Special case for dynamic alloca.
779 if (FPSI && FrameIndex == FPSI &&
780 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
781 lowerDynamicAlloc(II);
785 // Special case for pseudo-ops SPILL_CR and RESTORE_CR, etc.
786 if (OpC == PPC::SPILL_CR) {
787 lowerCRSpilling(II, FrameIndex);
789 } else if (OpC == PPC::RESTORE_CR) {
790 lowerCRRestore(II, FrameIndex);
792 } else if (OpC == PPC::SPILL_CRBIT) {
793 lowerCRBitSpilling(II, FrameIndex);
795 } else if (OpC == PPC::RESTORE_CRBIT) {
796 lowerCRBitRestore(II, FrameIndex);
798 } else if (OpC == PPC::SPILL_VRSAVE) {
799 lowerVRSAVESpilling(II, FrameIndex);
801 } else if (OpC == PPC::RESTORE_VRSAVE) {
802 lowerVRSAVERestore(II, FrameIndex);
806 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
807 MI.getOperand(FIOperandNum).ChangeToRegister(
808 FrameIndex < 0 ? getBaseRegister(MF) : getFrameRegister(MF), false);
810 // Figure out if the offset in the instruction is shifted right two bits.
811 bool isIXAddr = usesIXAddr(MI);
813 // If the instruction is not present in ImmToIdxMap, then it has no immediate
814 // form (and must be r+r).
815 bool noImmForm = !MI.isInlineAsm() && OpC != TargetOpcode::STACKMAP &&
816 OpC != TargetOpcode::PATCHPOINT && !ImmToIdxMap.count(OpC);
818 // Now add the frame object offset to the offset from r1.
819 int Offset = MFI->getObjectOffset(FrameIndex);
820 Offset += MI.getOperand(OffsetOperandNo).getImm();
822 // If we're not using a Frame Pointer that has been set to the value of the
823 // SP before having the stack size subtracted from it, then add the stack size
824 // to Offset to get the correct offset.
825 // Naked functions have stack size 0, although getStackSize may not reflect that
826 // because we didn't call all the pieces that compute it for naked functions.
827 if (!MF.getFunction()->hasFnAttribute(Attribute::Naked)) {
828 if (!(hasBasePointer(MF) && FrameIndex < 0))
829 Offset += MFI->getStackSize();
832 // If we can, encode the offset directly into the instruction. If this is a
833 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If
834 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits
835 // clear can be encoded. This is extremely uncommon, because normally you
836 // only "std" to a stack slot that is at least 4-byte aligned, but it can
837 // happen in invalid code.
838 assert(OpC != PPC::DBG_VALUE &&
839 "This should be handled in a target-independent way");
840 if (!noImmForm && ((isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0)) ||
841 OpC == TargetOpcode::STACKMAP ||
842 OpC == TargetOpcode::PATCHPOINT)) {
843 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
847 // The offset doesn't fit into a single register, scavenge one to build the
850 bool is64Bit = Subtarget.isPPC64();
851 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
852 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
853 const TargetRegisterClass *RC = is64Bit ? G8RC : GPRC;
854 unsigned SRegHi = MF.getRegInfo().createVirtualRegister(RC),
855 SReg = MF.getRegInfo().createVirtualRegister(RC);
857 // Insert a set of rA with the full offset value before the ld, st, or add
858 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SRegHi)
859 .addImm(Offset >> 16);
860 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg)
861 .addReg(SRegHi, RegState::Kill)
864 // Convert into indexed form of the instruction:
866 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
867 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
868 unsigned OperandBase;
872 else if (OpC != TargetOpcode::INLINEASM) {
873 assert(ImmToIdxMap.count(OpC) &&
874 "No indexed form of load or store available!");
875 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second;
876 MI.setDesc(TII.get(NewOpcode));
879 OperandBase = OffsetOperandNo;
882 unsigned StackReg = MI.getOperand(FIOperandNum).getReg();
883 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false);
884 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true);
887 unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
888 const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
890 if (!Subtarget.isPPC64())
891 return TFI->hasFP(MF) ? PPC::R31 : PPC::R1;
893 return TFI->hasFP(MF) ? PPC::X31 : PPC::X1;
896 unsigned PPCRegisterInfo::getBaseRegister(const MachineFunction &MF) const {
897 if (!hasBasePointer(MF))
898 return getFrameRegister(MF);
900 if (Subtarget.isPPC64())
903 if (Subtarget.isSVR4ABI() &&
904 MF.getTarget().getRelocationModel() == Reloc::PIC_)
910 bool PPCRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
911 if (!EnableBasePointer)
913 if (AlwaysBasePointer)
916 // If we need to realign the stack, then the stack pointer can no longer
917 // serve as an offset into the caller's stack space. As a result, we need a
919 return needsStackRealignment(MF);
922 bool PPCRegisterInfo::canRealignStack(const MachineFunction &MF) const {
923 if (MF.getFunction()->hasFnAttribute("no-realign-stack"))
929 bool PPCRegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
930 const MachineFrameInfo *MFI = MF.getFrameInfo();
931 const Function *F = MF.getFunction();
932 unsigned StackAlign = Subtarget.getFrameLowering()->getStackAlignment();
933 bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) ||
934 F->hasFnAttribute(Attribute::StackAlignment));
936 return requiresRealignment && canRealignStack(MF);
939 /// Returns true if the instruction's frame index
940 /// reference would be better served by a base register other than FP
941 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
942 /// references it should create new base registers for.
943 bool PPCRegisterInfo::
944 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
945 assert(Offset < 0 && "Local offset must be negative");
947 // It's the load/store FI references that cause issues, as it can be difficult
948 // to materialize the offset if it won't fit in the literal field. Estimate
949 // based on the size of the local frame and some conservative assumptions
950 // about the rest of the stack frame (note, this is pre-regalloc, so
951 // we don't know everything for certain yet) whether this offset is likely
952 // to be out of range of the immediate. Return true if so.
954 // We only generate virtual base registers for loads and stores that have
955 // an r+i form. Return false for everything else.
956 unsigned OpC = MI->getOpcode();
957 if (!ImmToIdxMap.count(OpC))
960 // Don't generate a new virtual base register just to add zero to it.
961 if ((OpC == PPC::ADDI || OpC == PPC::ADDI8) &&
962 MI->getOperand(2).getImm() == 0)
965 MachineBasicBlock &MBB = *MI->getParent();
966 MachineFunction &MF = *MBB.getParent();
968 const PPCFrameLowering *PPCFI =
969 static_cast<const PPCFrameLowering *>(Subtarget.getFrameLowering());
971 PPCFI->determineFrameLayout(MF, false, true);
973 // If we likely don't need a stack frame, then we probably don't need a
974 // virtual base register either.
978 // Estimate an offset from the stack pointer.
979 // The incoming offset is relating to the SP at the start of the function,
980 // but when we access the local it'll be relative to the SP after local
981 // allocation, so adjust our SP-relative offset by that allocation size.
984 // The frame pointer will point to the end of the stack, so estimate the
985 // offset as the difference between the object offset and the FP location.
986 return !isFrameOffsetLegal(MI, Offset);
989 /// Insert defining instruction(s) for BaseReg to
990 /// be a pointer to FrameIdx at the beginning of the basic block.
991 void PPCRegisterInfo::
992 materializeFrameBaseRegister(MachineBasicBlock *MBB,
993 unsigned BaseReg, int FrameIdx,
994 int64_t Offset) const {
995 unsigned ADDriOpc = Subtarget.isPPC64() ? PPC::ADDI8 : PPC::ADDI;
997 MachineBasicBlock::iterator Ins = MBB->begin();
998 DebugLoc DL; // Defaults to "unknown"
999 if (Ins != MBB->end())
1000 DL = Ins->getDebugLoc();
1002 const MachineFunction &MF = *MBB->getParent();
1003 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1004 const MCInstrDesc &MCID = TII.get(ADDriOpc);
1005 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1006 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
1008 BuildMI(*MBB, Ins, DL, MCID, BaseReg)
1009 .addFrameIndex(FrameIdx).addImm(Offset);
1012 void PPCRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
1013 int64_t Offset) const {
1014 unsigned FIOperandNum = 0;
1015 while (!MI.getOperand(FIOperandNum).isFI()) {
1017 assert(FIOperandNum < MI.getNumOperands() &&
1018 "Instr doesn't have FrameIndex operand!");
1021 MI.getOperand(FIOperandNum).ChangeToRegister(BaseReg, false);
1022 unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum);
1023 Offset += MI.getOperand(OffsetOperandNo).getImm();
1024 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
1026 MachineBasicBlock &MBB = *MI.getParent();
1027 MachineFunction &MF = *MBB.getParent();
1028 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1029 const MCInstrDesc &MCID = MI.getDesc();
1030 MachineRegisterInfo &MRI = MF.getRegInfo();
1031 MRI.constrainRegClass(BaseReg,
1032 TII.getRegClass(MCID, FIOperandNum, this, MF));
1035 bool PPCRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
1036 int64_t Offset) const {
1037 unsigned FIOperandNum = 0;
1038 while (!MI->getOperand(FIOperandNum).isFI()) {
1040 assert(FIOperandNum < MI->getNumOperands() &&
1041 "Instr doesn't have FrameIndex operand!");
1044 unsigned OffsetOperandNo = getOffsetONFromFION(*MI, FIOperandNum);
1045 Offset += MI->getOperand(OffsetOperandNo).getImm();
1047 return MI->getOpcode() == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm
1048 MI->getOpcode() == TargetOpcode::STACKMAP ||
1049 MI->getOpcode() == TargetOpcode::PATCHPOINT ||
1050 (isInt<16>(Offset) && (!usesIXAddr(*MI) || (Offset & 3) == 0));