1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetRegisterInfo
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "reginfo"
17 #include "PPCInstrBuilder.h"
18 #include "PPCMachineFunctionInfo.h"
19 #include "PPCRegisterInfo.h"
20 #include "PPCFrameLowering.h"
21 #include "PPCSubtarget.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/Function.h"
25 #include "llvm/Type.h"
26 #include "llvm/CodeGen/ValueTypes.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineModuleInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/RegisterScavenging.h"
33 #include "llvm/Target/TargetFrameLowering.h"
34 #include "llvm/Target/TargetInstrInfo.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
37 #include "llvm/Support/CommandLine.h"
38 #include "llvm/Support/Debug.h"
39 #include "llvm/Support/ErrorHandling.h"
40 #include "llvm/Support/MathExtras.h"
41 #include "llvm/Support/raw_ostream.h"
42 #include "llvm/ADT/BitVector.h"
43 #include "llvm/ADT/STLExtras.h"
46 #define GET_REGINFO_TARGET_DESC
47 #include "PPCGenRegisterInfo.inc"
49 // FIXME (64-bit): Eventually enable by default.
51 cl::opt<bool> EnablePPC32RS("enable-ppc32-regscavenger",
53 cl::desc("Enable PPC32 register scavenger"),
55 cl::opt<bool> EnablePPC64RS("enable-ppc64-regscavenger",
57 cl::desc("Enable PPC64 register scavenger"),
63 // FIXME (64-bit): Should be inlined.
65 PPCRegisterInfo::requiresRegisterScavenging(const MachineFunction &) const {
66 return ((EnablePPC32RS && !Subtarget.isPPC64()) ||
67 (EnablePPC64RS && Subtarget.isPPC64()));
70 /// getRegisterNumbering - Given the enum value for some register, e.g.
71 /// PPC::F14, return the number that it corresponds to (e.g. 14).
72 unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
76 case R0 : case X0 : case F0 : case V0 : case CR0: case CR0LT: return 0;
77 case R1 : case X1 : case F1 : case V1 : case CR1: case CR0GT: return 1;
78 case R2 : case X2 : case F2 : case V2 : case CR2: case CR0EQ: return 2;
79 case R3 : case X3 : case F3 : case V3 : case CR3: case CR0UN: return 3;
80 case R4 : case X4 : case F4 : case V4 : case CR4: case CR1LT: return 4;
81 case R5 : case X5 : case F5 : case V5 : case CR5: case CR1GT: return 5;
82 case R6 : case X6 : case F6 : case V6 : case CR6: case CR1EQ: return 6;
83 case R7 : case X7 : case F7 : case V7 : case CR7: case CR1UN: return 7;
84 case R8 : case X8 : case F8 : case V8 : case CR2LT: return 8;
85 case R9 : case X9 : case F9 : case V9 : case CR2GT: return 9;
86 case R10: case X10: case F10: case V10: case CR2EQ: return 10;
87 case R11: case X11: case F11: case V11: case CR2UN: return 11;
88 case R12: case X12: case F12: case V12: case CR3LT: return 12;
89 case R13: case X13: case F13: case V13: case CR3GT: return 13;
90 case R14: case X14: case F14: case V14: case CR3EQ: return 14;
91 case R15: case X15: case F15: case V15: case CR3UN: return 15;
92 case R16: case X16: case F16: case V16: case CR4LT: return 16;
93 case R17: case X17: case F17: case V17: case CR4GT: return 17;
94 case R18: case X18: case F18: case V18: case CR4EQ: return 18;
95 case R19: case X19: case F19: case V19: case CR4UN: return 19;
96 case R20: case X20: case F20: case V20: case CR5LT: return 20;
97 case R21: case X21: case F21: case V21: case CR5GT: return 21;
98 case R22: case X22: case F22: case V22: case CR5EQ: return 22;
99 case R23: case X23: case F23: case V23: case CR5UN: return 23;
100 case R24: case X24: case F24: case V24: case CR6LT: return 24;
101 case R25: case X25: case F25: case V25: case CR6GT: return 25;
102 case R26: case X26: case F26: case V26: case CR6EQ: return 26;
103 case R27: case X27: case F27: case V27: case CR6UN: return 27;
104 case R28: case X28: case F28: case V28: case CR7LT: return 28;
105 case R29: case X29: case F29: case V29: case CR7GT: return 29;
106 case R30: case X30: case F30: case V30: case CR7EQ: return 30;
107 case R31: case X31: case F31: case V31: case CR7UN: return 31;
109 llvm_unreachable("Unhandled reg in PPCRegisterInfo::getRegisterNumbering!");
113 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST,
114 const TargetInstrInfo &tii)
115 : PPCGenRegisterInfo(ST.isPPC64() ? PPC::LR8 : PPC::LR,
116 ST.isPPC64() ? 0 : 1,
117 ST.isPPC64() ? 0 : 1),
118 Subtarget(ST), TII(tii) {
119 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
120 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
121 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
122 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
123 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
124 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
125 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
126 ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
129 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8;
130 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8;
131 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8;
132 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX;
133 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32;
136 /// getPointerRegClass - Return the register class to use to hold pointers.
137 /// This is used for addressing modes.
138 const TargetRegisterClass *
139 PPCRegisterInfo::getPointerRegClass(unsigned Kind) const {
140 if (Subtarget.isPPC64())
141 return &PPC::G8RCRegClass;
142 return &PPC::GPRCRegClass;
146 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
147 // 32-bit Darwin calling convention.
148 static const unsigned Darwin32_CalleeSavedRegs[] = {
149 PPC::R13, PPC::R14, PPC::R15,
150 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
151 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
152 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
153 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
155 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
156 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
157 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
158 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
161 PPC::CR2, PPC::CR3, PPC::CR4,
162 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
163 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
164 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
166 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
167 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
168 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
173 // 32-bit SVR4 calling convention.
174 static const unsigned SVR4_CalleeSavedRegs[] = {
176 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
177 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
178 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
179 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
181 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
182 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
183 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
184 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
187 PPC::CR2, PPC::CR3, PPC::CR4,
191 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
192 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
193 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
195 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
196 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
197 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
201 // 64-bit Darwin calling convention.
202 static const unsigned Darwin64_CalleeSavedRegs[] = {
204 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
205 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
206 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
207 PPC::X28, PPC::X29, PPC::X30, PPC::X31,
209 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
210 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
211 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
212 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
215 PPC::CR2, PPC::CR3, PPC::CR4,
216 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
217 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
218 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
220 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
221 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
222 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
227 // 64-bit SVR4 calling convention.
228 static const unsigned SVR4_64_CalleeSavedRegs[] = {
230 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
231 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
232 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
233 PPC::X28, PPC::X29, PPC::X30, PPC::X31,
235 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
236 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
237 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
238 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
241 PPC::CR2, PPC::CR3, PPC::CR4,
245 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
246 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
247 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
249 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
250 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
251 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
256 if (Subtarget.isDarwinABI())
257 return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegs :
258 Darwin32_CalleeSavedRegs;
260 return Subtarget.isPPC64() ? SVR4_64_CalleeSavedRegs : SVR4_CalleeSavedRegs;
263 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
264 BitVector Reserved(getNumRegs());
265 const PPCFrameLowering *PPCFI =
266 static_cast<const PPCFrameLowering*>(MF.getTarget().getFrameLowering());
268 Reserved.set(PPC::R0);
269 Reserved.set(PPC::R1);
270 Reserved.set(PPC::LR);
271 Reserved.set(PPC::LR8);
272 Reserved.set(PPC::RM);
274 // The SVR4 ABI reserves r2 and r13
275 if (Subtarget.isSVR4ABI()) {
276 Reserved.set(PPC::R2); // System-reserved register
277 Reserved.set(PPC::R13); // Small Data Area pointer register
279 // Reserve R2 on Darwin to hack around the problem of save/restore of CR
280 // when the stack frame is too big to address directly; we need two regs.
282 if (Subtarget.isDarwinABI()) {
283 Reserved.set(PPC::R2);
286 // On PPC64, r13 is the thread pointer. Never allocate this register.
287 // Note that this is over conservative, as it also prevents allocation of R31
288 // when the FP is not needed.
289 if (Subtarget.isPPC64()) {
290 Reserved.set(PPC::R13);
291 Reserved.set(PPC::R31);
293 if (!requiresRegisterScavenging(MF))
294 Reserved.set(PPC::R0); // FIXME (64-bit): Remove
296 Reserved.set(PPC::X0);
297 Reserved.set(PPC::X1);
298 Reserved.set(PPC::X13);
299 Reserved.set(PPC::X31);
301 // The 64-bit SVR4 ABI reserves r2 for the TOC pointer.
302 if (Subtarget.isSVR4ABI()) {
303 Reserved.set(PPC::X2);
305 // Reserve R2 on Darwin to hack around the problem of save/restore of CR
306 // when the stack frame is too big to address directly; we need two regs.
308 if (Subtarget.isDarwinABI()) {
309 Reserved.set(PPC::X2);
313 if (PPCFI->needsFP(MF))
314 Reserved.set(PPC::R31);
319 //===----------------------------------------------------------------------===//
320 // Stack Frame Processing methods
321 //===----------------------------------------------------------------------===//
323 void PPCRegisterInfo::
324 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
325 MachineBasicBlock::iterator I) const {
326 if (GuaranteedTailCallOpt && I->getOpcode() == PPC::ADJCALLSTACKUP) {
327 // Add (actually subtract) back the amount the callee popped on return.
328 if (int CalleeAmt = I->getOperand(1).getImm()) {
329 bool is64Bit = Subtarget.isPPC64();
331 unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1;
332 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0;
333 unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI;
334 unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4;
335 unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS;
336 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI;
337 MachineInstr *MI = I;
338 DebugLoc dl = MI->getDebugLoc();
340 if (isInt<16>(CalleeAmt)) {
341 BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg).addReg(StackReg).
344 MachineBasicBlock::iterator MBBI = I;
345 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
346 .addImm(CalleeAmt >> 16);
347 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
348 .addReg(TmpReg, RegState::Kill)
349 .addImm(CalleeAmt & 0xFFFF);
350 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr))
357 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
361 /// findScratchRegister - Find a 'free' PPC register. Try for a call-clobbered
362 /// register first and then a spilled callee-saved register if that fails.
364 unsigned findScratchRegister(MachineBasicBlock::iterator II, RegScavenger *RS,
365 const TargetRegisterClass *RC, int SPAdj) {
366 assert(RS && "Register scavenging must be on");
367 unsigned Reg = RS->FindUnusedReg(RC);
368 // FIXME: move ARM callee-saved reg scan to target independent code, then
369 // search for already spilled CS register here.
371 Reg = RS->scavengeRegister(RC, II, SPAdj);
375 /// lowerDynamicAlloc - Generate the code for allocating an object in the
376 /// current frame. The sequence of code with be in the general form
378 /// addi R0, SP, \#frameSize ; get the address of the previous frame
379 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size
380 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation
382 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II,
383 int SPAdj, RegScavenger *RS) const {
384 // Get the instruction.
385 MachineInstr &MI = *II;
386 // Get the instruction's basic block.
387 MachineBasicBlock &MBB = *MI.getParent();
388 // Get the basic block's function.
389 MachineFunction &MF = *MBB.getParent();
390 // Get the frame info.
391 MachineFrameInfo *MFI = MF.getFrameInfo();
392 // Determine whether 64-bit pointers are used.
393 bool LP64 = Subtarget.isPPC64();
394 DebugLoc dl = MI.getDebugLoc();
396 // Get the maximum call stack size.
397 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
398 // Get the total frame size.
399 unsigned FrameSize = MFI->getStackSize();
401 // Get stack alignments.
402 unsigned TargetAlign = MF.getTarget().getFrameLowering()->getStackAlignment();
403 unsigned MaxAlign = MFI->getMaxAlignment();
404 if (MaxAlign > TargetAlign)
405 report_fatal_error("Dynamic alloca with large aligns not supported");
407 // Determine the previous frame's address. If FrameSize can't be
408 // represented as 16 bits or we need special alignment, then we load the
409 // previous frame's address from 0(SP). Why not do an addis of the hi?
410 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
411 // Constructing the constant and adding would take 3 instructions.
412 // Fortunately, a frame greater than 32K is rare.
413 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
414 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
415 const TargetRegisterClass *RC = LP64 ? G8RC : GPRC;
417 // FIXME (64-bit): Use "findScratchRegister"
419 if (requiresRegisterScavenging(MF))
420 Reg = findScratchRegister(II, RS, RC, SPAdj);
424 if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) {
425 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg)
429 if (requiresRegisterScavenging(MF)) // FIXME (64-bit): Use "true" part.
430 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg)
434 BuildMI(MBB, II, dl, TII.get(PPC::LD), PPC::X0)
438 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg)
443 // Grow the stack and update the stack pointer link, then determine the
444 // address of new allocated space.
446 if (requiresRegisterScavenging(MF)) // FIXME (64-bit): Use "true" part.
447 BuildMI(MBB, II, dl, TII.get(PPC::STDUX))
448 .addReg(Reg, RegState::Kill)
450 .addReg(MI.getOperand(1).getReg());
452 BuildMI(MBB, II, dl, TII.get(PPC::STDUX))
453 .addReg(PPC::X0, RegState::Kill)
455 .addReg(MI.getOperand(1).getReg());
457 if (!MI.getOperand(1).isKill())
458 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
460 .addImm(maxCallFrameSize);
462 // Implicitly kill the register.
463 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
465 .addImm(maxCallFrameSize)
466 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill);
468 BuildMI(MBB, II, dl, TII.get(PPC::STWUX))
469 .addReg(Reg, RegState::Kill)
471 .addReg(MI.getOperand(1).getReg());
473 if (!MI.getOperand(1).isKill())
474 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
476 .addImm(maxCallFrameSize);
478 // Implicitly kill the register.
479 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
481 .addImm(maxCallFrameSize)
482 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill);
485 // Discard the DYNALLOC instruction.
489 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of
490 /// reserving a whole register (R0), we scrounge for one here. This generates
493 /// mfcr rA ; Move the conditional register into GPR rA.
494 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot.
495 /// stw rA, FI ; Store rA to the frame.
497 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II,
498 unsigned FrameIndex, int SPAdj,
499 RegScavenger *RS) const {
500 // Get the instruction.
501 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>, <FI>
502 // Get the instruction's basic block.
503 MachineBasicBlock &MBB = *MI.getParent();
504 DebugLoc dl = MI.getDebugLoc();
506 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
507 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
508 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC;
509 unsigned Reg = findScratchRegister(II, RS, RC, SPAdj);
510 unsigned SrcReg = MI.getOperand(0).getReg();
511 bool LP64 = Subtarget.isPPC64();
513 // We need to store the CR in the low 4-bits of the saved value. First, issue
514 // an MFCRpsued to save all of the CRBits and, if needed, kill the SrcReg.
515 BuildMI(MBB, II, dl, TII.get(PPC::MFCRpseud), Reg)
516 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
518 // If the saved register wasn't CR0, shift the bits left so that they are in
520 if (SrcReg != PPC::CR0)
521 // rlwinm rA, rA, ShiftBits, 0, 31.
522 BuildMI(MBB, II, dl, TII.get(PPC::RLWINM), Reg)
523 .addReg(Reg, RegState::Kill)
524 .addImm(PPCRegisterInfo::getRegisterNumbering(SrcReg) * 4)
528 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW))
529 .addReg(Reg, getKillRegState(MI.getOperand(1).getImm())),
532 // Discard the pseudo instruction.
537 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
538 int SPAdj, RegScavenger *RS) const {
539 assert(SPAdj == 0 && "Unexpected");
541 // Get the instruction.
542 MachineInstr &MI = *II;
543 // Get the instruction's basic block.
544 MachineBasicBlock &MBB = *MI.getParent();
545 // Get the basic block's function.
546 MachineFunction &MF = *MBB.getParent();
547 // Get the frame info.
548 MachineFrameInfo *MFI = MF.getFrameInfo();
549 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
550 DebugLoc dl = MI.getDebugLoc();
552 // Find out which operand is the frame index.
553 unsigned FIOperandNo = 0;
554 while (!MI.getOperand(FIOperandNo).isFI()) {
556 assert(FIOperandNo != MI.getNumOperands() &&
557 "Instr doesn't have FrameIndex operand!");
559 // Take into account whether it's an add or mem instruction
560 unsigned OffsetOperandNo = (FIOperandNo == 2) ? 1 : 2;
561 if (MI.isInlineAsm())
562 OffsetOperandNo = FIOperandNo-1;
564 // Get the frame index.
565 int FrameIndex = MI.getOperand(FIOperandNo).getIndex();
567 // Get the frame pointer save index. Users of this index are primarily
568 // DYNALLOC instructions.
569 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
570 int FPSI = FI->getFramePointerSaveIndex();
571 // Get the instruction opcode.
572 unsigned OpC = MI.getOpcode();
574 // Special case for dynamic alloca.
575 if (FPSI && FrameIndex == FPSI &&
576 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
577 lowerDynamicAlloc(II, SPAdj, RS);
581 // Special case for pseudo-op SPILL_CR.
582 if (requiresRegisterScavenging(MF)) // FIXME (64-bit): Enable by default.
583 if (OpC == PPC::SPILL_CR) {
584 lowerCRSpilling(II, FrameIndex, SPAdj, RS);
588 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
589 MI.getOperand(FIOperandNo).ChangeToRegister(TFI->hasFP(MF) ?
593 // Figure out if the offset in the instruction is shifted right two bits. This
594 // is true for instructions like "STD", which the machine implicitly adds two
596 bool isIXAddr = false;
606 // Now add the frame object offset to the offset from r1.
607 int Offset = MFI->getObjectOffset(FrameIndex);
609 Offset += MI.getOperand(OffsetOperandNo).getImm();
611 Offset += MI.getOperand(OffsetOperandNo).getImm() << 2;
613 // If we're not using a Frame Pointer that has been set to the value of the
614 // SP before having the stack size subtracted from it, then add the stack size
615 // to Offset to get the correct offset.
616 // Naked functions have stack size 0, although getStackSize may not reflect that
617 // because we didn't call all the pieces that compute it for naked functions.
618 if (!MF.getFunction()->hasFnAttr(Attribute::Naked))
619 Offset += MFI->getStackSize();
621 // If we can, encode the offset directly into the instruction. If this is a
622 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If
623 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits
624 // clear can be encoded. This is extremely uncommon, because normally you
625 // only "std" to a stack slot that is at least 4-byte aligned, but it can
626 // happen in invalid code.
627 if (isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0)) {
629 Offset >>= 2; // The actual encoded value has the low two bits zero.
630 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
634 // The offset doesn't fit into a single register, scavenge one to build the
636 // FIXME: figure out what SPAdj is doing here.
638 // FIXME (64-bit): Use "findScratchRegister".
640 if (requiresRegisterScavenging(MF))
641 SReg = findScratchRegister(II, RS, &PPC::GPRCRegClass, SPAdj);
645 // Insert a set of rA with the full offset value before the ld, st, or add
646 BuildMI(MBB, II, dl, TII.get(PPC::LIS), SReg)
647 .addImm(Offset >> 16);
648 BuildMI(MBB, II, dl, TII.get(PPC::ORI), SReg)
649 .addReg(SReg, RegState::Kill)
652 // Convert into indexed form of the instruction:
654 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
655 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
656 unsigned OperandBase;
658 if (OpC != TargetOpcode::INLINEASM) {
659 assert(ImmToIdxMap.count(OpC) &&
660 "No indexed form of load or store available!");
661 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second;
662 MI.setDesc(TII.get(NewOpcode));
665 OperandBase = OffsetOperandNo;
668 unsigned StackReg = MI.getOperand(FIOperandNo).getReg();
669 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false);
670 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false);
673 unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
674 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
676 if (!Subtarget.isPPC64())
677 return TFI->hasFP(MF) ? PPC::R31 : PPC::R1;
679 return TFI->hasFP(MF) ? PPC::X31 : PPC::X1;
682 unsigned PPCRegisterInfo::getEHExceptionRegister() const {
683 return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3;
686 unsigned PPCRegisterInfo::getEHHandlerRegister() const {
687 return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4;