1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "reginfo"
16 #include "PPCInstrBuilder.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "PPCRegisterInfo.h"
19 #include "PPCFrameInfo.h"
20 #include "PPCSubtarget.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Type.h"
23 #include "llvm/CodeGen/ValueTypes.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineModuleInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineLocation.h"
29 #include "llvm/CodeGen/SelectionDAGNodes.h"
30 #include "llvm/Target/TargetFrameInfo.h"
31 #include "llvm/Target/TargetInstrInfo.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Target/TargetOptions.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/ADT/BitVector.h"
38 #include "llvm/ADT/STLExtras.h"
42 /// getRegisterNumbering - Given the enum value for some register, e.g.
43 /// PPC::F14, return the number that it corresponds to (e.g. 14).
44 unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
47 case R0 : case X0 : case F0 : case V0 : case CR0: return 0;
48 case R1 : case X1 : case F1 : case V1 : case CR1: return 1;
49 case R2 : case X2 : case F2 : case V2 : case CR2: return 2;
50 case R3 : case X3 : case F3 : case V3 : case CR3: return 3;
51 case R4 : case X4 : case F4 : case V4 : case CR4: return 4;
52 case R5 : case X5 : case F5 : case V5 : case CR5: return 5;
53 case R6 : case X6 : case F6 : case V6 : case CR6: return 6;
54 case R7 : case X7 : case F7 : case V7 : case CR7: return 7;
55 case R8 : case X8 : case F8 : case V8 : return 8;
56 case R9 : case X9 : case F9 : case V9 : return 9;
57 case R10: case X10: case F10: case V10: return 10;
58 case R11: case X11: case F11: case V11: return 11;
59 case R12: case X12: case F12: case V12: return 12;
60 case R13: case X13: case F13: case V13: return 13;
61 case R14: case X14: case F14: case V14: return 14;
62 case R15: case X15: case F15: case V15: return 15;
63 case R16: case X16: case F16: case V16: return 16;
64 case R17: case X17: case F17: case V17: return 17;
65 case R18: case X18: case F18: case V18: return 18;
66 case R19: case X19: case F19: case V19: return 19;
67 case R20: case X20: case F20: case V20: return 20;
68 case R21: case X21: case F21: case V21: return 21;
69 case R22: case X22: case F22: case V22: return 22;
70 case R23: case X23: case F23: case V23: return 23;
71 case R24: case X24: case F24: case V24: return 24;
72 case R25: case X25: case F25: case V25: return 25;
73 case R26: case X26: case F26: case V26: return 26;
74 case R27: case X27: case F27: case V27: return 27;
75 case R28: case X28: case F28: case V28: return 28;
76 case R29: case X29: case F29: case V29: return 29;
77 case R30: case X30: case F30: case V30: return 30;
78 case R31: case X31: case F31: case V31: return 31;
80 cerr << "Unhandled reg in PPCRegisterInfo::getRegisterNumbering!\n";
85 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST,
86 const TargetInstrInfo &tii)
87 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
88 Subtarget(ST), TII(tii) {
89 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
90 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
91 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
92 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
93 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
94 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
95 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
96 ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
99 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8;
100 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8;
101 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8;
102 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX;
103 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32;
106 static void StoreRegToStackSlot(const TargetInstrInfo &TII,
107 unsigned SrcReg, int FrameIdx,
108 const TargetRegisterClass *RC,
109 SmallVectorImpl<MachineInstr*> &NewMIs) {
110 if (RC == PPC::GPRCRegisterClass) {
111 if (SrcReg != PPC::LR) {
112 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STW))
113 .addReg(SrcReg, false, false, true), FrameIdx));
115 // FIXME: this spills LR immediately to memory in one step. To do this,
116 // we use R11, which we know cannot be used in the prolog/epilog. This is
118 NewMIs.push_back(BuildMI(TII.get(PPC::MFLR), PPC::R11));
119 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STW))
120 .addReg(PPC::R11, false, false, true), FrameIdx));
122 } else if (RC == PPC::G8RCRegisterClass) {
123 if (SrcReg != PPC::LR8) {
124 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STD))
125 .addReg(SrcReg, false, false, true), FrameIdx));
127 // FIXME: this spills LR immediately to memory in one step. To do this,
128 // we use R11, which we know cannot be used in the prolog/epilog. This is
130 NewMIs.push_back(BuildMI(TII.get(PPC::MFLR8), PPC::X11));
131 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STD))
132 .addReg(PPC::X11, false, false, true), FrameIdx));
134 } else if (RC == PPC::F8RCRegisterClass) {
135 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STFD))
136 .addReg(SrcReg, false, false, true), FrameIdx));
137 } else if (RC == PPC::F4RCRegisterClass) {
138 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STFS))
139 .addReg(SrcReg, false, false, true), FrameIdx));
140 } else if (RC == PPC::CRRCRegisterClass) {
141 // FIXME: We use R0 here, because it isn't available for RA.
142 // We need to store the CR in the low 4-bits of the saved value. First,
143 // issue a MFCR to save all of the CRBits.
144 NewMIs.push_back(BuildMI(TII.get(PPC::MFCR), PPC::R0));
146 // If the saved register wasn't CR0, shift the bits left so that they are in
148 if (SrcReg != PPC::CR0) {
149 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4;
150 // rlwinm r0, r0, ShiftBits, 0, 31.
151 NewMIs.push_back(BuildMI(TII.get(PPC::RLWINM), PPC::R0)
152 .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31));
155 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STW))
156 .addReg(PPC::R0, false, false, true), FrameIdx));
157 } else if (RC == PPC::VRRCRegisterClass) {
158 // We don't have indexed addressing for vector loads. Emit:
162 // FIXME: We use R0 here, because it isn't available for RA.
163 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::ADDI), PPC::R0),
165 NewMIs.push_back(BuildMI(TII.get(PPC::STVX))
166 .addReg(SrcReg, false, false, true).addReg(PPC::R0).addReg(PPC::R0));
168 assert(0 && "Unknown regclass!");
174 PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
175 MachineBasicBlock::iterator MI,
176 unsigned SrcReg, int FrameIdx,
177 const TargetRegisterClass *RC) const {
178 SmallVector<MachineInstr*, 4> NewMIs;
179 StoreRegToStackSlot(TII, SrcReg, FrameIdx, RC, NewMIs);
180 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
181 MBB.insert(MI, NewMIs[i]);
184 void PPCRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
185 SmallVectorImpl<MachineOperand> &Addr,
186 const TargetRegisterClass *RC,
187 SmallVectorImpl<MachineInstr*> &NewMIs) const {
188 if (Addr[0].isFrameIndex()) {
189 StoreRegToStackSlot(TII, SrcReg, Addr[0].getFrameIndex(), RC, NewMIs);
194 if (RC == PPC::GPRCRegisterClass) {
196 } else if (RC == PPC::G8RCRegisterClass) {
198 } else if (RC == PPC::F8RCRegisterClass) {
200 } else if (RC == PPC::F4RCRegisterClass) {
202 } else if (RC == PPC::VRRCRegisterClass) {
205 assert(0 && "Unknown regclass!");
208 MachineInstrBuilder MIB = BuildMI(TII.get(Opc))
209 .addReg(SrcReg, false, false, true);
210 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
211 MachineOperand &MO = Addr[i];
213 MIB.addReg(MO.getReg());
214 else if (MO.isImmediate())
215 MIB.addImm(MO.getImmedValue());
217 MIB.addFrameIndex(MO.getFrameIndex());
219 NewMIs.push_back(MIB);
223 static void LoadRegFromStackSlot(const TargetInstrInfo &TII,
224 unsigned DestReg, int FrameIdx,
225 const TargetRegisterClass *RC,
226 SmallVectorImpl<MachineInstr*> &NewMIs) {
227 if (RC == PPC::GPRCRegisterClass) {
228 if (DestReg != PPC::LR) {
229 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LWZ), DestReg),
232 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LWZ), PPC::R11),
234 NewMIs.push_back(BuildMI(TII.get(PPC::MTLR)).addReg(PPC::R11));
236 } else if (RC == PPC::G8RCRegisterClass) {
237 if (DestReg != PPC::LR8) {
238 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LD), DestReg),
241 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LD), PPC::R11),
243 NewMIs.push_back(BuildMI(TII.get(PPC::MTLR8)).addReg(PPC::R11));
245 } else if (RC == PPC::F8RCRegisterClass) {
246 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LFD), DestReg),
248 } else if (RC == PPC::F4RCRegisterClass) {
249 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LFS), DestReg),
251 } else if (RC == PPC::CRRCRegisterClass) {
252 // FIXME: We use R0 here, because it isn't available for RA.
253 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LWZ), PPC::R0),
256 // If the reloaded register isn't CR0, shift the bits right so that they are
257 // in the right CR's slot.
258 if (DestReg != PPC::CR0) {
259 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4;
260 // rlwinm r11, r11, 32-ShiftBits, 0, 31.
261 NewMIs.push_back(BuildMI(TII.get(PPC::RLWINM), PPC::R0)
262 .addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31));
265 NewMIs.push_back(BuildMI(TII.get(PPC::MTCRF), DestReg).addReg(PPC::R0));
266 } else if (RC == PPC::VRRCRegisterClass) {
267 // We don't have indexed addressing for vector loads. Emit:
271 // FIXME: We use R0 here, because it isn't available for RA.
272 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::ADDI), PPC::R0),
274 NewMIs.push_back(BuildMI(TII.get(PPC::LVX),DestReg).addReg(PPC::R0)
277 assert(0 && "Unknown regclass!");
283 PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
284 MachineBasicBlock::iterator MI,
285 unsigned DestReg, int FrameIdx,
286 const TargetRegisterClass *RC) const {
287 SmallVector<MachineInstr*, 4> NewMIs;
288 LoadRegFromStackSlot(TII, DestReg, FrameIdx, RC, NewMIs);
289 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
290 MBB.insert(MI, NewMIs[i]);
293 void PPCRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
294 SmallVectorImpl<MachineOperand> &Addr,
295 const TargetRegisterClass *RC,
296 SmallVectorImpl<MachineInstr*> &NewMIs) const {
297 if (Addr[0].isFrameIndex()) {
298 LoadRegFromStackSlot(TII, DestReg, Addr[0].getFrameIndex(), RC, NewMIs);
303 if (RC == PPC::GPRCRegisterClass) {
304 assert(DestReg != PPC::LR && "Can't handle this yet!");
306 } else if (RC == PPC::G8RCRegisterClass) {
307 assert(DestReg != PPC::LR8 && "Can't handle this yet!");
309 } else if (RC == PPC::F8RCRegisterClass) {
311 } else if (RC == PPC::F4RCRegisterClass) {
313 } else if (RC == PPC::VRRCRegisterClass) {
316 assert(0 && "Unknown regclass!");
319 MachineInstrBuilder MIB = BuildMI(TII.get(Opc), DestReg);
320 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
321 MachineOperand &MO = Addr[i];
323 MIB.addReg(MO.getReg());
324 else if (MO.isImmediate())
325 MIB.addImm(MO.getImmedValue());
327 MIB.addFrameIndex(MO.getFrameIndex());
329 NewMIs.push_back(MIB);
333 void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
334 MachineBasicBlock::iterator MI,
335 unsigned DestReg, unsigned SrcReg,
336 const TargetRegisterClass *DestRC,
337 const TargetRegisterClass *SrcRC) const {
338 if (DestRC != SrcRC) {
339 cerr << "Not yet supported!";
343 if (DestRC == PPC::GPRCRegisterClass) {
344 BuildMI(MBB, MI, TII.get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg);
345 } else if (DestRC == PPC::G8RCRegisterClass) {
346 BuildMI(MBB, MI, TII.get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg);
347 } else if (DestRC == PPC::F4RCRegisterClass) {
348 BuildMI(MBB, MI, TII.get(PPC::FMRS), DestReg).addReg(SrcReg);
349 } else if (DestRC == PPC::F8RCRegisterClass) {
350 BuildMI(MBB, MI, TII.get(PPC::FMRD), DestReg).addReg(SrcReg);
351 } else if (DestRC == PPC::CRRCRegisterClass) {
352 BuildMI(MBB, MI, TII.get(PPC::MCRF), DestReg).addReg(SrcReg);
353 } else if (DestRC == PPC::VRRCRegisterClass) {
354 BuildMI(MBB, MI, TII.get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg);
356 cerr << "Attempt to copy register that is not GPR or FPR";
361 void PPCRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
362 MachineBasicBlock::iterator I,
364 const MachineInstr *Orig) const {
365 MachineInstr *MI = Orig->clone();
366 MI->getOperand(0).setReg(DestReg);
371 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
372 // 32-bit Darwin calling convention.
373 static const unsigned Macho32_CalleeSavedRegs[] = {
374 PPC::R13, PPC::R14, PPC::R15,
375 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
376 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
377 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
378 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
380 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
381 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
382 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
383 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
386 PPC::CR2, PPC::CR3, PPC::CR4,
387 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
388 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
389 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
394 static const unsigned ELF32_CalleeSavedRegs[] = {
395 PPC::R13, PPC::R14, PPC::R15,
396 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
397 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
398 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
399 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
402 PPC::F10, PPC::F11, PPC::F12, PPC::F13,
403 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
404 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
405 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
406 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
409 PPC::CR2, PPC::CR3, PPC::CR4,
410 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
411 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
412 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
416 // 64-bit Darwin calling convention.
417 static const unsigned Macho64_CalleeSavedRegs[] = {
419 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
420 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
421 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
422 PPC::X28, PPC::X29, PPC::X30, PPC::X31,
424 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
425 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
426 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
427 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
430 PPC::CR2, PPC::CR3, PPC::CR4,
431 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
432 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
433 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
438 if (Subtarget.isMachoABI())
439 return Subtarget.isPPC64() ? Macho64_CalleeSavedRegs :
440 Macho32_CalleeSavedRegs;
443 return ELF32_CalleeSavedRegs;
446 const TargetRegisterClass* const*
447 PPCRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
448 // 32-bit Macho calling convention.
449 static const TargetRegisterClass * const Macho32_CalleeSavedRegClasses[] = {
450 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
451 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
452 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
453 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
454 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
456 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
457 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
458 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
459 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
460 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
462 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
464 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
465 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
466 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
468 &PPC::GPRCRegClass, 0
471 static const TargetRegisterClass * const ELF32_CalleeSavedRegClasses[] = {
472 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
473 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
474 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
475 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
476 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
479 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
480 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
481 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
482 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
483 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
484 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
486 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
488 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
489 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
490 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
492 &PPC::GPRCRegClass, 0
495 // 64-bit Macho calling convention.
496 static const TargetRegisterClass * const Macho64_CalleeSavedRegClasses[] = {
497 &PPC::G8RCRegClass,&PPC::G8RCRegClass,
498 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
499 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
500 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
501 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
503 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
504 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
505 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
506 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
507 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
509 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
511 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
512 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
513 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
515 &PPC::G8RCRegClass, 0
518 if (Subtarget.isMachoABI())
519 return Subtarget.isPPC64() ? Macho64_CalleeSavedRegClasses :
520 Macho32_CalleeSavedRegClasses;
523 return ELF32_CalleeSavedRegClasses;
526 // needsFP - Return true if the specified function should have a dedicated frame
527 // pointer register. This is true if the function has variable sized allocas or
528 // if frame pointer elimination is disabled.
530 static bool needsFP(const MachineFunction &MF) {
531 const MachineFrameInfo *MFI = MF.getFrameInfo();
532 return NoFramePointerElim || MFI->hasVarSizedObjects();
535 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
536 BitVector Reserved(getNumRegs());
537 Reserved.set(PPC::R0);
538 Reserved.set(PPC::R1);
539 Reserved.set(PPC::LR);
540 // In Linux, r2 is reserved for the OS.
541 if (!Subtarget.isDarwin())
542 Reserved.set(PPC::R2);
543 // On PPC64, r13 is the thread pointer. Never allocate this register.
544 // Note that this is overconservative, as it also prevents allocation of
545 // R31 when the FP is not needed.
546 if (Subtarget.isPPC64()) {
547 Reserved.set(PPC::R13);
548 Reserved.set(PPC::R31);
551 Reserved.set(PPC::R31);
555 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
556 /// copy instructions, turning them into load/store instructions.
557 MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI,
559 int FrameIndex) const {
560 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
561 // it takes more than one instruction to store it.
562 unsigned Opc = MI->getOpcode();
564 MachineInstr *NewMI = NULL;
565 if ((Opc == PPC::OR &&
566 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
567 if (OpNum == 0) { // move -> store
568 unsigned InReg = MI->getOperand(1).getReg();
569 NewMI = addFrameReference(BuildMI(TII.get(PPC::STW)).addReg(InReg),
571 } else { // move -> load
572 unsigned OutReg = MI->getOperand(0).getReg();
573 NewMI = addFrameReference(BuildMI(TII.get(PPC::LWZ), OutReg),
576 } else if ((Opc == PPC::OR8 &&
577 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
578 if (OpNum == 0) { // move -> store
579 unsigned InReg = MI->getOperand(1).getReg();
580 NewMI = addFrameReference(BuildMI(TII.get(PPC::STD)).addReg(InReg),
582 } else { // move -> load
583 unsigned OutReg = MI->getOperand(0).getReg();
584 NewMI = addFrameReference(BuildMI(TII.get(PPC::LD), OutReg), FrameIndex);
586 } else if (Opc == PPC::FMRD) {
587 if (OpNum == 0) { // move -> store
588 unsigned InReg = MI->getOperand(1).getReg();
589 NewMI = addFrameReference(BuildMI(TII.get(PPC::STFD)).addReg(InReg),
591 } else { // move -> load
592 unsigned OutReg = MI->getOperand(0).getReg();
593 NewMI = addFrameReference(BuildMI(TII.get(PPC::LFD), OutReg), FrameIndex);
595 } else if (Opc == PPC::FMRS) {
596 if (OpNum == 0) { // move -> store
597 unsigned InReg = MI->getOperand(1).getReg();
598 NewMI = addFrameReference(BuildMI(TII.get(PPC::STFS)).addReg(InReg),
600 } else { // move -> load
601 unsigned OutReg = MI->getOperand(0).getReg();
602 NewMI = addFrameReference(BuildMI(TII.get(PPC::LFS), OutReg), FrameIndex);
607 NewMI->copyKillDeadInfo(MI);
611 //===----------------------------------------------------------------------===//
612 // Stack Frame Processing methods
613 //===----------------------------------------------------------------------===//
615 // hasFP - Return true if the specified function actually has a dedicated frame
616 // pointer register. This is true if the function needs a frame pointer and has
617 // a non-zero stack size.
618 bool PPCRegisterInfo::hasFP(const MachineFunction &MF) const {
619 const MachineFrameInfo *MFI = MF.getFrameInfo();
620 return MFI->getStackSize() && needsFP(MF);
623 /// usesLR - Returns if the link registers (LR) has been used in the function.
625 bool PPCRegisterInfo::usesLR(MachineFunction &MF) const {
626 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
630 void PPCRegisterInfo::
631 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
632 MachineBasicBlock::iterator I) const {
633 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
637 /// LowerDynamicAlloc - Generate the code for allocating an object in the
638 /// current frame. The sequence of code with be in the general form
640 /// addi R0, SP, #frameSize ; get the address of the previous frame
641 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size
642 /// addi Rnew, SP, #maxCalFrameSize ; get the top of the allocation
644 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const {
645 // Get the instruction.
646 MachineInstr &MI = *II;
647 // Get the instruction's basic block.
648 MachineBasicBlock &MBB = *MI.getParent();
649 // Get the basic block's function.
650 MachineFunction &MF = *MBB.getParent();
651 // Get the frame info.
652 MachineFrameInfo *MFI = MF.getFrameInfo();
653 // Determine whether 64-bit pointers are used.
654 bool LP64 = Subtarget.isPPC64();
656 // Get the maximum call stack size.
657 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
658 // Get the total frame size.
659 unsigned FrameSize = MFI->getStackSize();
661 // Get stack alignments.
662 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
663 unsigned MaxAlign = MFI->getMaxAlignment();
664 assert(MaxAlign <= TargetAlign &&
665 "Dynamic alloca with large aligns not supported");
667 // Determine the previous frame's address. If FrameSize can't be
668 // represented as 16 bits or we need special alignment, then we load the
669 // previous frame's address from 0(SP). Why not do an addis of the hi?
670 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
671 // Constructing the constant and adding would take 3 instructions.
672 // Fortunately, a frame greater than 32K is rare.
673 if (MaxAlign < TargetAlign && isInt16(FrameSize)) {
674 BuildMI(MBB, II, TII.get(PPC::ADDI), PPC::R0)
678 BuildMI(MBB, II, TII.get(PPC::LD), PPC::X0)
682 BuildMI(MBB, II, TII.get(PPC::LWZ), PPC::R0)
687 // Grow the stack and update the stack pointer link, then
688 // determine the address of new allocated space.
690 BuildMI(MBB, II, TII.get(PPC::STDUX))
693 .addReg(MI.getOperand(1).getReg());
694 BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
696 .addImm(maxCallFrameSize);
698 BuildMI(MBB, II, TII.get(PPC::STWUX))
701 .addReg(MI.getOperand(1).getReg());
702 BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
704 .addImm(maxCallFrameSize);
707 // Discard the DYNALLOC instruction.
711 void PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
712 int SPAdj, RegScavenger *RS) const {
713 assert(SPAdj == 0 && "Unexpected");
715 // Get the instruction.
716 MachineInstr &MI = *II;
717 // Get the instruction's basic block.
718 MachineBasicBlock &MBB = *MI.getParent();
719 // Get the basic block's function.
720 MachineFunction &MF = *MBB.getParent();
721 // Get the frame info.
722 MachineFrameInfo *MFI = MF.getFrameInfo();
724 // Find out which operand is the frame index.
725 unsigned FIOperandNo = 0;
726 while (!MI.getOperand(FIOperandNo).isFrameIndex()) {
728 assert(FIOperandNo != MI.getNumOperands() &&
729 "Instr doesn't have FrameIndex operand!");
731 // Take into account whether it's an add or mem instruction
732 unsigned OffsetOperandNo = (FIOperandNo == 2) ? 1 : 2;
733 if (MI.getOpcode() == TargetInstrInfo::INLINEASM)
734 OffsetOperandNo = FIOperandNo-1;
736 // Get the frame index.
737 int FrameIndex = MI.getOperand(FIOperandNo).getFrameIndex();
739 // Get the frame pointer save index. Users of this index are primarily
740 // DYNALLOC instructions.
741 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
742 int FPSI = FI->getFramePointerSaveIndex();
743 // Get the instruction opcode.
744 unsigned OpC = MI.getOpcode();
746 // Special case for dynamic alloca.
747 if (FPSI && FrameIndex == FPSI &&
748 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
749 lowerDynamicAlloc(II);
753 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
754 MI.getOperand(FIOperandNo).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1,
757 // Figure out if the offset in the instruction is shifted right two bits. This
758 // is true for instructions like "STD", which the machine implicitly adds two
760 bool isIXAddr = false;
770 // Now add the frame object offset to the offset from r1.
771 int Offset = MFI->getObjectOffset(FrameIndex);
773 Offset += MI.getOperand(OffsetOperandNo).getImmedValue();
775 Offset += MI.getOperand(OffsetOperandNo).getImmedValue() << 2;
777 // If we're not using a Frame Pointer that has been set to the value of the
778 // SP before having the stack size subtracted from it, then add the stack size
779 // to Offset to get the correct offset.
780 Offset += MFI->getStackSize();
782 if (isInt16(Offset)) {
784 assert((Offset & 3) == 0 && "Invalid frame offset!");
785 Offset >>= 2; // The actual encoded value has the low two bits zero.
787 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
789 // Insert a set of r0 with the full offset value before the ld, st, or add
790 BuildMI(MBB, II, TII.get(PPC::LIS), PPC::R0).addImm(Offset >> 16);
791 BuildMI(MBB, II, TII.get(PPC::ORI), PPC::R0).addReg(PPC::R0).addImm(Offset);
793 // Convert into indexed form of the instruction
794 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
795 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
796 unsigned OperandBase;
797 if (OpC != TargetInstrInfo::INLINEASM) {
798 assert(ImmToIdxMap.count(OpC) &&
799 "No indexed form of load or store available!");
800 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second;
801 MI.setInstrDescriptor(TII.get(NewOpcode));
804 OperandBase = OffsetOperandNo;
807 unsigned StackReg = MI.getOperand(FIOperandNo).getReg();
808 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false);
809 MI.getOperand(OperandBase+1).ChangeToRegister(PPC::R0, false);
813 /// VRRegNo - Map from a numbered VR register to its enum value.
815 static const unsigned short VRRegNo[] = {
816 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
817 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
818 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
819 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
822 /// RemoveVRSaveCode - We have found that this function does not need any code
823 /// to manipulate the VRSAVE register, even though it uses vector registers.
824 /// This can happen when the only registers used are known to be live in or out
825 /// of the function. Remove all of the VRSAVE related code from the function.
826 static void RemoveVRSaveCode(MachineInstr *MI) {
827 MachineBasicBlock *Entry = MI->getParent();
828 MachineFunction *MF = Entry->getParent();
830 // We know that the MTVRSAVE instruction immediately follows MI. Remove it.
831 MachineBasicBlock::iterator MBBI = MI;
833 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
834 MBBI->eraseFromParent();
836 bool RemovedAllMTVRSAVEs = true;
837 // See if we can find and remove the MTVRSAVE instruction from all of the
839 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
840 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
841 // If last instruction is a return instruction, add an epilogue
842 if (!I->empty() && TII.isReturn(I->back().getOpcode())) {
843 bool FoundIt = false;
844 for (MBBI = I->end(); MBBI != I->begin(); ) {
846 if (MBBI->getOpcode() == PPC::MTVRSAVE) {
847 MBBI->eraseFromParent(); // remove it.
852 RemovedAllMTVRSAVEs &= FoundIt;
856 // If we found and removed all MTVRSAVE instructions, remove the read of
858 if (RemovedAllMTVRSAVEs) {
860 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
862 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
863 MBBI->eraseFromParent();
866 // Finally, nuke the UPDATE_VRSAVE.
867 MI->eraseFromParent();
870 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
871 // instruction selector. Based on the vector registers that have been used,
872 // transform this into the appropriate ORI instruction.
873 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) {
874 MachineFunction *MF = MI->getParent()->getParent();
876 unsigned UsedRegMask = 0;
877 for (unsigned i = 0; i != 32; ++i)
878 if (MF->isPhysRegUsed(VRRegNo[i]))
879 UsedRegMask |= 1 << (31-i);
881 // Live in and live out values already must be in the mask, so don't bother
883 for (MachineFunction::livein_iterator I =
884 MF->livein_begin(), E = MF->livein_end(); I != E; ++I) {
885 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first);
886 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg.
887 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
889 for (MachineFunction::liveout_iterator I =
890 MF->liveout_begin(), E = MF->liveout_end(); I != E; ++I) {
891 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I);
892 if (VRRegNo[RegNo] == *I) // If this really is a vector reg.
893 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
896 unsigned SrcReg = MI->getOperand(1).getReg();
897 unsigned DstReg = MI->getOperand(0).getReg();
898 // If no registers are used, turn this into a copy.
899 if (UsedRegMask == 0) {
900 // Remove all VRSAVE code.
901 RemoveVRSaveCode(MI);
903 } else if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
904 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg)
905 .addReg(SrcReg).addImm(UsedRegMask);
906 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
907 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
908 .addReg(SrcReg).addImm(UsedRegMask >> 16);
910 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
911 .addReg(SrcReg).addImm(UsedRegMask >> 16);
912 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg)
913 .addReg(DstReg).addImm(UsedRegMask & 0xFFFF);
916 // Remove the old UPDATE_VRSAVE instruction.
917 MI->eraseFromParent();
920 /// determineFrameLayout - Determine the size of the frame and maximum call
922 void PPCRegisterInfo::determineFrameLayout(MachineFunction &MF) const {
923 MachineFrameInfo *MFI = MF.getFrameInfo();
925 // Get the number of bytes to allocate from the FrameInfo
926 unsigned FrameSize = MFI->getStackSize();
928 // Get the alignments provided by the target, and the maximum alignment
929 // (if any) of the fixed frame objects.
930 unsigned MaxAlign = MFI->getMaxAlignment();
931 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
932 unsigned AlignMask = TargetAlign - 1; //
934 // If we are a leaf function, and use up to 224 bytes of stack space,
935 // don't have a frame pointer, calls, or dynamic alloca then we do not need
936 // to adjust the stack pointer (we fit in the Red Zone).
937 if (FrameSize <= 224 && // Fits in red zone.
938 !MFI->hasVarSizedObjects() && // No dynamic alloca.
939 !MFI->hasCalls() && // No calls.
940 MaxAlign <= TargetAlign) { // No special alignment.
942 MFI->setStackSize(0);
946 // Get the maximum call frame size of all the calls.
947 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
949 // Maximum call frame needs to be at least big enough for linkage and 8 args.
950 unsigned minCallFrameSize =
951 PPCFrameInfo::getMinCallFrameSize(Subtarget.isPPC64(),
952 Subtarget.isMachoABI());
953 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
955 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
956 // that allocations will be aligned.
957 if (MFI->hasVarSizedObjects())
958 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
960 // Update maximum call frame size.
961 MFI->setMaxCallFrameSize(maxCallFrameSize);
963 // Include call frame size in total.
964 FrameSize += maxCallFrameSize;
966 // Make sure the frame is aligned.
967 FrameSize = (FrameSize + AlignMask) & ~AlignMask;
969 // Update frame info.
970 MFI->setStackSize(FrameSize);
973 void PPCRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
976 // Save and clear the LR state.
977 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
978 unsigned LR = getRARegister();
979 FI->setUsesLR(MF.isPhysRegUsed(LR));
980 MF.setPhysRegUnused(LR);
982 // Save R31 if necessary
983 int FPSI = FI->getFramePointerSaveIndex();
984 bool IsPPC64 = Subtarget.isPPC64();
985 bool IsELF32_ABI = Subtarget.isELF32_ABI();
986 bool IsMachoABI = Subtarget.isMachoABI();
987 const MachineFrameInfo *MFI = MF.getFrameInfo();
989 // If the frame pointer save index hasn't been defined yet.
990 if (!FPSI && (NoFramePointerElim || MFI->hasVarSizedObjects())
992 // Find out what the fix offset of the frame pointer save area.
993 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64,
995 // Allocate the frame index for frame pointer save area.
996 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset);
998 FI->setFramePointerSaveIndex(FPSI);
1003 void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
1004 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
1005 MachineBasicBlock::iterator MBBI = MBB.begin();
1006 MachineFrameInfo *MFI = MF.getFrameInfo();
1007 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
1009 // Prepare for frame info.
1010 unsigned FrameLabelId = 0;
1012 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
1014 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
1015 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
1016 HandleVRSaveUpdate(MBBI, TII);
1021 // Move MBBI back to the beginning of the function.
1024 // Work out frame sizes.
1025 determineFrameLayout(MF);
1026 unsigned FrameSize = MFI->getStackSize();
1028 int NegFrameSize = -FrameSize;
1030 // Get processor type.
1031 bool IsPPC64 = Subtarget.isPPC64();
1032 // Get operating system
1033 bool IsMachoABI = Subtarget.isMachoABI();
1034 // Check if the link register (LR) has been used.
1035 bool UsesLR = MFI->hasCalls() || usesLR(MF);
1036 // Do we have a frame pointer for this function?
1037 bool HasFP = hasFP(MF) && FrameSize;
1039 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI);
1040 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI);
1044 BuildMI(MBB, MBBI, TII.get(PPC::MFLR8), PPC::X0);
1047 BuildMI(MBB, MBBI, TII.get(PPC::STD))
1048 .addReg(PPC::X31).addImm(FPOffset/4).addReg(PPC::X1);
1051 BuildMI(MBB, MBBI, TII.get(PPC::STD))
1052 .addReg(PPC::X0).addImm(LROffset/4).addReg(PPC::X1);
1055 BuildMI(MBB, MBBI, TII.get(PPC::MFLR), PPC::R0);
1058 BuildMI(MBB, MBBI, TII.get(PPC::STW))
1059 .addReg(PPC::R31).addImm(FPOffset).addReg(PPC::R1);
1062 BuildMI(MBB, MBBI, TII.get(PPC::STW))
1063 .addReg(PPC::R0).addImm(LROffset).addReg(PPC::R1);
1066 // Skip if a leaf routine.
1067 if (!FrameSize) return;
1069 // Get stack alignments.
1070 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
1071 unsigned MaxAlign = MFI->getMaxAlignment();
1073 if (MMI && MMI->needsFrameInfo()) {
1074 // Mark effective beginning of when frame pointer becomes valid.
1075 FrameLabelId = MMI->NextLabelID();
1076 BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(FrameLabelId);
1079 // Adjust stack pointer: r1 += NegFrameSize.
1080 // If there is a preferred stack alignment, align R1 now
1083 if (MaxAlign > TargetAlign) {
1084 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!");
1085 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!");
1086 BuildMI(MBB, MBBI, TII.get(PPC::RLWINM), PPC::R0)
1087 .addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31);
1088 BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC) ,PPC::R0).addReg(PPC::R0)
1089 .addImm(NegFrameSize);
1090 BuildMI(MBB, MBBI, TII.get(PPC::STWUX))
1091 .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
1092 } else if (isInt16(NegFrameSize)) {
1093 BuildMI(MBB, MBBI, TII.get(PPC::STWU),
1094 PPC::R1).addReg(PPC::R1).addImm(NegFrameSize).addReg(PPC::R1);
1096 BuildMI(MBB, MBBI, TII.get(PPC::LIS), PPC::R0).addImm(NegFrameSize >> 16);
1097 BuildMI(MBB, MBBI, TII.get(PPC::ORI), PPC::R0).addReg(PPC::R0)
1098 .addImm(NegFrameSize & 0xFFFF);
1099 BuildMI(MBB, MBBI, TII.get(PPC::STWUX)).addReg(PPC::R1).addReg(PPC::R1)
1103 if (MaxAlign > TargetAlign) {
1104 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!");
1105 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!");
1106 BuildMI(MBB, MBBI, TII.get(PPC::RLDICL), PPC::X0)
1107 .addReg(PPC::X1).addImm(0).addImm(64-Log2_32(MaxAlign));
1108 BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC8), PPC::X0).addReg(PPC::X0)
1109 .addImm(NegFrameSize);
1110 BuildMI(MBB, MBBI, TII.get(PPC::STDUX))
1111 .addReg(PPC::X1).addReg(PPC::X1).addReg(PPC::X0);
1112 } else if (isInt16(NegFrameSize)) {
1113 BuildMI(MBB, MBBI, TII.get(PPC::STDU), PPC::X1)
1114 .addReg(PPC::X1).addImm(NegFrameSize/4).addReg(PPC::X1);
1116 BuildMI(MBB, MBBI, TII.get(PPC::LIS8), PPC::X0).addImm(NegFrameSize >>16);
1117 BuildMI(MBB, MBBI, TII.get(PPC::ORI8), PPC::X0).addReg(PPC::X0)
1118 .addImm(NegFrameSize & 0xFFFF);
1119 BuildMI(MBB, MBBI, TII.get(PPC::STDUX)).addReg(PPC::X1).addReg(PPC::X1)
1124 if (MMI && MMI->needsFrameInfo()) {
1125 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
1128 // Show update of SP.
1129 MachineLocation SPDst(MachineLocation::VirtualFP);
1130 MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize);
1131 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
1133 MachineLocation SP(IsPPC64 ? PPC::X31 : PPC::R31);
1134 Moves.push_back(MachineMove(FrameLabelId, SP, SP));
1138 MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset);
1139 MachineLocation FPSrc(IsPPC64 ? PPC::X31 : PPC::R31);
1140 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc));
1143 // Add callee saved registers to move list.
1144 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1145 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
1146 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
1147 unsigned Reg = CSI[I].getReg();
1148 if (Reg == PPC::LR || Reg == PPC::LR8) continue;
1149 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
1150 MachineLocation CSSrc(Reg);
1151 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
1154 MachineLocation LRDst(MachineLocation::VirtualFP, LROffset);
1155 MachineLocation LRSrc(IsPPC64 ? PPC::LR8 : PPC::LR);
1156 Moves.push_back(MachineMove(FrameLabelId, LRDst, LRSrc));
1158 // Mark effective beginning of when frame pointer is ready.
1159 unsigned ReadyLabelId = MMI->NextLabelID();
1160 BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(ReadyLabelId);
1162 MachineLocation FPDst(HasFP ? (IsPPC64 ? PPC::X31 : PPC::R31) :
1163 (IsPPC64 ? PPC::X1 : PPC::R1));
1164 MachineLocation FPSrc(MachineLocation::VirtualFP);
1165 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
1168 // If there is a frame pointer, copy R1 into R31
1171 BuildMI(MBB, MBBI, TII.get(PPC::OR), PPC::R31).addReg(PPC::R1)
1174 BuildMI(MBB, MBBI, TII.get(PPC::OR8), PPC::X31).addReg(PPC::X1)
1180 void PPCRegisterInfo::emitEpilogue(MachineFunction &MF,
1181 MachineBasicBlock &MBB) const {
1182 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1183 assert(MBBI->getOpcode() == PPC::BLR &&
1184 "Can only insert epilog into returning blocks");
1186 // Get alignment info so we know how to restore r1
1187 const MachineFrameInfo *MFI = MF.getFrameInfo();
1188 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
1189 unsigned MaxAlign = MFI->getMaxAlignment();
1191 // Get the number of bytes allocated from the FrameInfo.
1192 unsigned FrameSize = MFI->getStackSize();
1194 // Get processor type.
1195 bool IsPPC64 = Subtarget.isPPC64();
1196 // Get operating system
1197 bool IsMachoABI = Subtarget.isMachoABI();
1198 // Check if the link register (LR) has been used.
1199 bool UsesLR = MFI->hasCalls() || usesLR(MF);
1200 // Do we have a frame pointer for this function?
1201 bool HasFP = hasFP(MF) && FrameSize;
1203 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI);
1204 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI);
1207 // The loaded (or persistent) stack pointer value is offset by the 'stwu'
1208 // on entry to the function. Add this offset back now.
1209 if (!Subtarget.isPPC64()) {
1210 if (isInt16(FrameSize) && TargetAlign >= MaxAlign &&
1211 !MFI->hasVarSizedObjects()) {
1212 BuildMI(MBB, MBBI, TII.get(PPC::ADDI), PPC::R1)
1213 .addReg(PPC::R1).addImm(FrameSize);
1215 BuildMI(MBB, MBBI, TII.get(PPC::LWZ),PPC::R1).addImm(0).addReg(PPC::R1);
1218 if (isInt16(FrameSize) && TargetAlign >= MaxAlign &&
1219 !MFI->hasVarSizedObjects()) {
1220 BuildMI(MBB, MBBI, TII.get(PPC::ADDI8), PPC::X1)
1221 .addReg(PPC::X1).addImm(FrameSize);
1223 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X1).addImm(0).addReg(PPC::X1);
1230 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X0)
1231 .addImm(LROffset/4).addReg(PPC::X1);
1234 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X31)
1235 .addImm(FPOffset/4).addReg(PPC::X1);
1238 BuildMI(MBB, MBBI, TII.get(PPC::MTLR8)).addReg(PPC::X0);
1241 BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R0)
1242 .addImm(LROffset).addReg(PPC::R1);
1245 BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R31)
1246 .addImm(FPOffset).addReg(PPC::R1);
1249 BuildMI(MBB, MBBI, TII.get(PPC::MTLR)).addReg(PPC::R0);
1253 unsigned PPCRegisterInfo::getRARegister() const {
1254 return !Subtarget.isPPC64() ? PPC::LR : PPC::LR8;
1257 unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const {
1258 if (!Subtarget.isPPC64())
1259 return hasFP(MF) ? PPC::R31 : PPC::R1;
1261 return hasFP(MF) ? PPC::X31 : PPC::X1;
1264 void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
1266 // Initial state of the frame pointer is R1.
1267 MachineLocation Dst(MachineLocation::VirtualFP);
1268 MachineLocation Src(PPC::R1, 0);
1269 Moves.push_back(MachineMove(0, Dst, Src));
1272 unsigned PPCRegisterInfo::getEHExceptionRegister() const {
1273 return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3;
1276 unsigned PPCRegisterInfo::getEHHandlerRegister() const {
1277 return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4;
1280 int PPCRegisterInfo::getDwarfRegNum(unsigned RegNum) const {
1281 // FIXME: Most probably dwarf numbers differs for Linux and Darwin
1282 return PPCGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
1285 #include "PPCGenRegisterInfo.inc"