1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetRegisterInfo
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "reginfo"
17 #include "PPCInstrBuilder.h"
18 #include "PPCMachineFunctionInfo.h"
19 #include "PPCRegisterInfo.h"
20 #include "PPCFrameInfo.h"
21 #include "PPCSubtarget.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/Function.h"
25 #include "llvm/Type.h"
26 #include "llvm/CodeGen/ValueTypes.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineModuleInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineLocation.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/RegisterScavenging.h"
34 #include "llvm/Target/TargetFrameInfo.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/Support/CommandLine.h"
39 #include "llvm/Support/Debug.h"
40 #include "llvm/Support/ErrorHandling.h"
41 #include "llvm/Support/MathExtras.h"
42 #include "llvm/Support/raw_ostream.h"
43 #include "llvm/ADT/BitVector.h"
44 #include "llvm/ADT/STLExtras.h"
48 // FIXME This disables some code that aligns the stack to a boundary
49 // bigger than the default (16 bytes on Darwin) when there is a stack local
50 // of greater alignment. This does not currently work, because the delta
51 // between old and new stack pointers is added to offsets that reference
52 // incoming parameters after the prolog is generated, and the code that
53 // does that doesn't handle a variable delta. You don't want to do that
54 // anyway; a better approach is to reserve another register that retains
55 // to the incoming stack pointer, and reference parameters relative to that.
58 // FIXME (64-bit): Eventually enable by default.
59 cl::opt<bool> EnablePPC32RS("enable-ppc32-regscavenger",
61 cl::desc("Enable PPC32 register scavenger"),
63 cl::opt<bool> EnablePPC64RS("enable-ppc64-regscavenger",
65 cl::desc("Enable PPC64 register scavenger"),
67 #define EnableRegisterScavenging \
68 ((EnablePPC32RS && !Subtarget.isPPC64()) || \
69 (EnablePPC64RS && Subtarget.isPPC64()))
71 // FIXME (64-bit): Should be inlined.
73 PPCRegisterInfo::requiresRegisterScavenging(const MachineFunction &) const {
74 return EnableRegisterScavenging;
77 /// getRegisterNumbering - Given the enum value for some register, e.g.
78 /// PPC::F14, return the number that it corresponds to (e.g. 14).
79 unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
83 case R0 : case X0 : case F0 : case V0 : case CR0: case CR0LT: return 0;
84 case R1 : case X1 : case F1 : case V1 : case CR1: case CR0GT: return 1;
85 case R2 : case X2 : case F2 : case V2 : case CR2: case CR0EQ: return 2;
86 case R3 : case X3 : case F3 : case V3 : case CR3: case CR0UN: return 3;
87 case R4 : case X4 : case F4 : case V4 : case CR4: case CR1LT: return 4;
88 case R5 : case X5 : case F5 : case V5 : case CR5: case CR1GT: return 5;
89 case R6 : case X6 : case F6 : case V6 : case CR6: case CR1EQ: return 6;
90 case R7 : case X7 : case F7 : case V7 : case CR7: case CR1UN: return 7;
91 case R8 : case X8 : case F8 : case V8 : case CR2LT: return 8;
92 case R9 : case X9 : case F9 : case V9 : case CR2GT: return 9;
93 case R10: case X10: case F10: case V10: case CR2EQ: return 10;
94 case R11: case X11: case F11: case V11: case CR2UN: return 11;
95 case R12: case X12: case F12: case V12: case CR3LT: return 12;
96 case R13: case X13: case F13: case V13: case CR3GT: return 13;
97 case R14: case X14: case F14: case V14: case CR3EQ: return 14;
98 case R15: case X15: case F15: case V15: case CR3UN: return 15;
99 case R16: case X16: case F16: case V16: case CR4LT: return 16;
100 case R17: case X17: case F17: case V17: case CR4GT: return 17;
101 case R18: case X18: case F18: case V18: case CR4EQ: return 18;
102 case R19: case X19: case F19: case V19: case CR4UN: return 19;
103 case R20: case X20: case F20: case V20: case CR5LT: return 20;
104 case R21: case X21: case F21: case V21: case CR5GT: return 21;
105 case R22: case X22: case F22: case V22: case CR5EQ: return 22;
106 case R23: case X23: case F23: case V23: case CR5UN: return 23;
107 case R24: case X24: case F24: case V24: case CR6LT: return 24;
108 case R25: case X25: case F25: case V25: case CR6GT: return 25;
109 case R26: case X26: case F26: case V26: case CR6EQ: return 26;
110 case R27: case X27: case F27: case V27: case CR6UN: return 27;
111 case R28: case X28: case F28: case V28: case CR7LT: return 28;
112 case R29: case X29: case F29: case V29: case CR7GT: return 29;
113 case R30: case X30: case F30: case V30: case CR7EQ: return 30;
114 case R31: case X31: case F31: case V31: case CR7UN: return 31;
116 llvm_unreachable("Unhandled reg in PPCRegisterInfo::getRegisterNumbering!");
120 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST,
121 const TargetInstrInfo &tii)
122 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
123 Subtarget(ST), TII(tii) {
124 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
125 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
126 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
127 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
128 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
129 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
130 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
131 ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
134 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8;
135 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8;
136 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8;
137 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX;
138 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32;
141 /// getPointerRegClass - Return the register class to use to hold pointers.
142 /// This is used for addressing modes.
143 const TargetRegisterClass *
144 PPCRegisterInfo::getPointerRegClass(unsigned Kind) const {
145 if (Subtarget.isPPC64())
146 return &PPC::G8RCRegClass;
147 return &PPC::GPRCRegClass;
151 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
152 // 32-bit Darwin calling convention.
153 static const unsigned Darwin32_CalleeSavedRegs[] = {
154 PPC::R13, PPC::R14, PPC::R15,
155 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
156 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
157 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
158 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
160 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
161 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
162 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
163 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
166 PPC::CR2, PPC::CR3, PPC::CR4,
167 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
168 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
169 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
171 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
172 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
173 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
178 // 32-bit SVR4 calling convention.
179 static const unsigned SVR4_CalleeSavedRegs[] = {
181 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
182 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
183 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
184 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
186 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
187 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
188 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
189 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
192 PPC::CR2, PPC::CR3, PPC::CR4,
196 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
197 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
198 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
200 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
201 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
202 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
206 // 64-bit Darwin calling convention.
207 static const unsigned Darwin64_CalleeSavedRegs[] = {
209 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
210 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
211 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
212 PPC::X28, PPC::X29, PPC::X30, PPC::X31,
214 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
215 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
216 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
217 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
220 PPC::CR2, PPC::CR3, PPC::CR4,
221 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
222 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
223 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
225 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
226 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
227 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
232 // 64-bit SVR4 calling convention.
233 static const unsigned SVR4_64_CalleeSavedRegs[] = {
235 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
236 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
237 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
238 PPC::X28, PPC::X29, PPC::X30, PPC::X31,
240 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
241 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
242 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
243 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
246 PPC::CR2, PPC::CR3, PPC::CR4,
250 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
251 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
252 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
254 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
255 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
256 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
261 if (Subtarget.isDarwinABI())
262 return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegs :
263 Darwin32_CalleeSavedRegs;
265 return Subtarget.isPPC64() ? SVR4_64_CalleeSavedRegs : SVR4_CalleeSavedRegs;
268 const TargetRegisterClass* const*
269 PPCRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
270 // 32-bit Darwin calling convention.
271 static const TargetRegisterClass * const Darwin32_CalleeSavedRegClasses[] = {
272 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
273 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
274 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
275 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
276 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
278 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
279 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
280 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
281 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
282 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
284 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
286 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
287 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
288 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
290 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
291 &PPC::CRBITRCRegClass,
292 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
293 &PPC::CRBITRCRegClass,
294 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
295 &PPC::CRBITRCRegClass,
297 &PPC::GPRCRegClass, 0
300 // 32-bit SVR4 calling convention.
301 static const TargetRegisterClass * const SVR4_CalleeSavedRegClasses[] = {
302 &PPC::GPRCRegClass,&PPC::GPRCRegClass,
303 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
304 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
305 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
306 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
308 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
309 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
310 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
311 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
312 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
314 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
316 &PPC::VRSAVERCRegClass,
318 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
319 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
320 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
322 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
323 &PPC::CRBITRCRegClass,
324 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
325 &PPC::CRBITRCRegClass,
326 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
327 &PPC::CRBITRCRegClass,
332 // 64-bit Darwin calling convention.
333 static const TargetRegisterClass * const Darwin64_CalleeSavedRegClasses[] = {
334 &PPC::G8RCRegClass,&PPC::G8RCRegClass,
335 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
336 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
337 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
338 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
340 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
341 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
342 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
343 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
344 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
346 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
348 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
349 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
350 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
352 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
353 &PPC::CRBITRCRegClass,
354 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
355 &PPC::CRBITRCRegClass,
356 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
357 &PPC::CRBITRCRegClass,
359 &PPC::G8RCRegClass, 0
362 // 64-bit SVR4 calling convention.
363 static const TargetRegisterClass * const SVR4_64_CalleeSavedRegClasses[] = {
364 &PPC::G8RCRegClass,&PPC::G8RCRegClass,
365 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
366 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
367 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
368 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
370 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
371 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
372 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
373 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
374 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
376 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
378 &PPC::VRSAVERCRegClass,
380 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
381 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
382 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
384 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
385 &PPC::CRBITRCRegClass,
386 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
387 &PPC::CRBITRCRegClass,
388 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
389 &PPC::CRBITRCRegClass,
394 if (Subtarget.isDarwinABI())
395 return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegClasses :
396 Darwin32_CalleeSavedRegClasses;
398 return Subtarget.isPPC64() ? SVR4_64_CalleeSavedRegClasses
399 : SVR4_CalleeSavedRegClasses;
402 // needsFP - Return true if the specified function should have a dedicated frame
403 // pointer register. This is true if the function has variable sized allocas or
404 // if frame pointer elimination is disabled.
406 static bool needsFP(const MachineFunction &MF) {
407 const MachineFrameInfo *MFI = MF.getFrameInfo();
408 return NoFramePointerElim || MFI->hasVarSizedObjects() ||
409 (PerformTailCallOpt && MF.getInfo<PPCFunctionInfo>()->hasFastCall());
412 static bool spillsCR(const MachineFunction &MF) {
413 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
414 return FuncInfo->isCRSpilled();
417 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
418 BitVector Reserved(getNumRegs());
419 Reserved.set(PPC::R0);
420 Reserved.set(PPC::R1);
421 Reserved.set(PPC::LR);
422 Reserved.set(PPC::LR8);
423 Reserved.set(PPC::RM);
425 // The SVR4 ABI reserves r2 and r13
426 if (Subtarget.isSVR4ABI()) {
427 Reserved.set(PPC::R2); // System-reserved register
428 Reserved.set(PPC::R13); // Small Data Area pointer register
431 // On PPC64, r13 is the thread pointer. Never allocate this register.
432 // Note that this is over conservative, as it also prevents allocation of R31
433 // when the FP is not needed.
434 if (Subtarget.isPPC64()) {
435 Reserved.set(PPC::R13);
436 Reserved.set(PPC::R31);
438 if (!EnableRegisterScavenging)
439 Reserved.set(PPC::R0); // FIXME (64-bit): Remove
441 Reserved.set(PPC::X0);
442 Reserved.set(PPC::X1);
443 Reserved.set(PPC::X13);
444 Reserved.set(PPC::X31);
446 // The 64-bit SVR4 ABI reserves r2 for the TOC pointer.
447 if (Subtarget.isSVR4ABI()) {
448 Reserved.set(PPC::X2);
453 Reserved.set(PPC::R31);
458 //===----------------------------------------------------------------------===//
459 // Stack Frame Processing methods
460 //===----------------------------------------------------------------------===//
462 // hasFP - Return true if the specified function actually has a dedicated frame
463 // pointer register. This is true if the function needs a frame pointer and has
464 // a non-zero stack size.
465 bool PPCRegisterInfo::hasFP(const MachineFunction &MF) const {
466 const MachineFrameInfo *MFI = MF.getFrameInfo();
467 return MFI->getStackSize() && needsFP(MF);
470 /// MustSaveLR - Return true if this function requires that we save the LR
471 /// register onto the stack in the prolog and restore it in the epilog of the
473 static bool MustSaveLR(const MachineFunction &MF, unsigned LR) {
474 const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>();
476 // We need a save/restore of LR if there is any def of LR (which is
477 // defined by calls, including the PIC setup sequence), or if there is
478 // some use of the LR stack slot (e.g. for builtin_return_address).
479 // (LR comes in 32 and 64 bit versions.)
480 MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR);
481 return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired();
486 void PPCRegisterInfo::
487 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
488 MachineBasicBlock::iterator I) const {
489 if (PerformTailCallOpt && I->getOpcode() == PPC::ADJCALLSTACKUP) {
490 // Add (actually subtract) back the amount the callee popped on return.
491 if (int CalleeAmt = I->getOperand(1).getImm()) {
492 bool is64Bit = Subtarget.isPPC64();
494 unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1;
495 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0;
496 unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI;
497 unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4;
498 unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS;
499 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI;
500 MachineInstr *MI = I;
501 DebugLoc dl = MI->getDebugLoc();
503 if (isInt16(CalleeAmt)) {
504 BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg).addReg(StackReg).
507 MachineBasicBlock::iterator MBBI = I;
508 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
509 .addImm(CalleeAmt >> 16);
510 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
511 .addReg(TmpReg, RegState::Kill)
512 .addImm(CalleeAmt & 0xFFFF);
513 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr))
520 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
524 /// findScratchRegister - Find a 'free' PPC register. Try for a call-clobbered
525 /// register first and then a spilled callee-saved register if that fails.
527 unsigned findScratchRegister(MachineBasicBlock::iterator II, RegScavenger *RS,
528 const TargetRegisterClass *RC, int SPAdj) {
529 assert(RS && "Register scavenging must be on");
530 unsigned Reg = RS->FindUnusedReg(RC);
531 // FIXME: move ARM callee-saved reg scan to target independent code, then
532 // search for already spilled CS register here.
534 Reg = RS->scavengeRegister(RC, II, SPAdj);
538 /// lowerDynamicAlloc - Generate the code for allocating an object in the
539 /// current frame. The sequence of code with be in the general form
541 /// addi R0, SP, \#frameSize ; get the address of the previous frame
542 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size
543 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation
545 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II,
546 int SPAdj, RegScavenger *RS) const {
547 // Get the instruction.
548 MachineInstr &MI = *II;
549 // Get the instruction's basic block.
550 MachineBasicBlock &MBB = *MI.getParent();
551 // Get the basic block's function.
552 MachineFunction &MF = *MBB.getParent();
553 // Get the frame info.
554 MachineFrameInfo *MFI = MF.getFrameInfo();
555 // Determine whether 64-bit pointers are used.
556 bool LP64 = Subtarget.isPPC64();
557 DebugLoc dl = MI.getDebugLoc();
559 // Get the maximum call stack size.
560 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
561 // Get the total frame size.
562 unsigned FrameSize = MFI->getStackSize();
564 // Get stack alignments.
565 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
566 unsigned MaxAlign = MFI->getMaxAlignment();
567 assert(MaxAlign <= TargetAlign &&
568 "Dynamic alloca with large aligns not supported");
570 // Determine the previous frame's address. If FrameSize can't be
571 // represented as 16 bits or we need special alignment, then we load the
572 // previous frame's address from 0(SP). Why not do an addis of the hi?
573 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
574 // Constructing the constant and adding would take 3 instructions.
575 // Fortunately, a frame greater than 32K is rare.
576 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
577 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
578 const TargetRegisterClass *RC = LP64 ? G8RC : GPRC;
580 // FIXME (64-bit): Use "findScratchRegister"
582 if (EnableRegisterScavenging)
583 Reg = findScratchRegister(II, RS, RC, SPAdj);
587 if (MaxAlign < TargetAlign && isInt16(FrameSize)) {
588 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg)
592 if (EnableRegisterScavenging) // FIXME (64-bit): Use "true" part.
593 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg)
597 BuildMI(MBB, II, dl, TII.get(PPC::LD), PPC::X0)
601 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg)
606 // Grow the stack and update the stack pointer link, then determine the
607 // address of new allocated space.
609 if (EnableRegisterScavenging) // FIXME (64-bit): Use "true" part.
610 BuildMI(MBB, II, dl, TII.get(PPC::STDUX))
611 .addReg(Reg, RegState::Kill)
613 .addReg(MI.getOperand(1).getReg());
615 BuildMI(MBB, II, dl, TII.get(PPC::STDUX))
616 .addReg(PPC::X0, RegState::Kill)
618 .addReg(MI.getOperand(1).getReg());
620 if (!MI.getOperand(1).isKill())
621 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
623 .addImm(maxCallFrameSize);
625 // Implicitly kill the register.
626 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
628 .addImm(maxCallFrameSize)
629 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill);
631 BuildMI(MBB, II, dl, TII.get(PPC::STWUX))
632 .addReg(Reg, RegState::Kill)
634 .addReg(MI.getOperand(1).getReg());
636 if (!MI.getOperand(1).isKill())
637 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
639 .addImm(maxCallFrameSize);
641 // Implicitly kill the register.
642 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
644 .addImm(maxCallFrameSize)
645 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill);
648 // Discard the DYNALLOC instruction.
652 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of
653 /// reserving a whole register (R0), we scrounge for one here. This generates
656 /// mfcr rA ; Move the conditional register into GPR rA.
657 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot.
658 /// stw rA, FI ; Store rA to the frame.
660 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II,
661 unsigned FrameIndex, int SPAdj,
662 RegScavenger *RS) const {
663 // Get the instruction.
664 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>, <FI>
665 // Get the instruction's basic block.
666 MachineBasicBlock &MBB = *MI.getParent();
667 DebugLoc dl = MI.getDebugLoc();
669 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
670 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
671 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC;
672 unsigned Reg = findScratchRegister(II, RS, RC, SPAdj);
674 // We need to store the CR in the low 4-bits of the saved value. First, issue
675 // an MFCR to save all of the CRBits. Add an implicit kill of the CR.
676 if (!MI.getOperand(0).isKill())
677 BuildMI(MBB, II, dl, TII.get(PPC::MFCR), Reg);
679 // Implicitly kill the CR register.
680 BuildMI(MBB, II, dl, TII.get(PPC::MFCR), Reg)
681 .addReg(MI.getOperand(0).getReg(), RegState::ImplicitKill);
683 // If the saved register wasn't CR0, shift the bits left so that they are in
685 unsigned SrcReg = MI.getOperand(0).getReg();
686 if (SrcReg != PPC::CR0)
687 // rlwinm rA, rA, ShiftBits, 0, 31.
688 BuildMI(MBB, II, dl, TII.get(PPC::RLWINM), Reg)
689 .addReg(Reg, RegState::Kill)
690 .addImm(PPCRegisterInfo::getRegisterNumbering(SrcReg) * 4)
694 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::STW))
695 .addReg(Reg, getKillRegState(MI.getOperand(1).getImm())),
698 // Discard the pseudo instruction.
703 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
704 int SPAdj, int *Value,
705 RegScavenger *RS) const {
706 assert(SPAdj == 0 && "Unexpected");
708 // Get the instruction.
709 MachineInstr &MI = *II;
710 // Get the instruction's basic block.
711 MachineBasicBlock &MBB = *MI.getParent();
712 // Get the basic block's function.
713 MachineFunction &MF = *MBB.getParent();
714 // Get the frame info.
715 MachineFrameInfo *MFI = MF.getFrameInfo();
716 DebugLoc dl = MI.getDebugLoc();
718 // Find out which operand is the frame index.
719 unsigned FIOperandNo = 0;
720 while (!MI.getOperand(FIOperandNo).isFI()) {
722 assert(FIOperandNo != MI.getNumOperands() &&
723 "Instr doesn't have FrameIndex operand!");
725 // Take into account whether it's an add or mem instruction
726 unsigned OffsetOperandNo = (FIOperandNo == 2) ? 1 : 2;
727 if (MI.getOpcode() == TargetInstrInfo::INLINEASM)
728 OffsetOperandNo = FIOperandNo-1;
730 // Get the frame index.
731 int FrameIndex = MI.getOperand(FIOperandNo).getIndex();
733 // Get the frame pointer save index. Users of this index are primarily
734 // DYNALLOC instructions.
735 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
736 int FPSI = FI->getFramePointerSaveIndex();
737 // Get the instruction opcode.
738 unsigned OpC = MI.getOpcode();
740 // Special case for dynamic alloca.
741 if (FPSI && FrameIndex == FPSI &&
742 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
743 lowerDynamicAlloc(II, SPAdj, RS);
747 // Special case for pseudo-op SPILL_CR.
748 if (EnableRegisterScavenging) // FIXME (64-bit): Enable by default.
749 if (OpC == PPC::SPILL_CR) {
750 lowerCRSpilling(II, FrameIndex, SPAdj, RS);
754 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
755 MI.getOperand(FIOperandNo).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1,
758 // Figure out if the offset in the instruction is shifted right two bits. This
759 // is true for instructions like "STD", which the machine implicitly adds two
761 bool isIXAddr = false;
771 // Now add the frame object offset to the offset from r1.
772 int Offset = MFI->getObjectOffset(FrameIndex);
774 Offset += MI.getOperand(OffsetOperandNo).getImm();
776 Offset += MI.getOperand(OffsetOperandNo).getImm() << 2;
778 // If we're not using a Frame Pointer that has been set to the value of the
779 // SP before having the stack size subtracted from it, then add the stack size
780 // to Offset to get the correct offset.
781 Offset += MFI->getStackSize();
783 // If we can, encode the offset directly into the instruction. If this is a
784 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If
785 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits
786 // clear can be encoded. This is extremely uncommon, because normally you
787 // only "std" to a stack slot that is at least 4-byte aligned, but it can
788 // happen in invalid code.
789 if (isInt16(Offset) && (!isIXAddr || (Offset & 3) == 0)) {
791 Offset >>= 2; // The actual encoded value has the low two bits zero.
792 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
796 // The offset doesn't fit into a single register, scavenge one to build the
798 // FIXME: figure out what SPAdj is doing here.
800 // FIXME (64-bit): Use "findScratchRegister".
802 if (EnableRegisterScavenging)
803 SReg = findScratchRegister(II, RS, &PPC::GPRCRegClass, SPAdj);
807 // Insert a set of rA with the full offset value before the ld, st, or add
808 BuildMI(MBB, II, dl, TII.get(PPC::LIS), SReg)
809 .addImm(Offset >> 16);
810 BuildMI(MBB, II, dl, TII.get(PPC::ORI), SReg)
811 .addReg(SReg, RegState::Kill)
814 // Convert into indexed form of the instruction:
816 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
817 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
818 unsigned OperandBase;
820 if (OpC != TargetInstrInfo::INLINEASM) {
821 assert(ImmToIdxMap.count(OpC) &&
822 "No indexed form of load or store available!");
823 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second;
824 MI.setDesc(TII.get(NewOpcode));
827 OperandBase = OffsetOperandNo;
830 unsigned StackReg = MI.getOperand(FIOperandNo).getReg();
831 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false);
832 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false);
836 /// VRRegNo - Map from a numbered VR register to its enum value.
838 static const unsigned short VRRegNo[] = {
839 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
840 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
841 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
842 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
845 /// RemoveVRSaveCode - We have found that this function does not need any code
846 /// to manipulate the VRSAVE register, even though it uses vector registers.
847 /// This can happen when the only registers used are known to be live in or out
848 /// of the function. Remove all of the VRSAVE related code from the function.
849 static void RemoveVRSaveCode(MachineInstr *MI) {
850 MachineBasicBlock *Entry = MI->getParent();
851 MachineFunction *MF = Entry->getParent();
853 // We know that the MTVRSAVE instruction immediately follows MI. Remove it.
854 MachineBasicBlock::iterator MBBI = MI;
856 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
857 MBBI->eraseFromParent();
859 bool RemovedAllMTVRSAVEs = true;
860 // See if we can find and remove the MTVRSAVE instruction from all of the
862 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
863 // If last instruction is a return instruction, add an epilogue
864 if (!I->empty() && I->back().getDesc().isReturn()) {
865 bool FoundIt = false;
866 for (MBBI = I->end(); MBBI != I->begin(); ) {
868 if (MBBI->getOpcode() == PPC::MTVRSAVE) {
869 MBBI->eraseFromParent(); // remove it.
874 RemovedAllMTVRSAVEs &= FoundIt;
878 // If we found and removed all MTVRSAVE instructions, remove the read of
880 if (RemovedAllMTVRSAVEs) {
882 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
884 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
885 MBBI->eraseFromParent();
888 // Finally, nuke the UPDATE_VRSAVE.
889 MI->eraseFromParent();
892 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
893 // instruction selector. Based on the vector registers that have been used,
894 // transform this into the appropriate ORI instruction.
895 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) {
896 MachineFunction *MF = MI->getParent()->getParent();
897 DebugLoc dl = MI->getDebugLoc();
899 unsigned UsedRegMask = 0;
900 for (unsigned i = 0; i != 32; ++i)
901 if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i]))
902 UsedRegMask |= 1 << (31-i);
904 // Live in and live out values already must be in the mask, so don't bother
906 for (MachineRegisterInfo::livein_iterator
907 I = MF->getRegInfo().livein_begin(),
908 E = MF->getRegInfo().livein_end(); I != E; ++I) {
909 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first);
910 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg.
911 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
913 for (MachineRegisterInfo::liveout_iterator
914 I = MF->getRegInfo().liveout_begin(),
915 E = MF->getRegInfo().liveout_end(); I != E; ++I) {
916 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I);
917 if (VRRegNo[RegNo] == *I) // If this really is a vector reg.
918 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
921 // If no registers are used, turn this into a copy.
922 if (UsedRegMask == 0) {
923 // Remove all VRSAVE code.
924 RemoveVRSaveCode(MI);
928 unsigned SrcReg = MI->getOperand(1).getReg();
929 unsigned DstReg = MI->getOperand(0).getReg();
931 if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
932 if (DstReg != SrcReg)
933 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
935 .addImm(UsedRegMask);
937 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
938 .addReg(SrcReg, RegState::Kill)
939 .addImm(UsedRegMask);
940 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
941 if (DstReg != SrcReg)
942 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
944 .addImm(UsedRegMask >> 16);
946 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
947 .addReg(SrcReg, RegState::Kill)
948 .addImm(UsedRegMask >> 16);
950 if (DstReg != SrcReg)
951 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
953 .addImm(UsedRegMask >> 16);
955 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
956 .addReg(SrcReg, RegState::Kill)
957 .addImm(UsedRegMask >> 16);
959 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
960 .addReg(DstReg, RegState::Kill)
961 .addImm(UsedRegMask & 0xFFFF);
964 // Remove the old UPDATE_VRSAVE instruction.
965 MI->eraseFromParent();
968 /// determineFrameLayout - Determine the size of the frame and maximum call
970 void PPCRegisterInfo::determineFrameLayout(MachineFunction &MF) const {
971 MachineFrameInfo *MFI = MF.getFrameInfo();
973 // Get the number of bytes to allocate from the FrameInfo
974 unsigned FrameSize = MFI->getStackSize();
976 // Get the alignments provided by the target, and the maximum alignment
977 // (if any) of the fixed frame objects.
978 unsigned MaxAlign = MFI->getMaxAlignment();
979 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
980 unsigned AlignMask = TargetAlign - 1; //
982 // If we are a leaf function, and use up to 224 bytes of stack space,
983 // don't have a frame pointer, calls, or dynamic alloca then we do not need
984 // to adjust the stack pointer (we fit in the Red Zone).
985 bool DisableRedZone = MF.getFunction()->hasFnAttr(Attribute::NoRedZone);
986 // FIXME SVR4 The 32-bit SVR4 ABI has no red zone.
987 if (!DisableRedZone &&
988 FrameSize <= 224 && // Fits in red zone.
989 !MFI->hasVarSizedObjects() && // No dynamic alloca.
990 !MFI->hasCalls() && // No calls.
991 (!ALIGN_STACK || MaxAlign <= TargetAlign)) { // No special alignment.
993 MFI->setStackSize(0);
997 // Get the maximum call frame size of all the calls.
998 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
1000 // Maximum call frame needs to be at least big enough for linkage and 8 args.
1001 unsigned minCallFrameSize =
1002 PPCFrameInfo::getMinCallFrameSize(Subtarget.isPPC64(),
1003 Subtarget.isDarwinABI());
1004 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
1006 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
1007 // that allocations will be aligned.
1008 if (MFI->hasVarSizedObjects())
1009 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
1011 // Update maximum call frame size.
1012 MFI->setMaxCallFrameSize(maxCallFrameSize);
1014 // Include call frame size in total.
1015 FrameSize += maxCallFrameSize;
1017 // Make sure the frame is aligned.
1018 FrameSize = (FrameSize + AlignMask) & ~AlignMask;
1020 // Update frame info.
1021 MFI->setStackSize(FrameSize);
1025 PPCRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
1026 RegScavenger *RS) const {
1027 // Save and clear the LR state.
1028 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1029 unsigned LR = getRARegister();
1030 FI->setMustSaveLR(MustSaveLR(MF, LR));
1031 MF.getRegInfo().setPhysRegUnused(LR);
1033 // Save R31 if necessary
1034 int FPSI = FI->getFramePointerSaveIndex();
1035 bool IsPPC64 = Subtarget.isPPC64();
1036 bool IsSVR4ABI = Subtarget.isSVR4ABI();
1037 bool isDarwinABI = Subtarget.isDarwinABI();
1038 MachineFrameInfo *MFI = MF.getFrameInfo();
1040 // If the frame pointer save index hasn't been defined yet.
1041 if (!FPSI && needsFP(MF) && IsSVR4ABI) {
1042 // Find out what the fix offset of the frame pointer save area.
1043 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64,
1045 // Allocate the frame index for frame pointer save area.
1046 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset);
1048 FI->setFramePointerSaveIndex(FPSI);
1051 // Reserve stack space to move the linkage area to in case of a tail call.
1053 if (PerformTailCallOpt && (TCSPDelta = FI->getTailCallSPDelta()) < 0) {
1054 MF.getFrameInfo()->CreateFixedObject(-1 * TCSPDelta, TCSPDelta);
1057 // Reserve a slot closest to SP or frame pointer if we have a dynalloc or
1058 // a large stack, which will require scavenging a register to materialize a
1060 // FIXME: this doesn't actually check stack size, so is a bit pessimistic
1061 // FIXME: doesn't detect whether or not we need to spill vXX, which requires
1064 if (EnableRegisterScavenging) // FIXME (64-bit): Enable.
1065 if (needsFP(MF) || spillsCR(MF)) {
1066 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
1067 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
1068 const TargetRegisterClass *RC = IsPPC64 ? G8RC : GPRC;
1069 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1070 RC->getAlignment()));
1075 PPCRegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF)
1077 // Early exit if not using the SVR4 ABI.
1078 if (!Subtarget.isSVR4ABI()) {
1082 // Get callee saved register information.
1083 MachineFrameInfo *FFI = MF.getFrameInfo();
1084 const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo();
1086 // Early exit if no callee saved registers are modified!
1087 if (CSI.empty() && !needsFP(MF)) {
1091 unsigned MinGPR = PPC::R31;
1092 unsigned MinG8R = PPC::X31;
1093 unsigned MinFPR = PPC::F31;
1094 unsigned MinVR = PPC::V31;
1096 bool HasGPSaveArea = false;
1097 bool HasG8SaveArea = false;
1098 bool HasFPSaveArea = false;
1099 bool HasCRSaveArea = false;
1100 bool HasVRSAVESaveArea = false;
1101 bool HasVRSaveArea = false;
1103 SmallVector<CalleeSavedInfo, 18> GPRegs;
1104 SmallVector<CalleeSavedInfo, 18> G8Regs;
1105 SmallVector<CalleeSavedInfo, 18> FPRegs;
1106 SmallVector<CalleeSavedInfo, 18> VRegs;
1108 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1109 unsigned Reg = CSI[i].getReg();
1110 const TargetRegisterClass *RC = CSI[i].getRegClass();
1112 if (RC == PPC::GPRCRegisterClass) {
1113 HasGPSaveArea = true;
1115 GPRegs.push_back(CSI[i]);
1120 } else if (RC == PPC::G8RCRegisterClass) {
1121 HasG8SaveArea = true;
1123 G8Regs.push_back(CSI[i]);
1128 } else if (RC == PPC::F8RCRegisterClass) {
1129 HasFPSaveArea = true;
1131 FPRegs.push_back(CSI[i]);
1136 // FIXME SVR4: Disable CR save area for now.
1137 } else if ( RC == PPC::CRBITRCRegisterClass
1138 || RC == PPC::CRRCRegisterClass) {
1139 // HasCRSaveArea = true;
1140 } else if (RC == PPC::VRSAVERCRegisterClass) {
1141 HasVRSAVESaveArea = true;
1142 } else if (RC == PPC::VRRCRegisterClass) {
1143 HasVRSaveArea = true;
1145 VRegs.push_back(CSI[i]);
1151 llvm_unreachable("Unknown RegisterClass!");
1155 PPCFunctionInfo *PFI = MF.getInfo<PPCFunctionInfo>();
1157 int64_t LowerBound = 0;
1159 // Take into account stack space reserved for tail calls.
1161 if (PerformTailCallOpt && (TCSPDelta = PFI->getTailCallSPDelta()) < 0) {
1162 LowerBound = TCSPDelta;
1165 // The Floating-point register save area is right below the back chain word
1166 // of the previous stack frame.
1167 if (HasFPSaveArea) {
1168 for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) {
1169 int FI = FPRegs[i].getFrameIdx();
1171 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1174 LowerBound -= (31 - getRegisterNumbering(MinFPR) + 1) * 8;
1177 // Check whether the frame pointer register is allocated. If so, make sure it
1178 // is spilled to the correct offset.
1180 HasGPSaveArea = true;
1182 int FI = PFI->getFramePointerSaveIndex();
1183 assert(FI && "No Frame Pointer Save Slot!");
1185 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1188 // General register save area starts right below the Floating-point
1189 // register save area.
1190 if (HasGPSaveArea || HasG8SaveArea) {
1191 // Move general register save area spill slots down, taking into account
1192 // the size of the Floating-point register save area.
1193 for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) {
1194 int FI = GPRegs[i].getFrameIdx();
1196 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1199 // Move general register save area spill slots down, taking into account
1200 // the size of the Floating-point register save area.
1201 for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) {
1202 int FI = G8Regs[i].getFrameIdx();
1204 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1207 unsigned MinReg = std::min<unsigned>(getRegisterNumbering(MinGPR),
1208 getRegisterNumbering(MinG8R));
1210 if (Subtarget.isPPC64()) {
1211 LowerBound -= (31 - MinReg + 1) * 8;
1213 LowerBound -= (31 - MinReg + 1) * 4;
1217 // The CR save area is below the general register save area.
1218 if (HasCRSaveArea) {
1219 // FIXME SVR4: Is it actually possible to have multiple elements in CSI
1220 // which have the CR/CRBIT register class?
1221 // Adjust the frame index of the CR spill slot.
1222 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1223 const TargetRegisterClass *RC = CSI[i].getRegClass();
1225 if (RC == PPC::CRBITRCRegisterClass || RC == PPC::CRRCRegisterClass) {
1226 int FI = CSI[i].getFrameIdx();
1228 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1232 LowerBound -= 4; // The CR save area is always 4 bytes long.
1235 if (HasVRSAVESaveArea) {
1236 // FIXME SVR4: Is it actually possible to have multiple elements in CSI
1237 // which have the VRSAVE register class?
1238 // Adjust the frame index of the VRSAVE spill slot.
1239 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1240 const TargetRegisterClass *RC = CSI[i].getRegClass();
1242 if (RC == PPC::VRSAVERCRegisterClass) {
1243 int FI = CSI[i].getFrameIdx();
1245 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1249 LowerBound -= 4; // The VRSAVE save area is always 4 bytes long.
1252 if (HasVRSaveArea) {
1253 // Insert alignment padding, we need 16-byte alignment.
1254 LowerBound = (LowerBound - 15) & ~(15);
1256 for (unsigned i = 0, e = VRegs.size(); i != e; ++i) {
1257 int FI = VRegs[i].getFrameIdx();
1259 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1265 PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
1266 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
1267 MachineBasicBlock::iterator MBBI = MBB.begin();
1268 MachineFrameInfo *MFI = MF.getFrameInfo();
1269 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
1270 DebugLoc dl = DebugLoc::getUnknownLoc();
1271 bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) ||
1272 !MF.getFunction()->doesNotThrow() ||
1273 UnwindTablesMandatory;
1275 // Prepare for frame info.
1276 unsigned FrameLabelId = 0;
1278 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
1280 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
1281 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
1282 HandleVRSaveUpdate(MBBI, TII);
1287 // Move MBBI back to the beginning of the function.
1290 // Work out frame sizes.
1291 determineFrameLayout(MF);
1292 unsigned FrameSize = MFI->getStackSize();
1294 int NegFrameSize = -FrameSize;
1296 // Get processor type.
1297 bool IsPPC64 = Subtarget.isPPC64();
1298 // Get operating system
1299 bool isDarwinABI = Subtarget.isDarwinABI();
1300 // Check if the link register (LR) must be saved.
1301 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1302 bool MustSaveLR = FI->mustSaveLR();
1303 // Do we have a frame pointer for this function?
1304 bool HasFP = hasFP(MF) && FrameSize;
1306 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, isDarwinABI);
1310 if (Subtarget.isSVR4ABI()) {
1311 MachineFrameInfo *FFI = MF.getFrameInfo();
1312 int FPIndex = FI->getFramePointerSaveIndex();
1313 assert(FPIndex && "No Frame Pointer Save Slot!");
1314 FPOffset = FFI->getObjectOffset(FPIndex);
1316 FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, isDarwinABI);
1322 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR8), PPC::X0);
1325 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD))
1331 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD))
1333 .addImm(LROffset / 4)
1337 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR), PPC::R0);
1340 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW))
1346 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW))
1352 // Skip if a leaf routine.
1353 if (!FrameSize) return;
1355 // Get stack alignments.
1356 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
1357 unsigned MaxAlign = MFI->getMaxAlignment();
1359 if (needsFrameMoves) {
1360 // Mark effective beginning of when frame pointer becomes valid.
1361 FrameLabelId = MMI->NextLabelID();
1362 BuildMI(MBB, MBBI, dl, TII.get(PPC::DBG_LABEL)).addImm(FrameLabelId);
1365 // Adjust stack pointer: r1 += NegFrameSize.
1366 // If there is a preferred stack alignment, align R1 now
1369 if (ALIGN_STACK && MaxAlign > TargetAlign) {
1370 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!");
1371 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!");
1373 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), PPC::R0)
1376 .addImm(32 - Log2_32(MaxAlign))
1378 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC) ,PPC::R0)
1379 .addReg(PPC::R0, RegState::Kill)
1380 .addImm(NegFrameSize);
1381 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX))
1385 } else if (isInt16(NegFrameSize)) {
1386 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWU), PPC::R1)
1388 .addImm(NegFrameSize)
1391 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0)
1392 .addImm(NegFrameSize >> 16);
1393 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0)
1394 .addReg(PPC::R0, RegState::Kill)
1395 .addImm(NegFrameSize & 0xFFFF);
1396 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX))
1402 if (ALIGN_STACK && MaxAlign > TargetAlign) {
1403 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!");
1404 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!");
1406 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), PPC::X0)
1409 .addImm(64 - Log2_32(MaxAlign));
1410 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC8), PPC::X0)
1412 .addImm(NegFrameSize);
1413 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX))
1417 } else if (isInt16(NegFrameSize)) {
1418 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDU), PPC::X1)
1420 .addImm(NegFrameSize / 4)
1423 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0)
1424 .addImm(NegFrameSize >> 16);
1425 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0)
1426 .addReg(PPC::X0, RegState::Kill)
1427 .addImm(NegFrameSize & 0xFFFF);
1428 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX))
1435 if (needsFrameMoves) {
1436 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
1439 // Show update of SP.
1440 MachineLocation SPDst(MachineLocation::VirtualFP);
1441 MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize);
1442 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
1444 MachineLocation SP(IsPPC64 ? PPC::X31 : PPC::R31);
1445 Moves.push_back(MachineMove(FrameLabelId, SP, SP));
1449 MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset);
1450 MachineLocation FPSrc(IsPPC64 ? PPC::X31 : PPC::R31);
1451 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc));
1454 // Add callee saved registers to move list.
1455 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1456 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
1457 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
1458 unsigned Reg = CSI[I].getReg();
1459 if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue;
1460 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
1461 MachineLocation CSSrc(Reg);
1462 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
1465 MachineLocation LRDst(MachineLocation::VirtualFP, LROffset);
1466 MachineLocation LRSrc(IsPPC64 ? PPC::LR8 : PPC::LR);
1467 Moves.push_back(MachineMove(FrameLabelId, LRDst, LRSrc));
1469 // Mark effective beginning of when frame pointer is ready.
1470 unsigned ReadyLabelId = MMI->NextLabelID();
1471 BuildMI(MBB, MBBI, dl, TII.get(PPC::DBG_LABEL)).addImm(ReadyLabelId);
1473 MachineLocation FPDst(HasFP ? (IsPPC64 ? PPC::X31 : PPC::R31) :
1474 (IsPPC64 ? PPC::X1 : PPC::R1));
1475 MachineLocation FPSrc(MachineLocation::VirtualFP);
1476 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
1479 // If there is a frame pointer, copy R1 into R31
1482 BuildMI(MBB, MBBI, dl, TII.get(PPC::OR), PPC::R31)
1486 BuildMI(MBB, MBBI, dl, TII.get(PPC::OR8), PPC::X31)
1493 void PPCRegisterInfo::emitEpilogue(MachineFunction &MF,
1494 MachineBasicBlock &MBB) const {
1495 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1496 unsigned RetOpcode = MBBI->getOpcode();
1497 DebugLoc dl = DebugLoc::getUnknownLoc();
1499 assert( (RetOpcode == PPC::BLR ||
1500 RetOpcode == PPC::TCRETURNri ||
1501 RetOpcode == PPC::TCRETURNdi ||
1502 RetOpcode == PPC::TCRETURNai ||
1503 RetOpcode == PPC::TCRETURNri8 ||
1504 RetOpcode == PPC::TCRETURNdi8 ||
1505 RetOpcode == PPC::TCRETURNai8) &&
1506 "Can only insert epilog into returning blocks");
1508 // Get alignment info so we know how to restore r1
1509 const MachineFrameInfo *MFI = MF.getFrameInfo();
1510 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
1511 unsigned MaxAlign = MFI->getMaxAlignment();
1513 // Get the number of bytes allocated from the FrameInfo.
1514 int FrameSize = MFI->getStackSize();
1516 // Get processor type.
1517 bool IsPPC64 = Subtarget.isPPC64();
1518 // Get operating system
1519 bool isDarwinABI = Subtarget.isDarwinABI();
1520 // Check if the link register (LR) has been saved.
1521 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1522 bool MustSaveLR = FI->mustSaveLR();
1523 // Do we have a frame pointer for this function?
1524 bool HasFP = hasFP(MF) && FrameSize;
1526 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, isDarwinABI);
1530 if (Subtarget.isSVR4ABI()) {
1531 MachineFrameInfo *FFI = MF.getFrameInfo();
1532 int FPIndex = FI->getFramePointerSaveIndex();
1533 assert(FPIndex && "No Frame Pointer Save Slot!");
1534 FPOffset = FFI->getObjectOffset(FPIndex);
1536 FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, isDarwinABI);
1540 bool UsesTCRet = RetOpcode == PPC::TCRETURNri ||
1541 RetOpcode == PPC::TCRETURNdi ||
1542 RetOpcode == PPC::TCRETURNai ||
1543 RetOpcode == PPC::TCRETURNri8 ||
1544 RetOpcode == PPC::TCRETURNdi8 ||
1545 RetOpcode == PPC::TCRETURNai8;
1548 int MaxTCRetDelta = FI->getTailCallSPDelta();
1549 MachineOperand &StackAdjust = MBBI->getOperand(1);
1550 assert(StackAdjust.isImm() && "Expecting immediate value.");
1551 // Adjust stack pointer.
1552 int StackAdj = StackAdjust.getImm();
1553 int Delta = StackAdj - MaxTCRetDelta;
1554 assert((Delta >= 0) && "Delta must be positive");
1555 if (MaxTCRetDelta>0)
1556 FrameSize += (StackAdj +Delta);
1558 FrameSize += StackAdj;
1562 // The loaded (or persistent) stack pointer value is offset by the 'stwu'
1563 // on entry to the function. Add this offset back now.
1565 // If this function contained a fastcc call and PerformTailCallOpt is
1566 // enabled (=> hasFastCall()==true) the fastcc call might contain a tail
1567 // call which invalidates the stack pointer value in SP(0). So we use the
1568 // value of R31 in this case.
1569 if (FI->hasFastCall() && isInt16(FrameSize)) {
1570 assert(hasFP(MF) && "Expecting a valid the frame pointer.");
1571 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1)
1572 .addReg(PPC::R31).addImm(FrameSize);
1573 } else if(FI->hasFastCall()) {
1574 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0)
1575 .addImm(FrameSize >> 16);
1576 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0)
1577 .addReg(PPC::R0, RegState::Kill)
1578 .addImm(FrameSize & 0xFFFF);
1579 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD4))
1583 } else if (isInt16(FrameSize) &&
1584 (!ALIGN_STACK || TargetAlign >= MaxAlign) &&
1585 !MFI->hasVarSizedObjects()) {
1586 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1)
1587 .addReg(PPC::R1).addImm(FrameSize);
1589 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ),PPC::R1)
1590 .addImm(0).addReg(PPC::R1);
1593 if (FI->hasFastCall() && isInt16(FrameSize)) {
1594 assert(hasFP(MF) && "Expecting a valid the frame pointer.");
1595 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1)
1596 .addReg(PPC::X31).addImm(FrameSize);
1597 } else if(FI->hasFastCall()) {
1598 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0)
1599 .addImm(FrameSize >> 16);
1600 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0)
1601 .addReg(PPC::X0, RegState::Kill)
1602 .addImm(FrameSize & 0xFFFF);
1603 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD8))
1607 } else if (isInt16(FrameSize) && TargetAlign >= MaxAlign &&
1608 !MFI->hasVarSizedObjects()) {
1609 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1)
1610 .addReg(PPC::X1).addImm(FrameSize);
1612 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X1)
1613 .addImm(0).addReg(PPC::X1);
1620 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X0)
1621 .addImm(LROffset/4).addReg(PPC::X1);
1624 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X31)
1625 .addImm(FPOffset/4).addReg(PPC::X1);
1628 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR8)).addReg(PPC::X0);
1631 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R0)
1632 .addImm(LROffset).addReg(PPC::R1);
1635 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R31)
1636 .addImm(FPOffset).addReg(PPC::R1);
1639 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR)).addReg(PPC::R0);
1642 // Callee pop calling convention. Pop parameter/linkage area. Used for tail
1643 // call optimization
1644 if (PerformTailCallOpt && RetOpcode == PPC::BLR &&
1645 MF.getFunction()->getCallingConv() == CallingConv::Fast) {
1646 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1647 unsigned CallerAllocatedAmt = FI->getMinReservedArea();
1648 unsigned StackReg = IsPPC64 ? PPC::X1 : PPC::R1;
1649 unsigned FPReg = IsPPC64 ? PPC::X31 : PPC::R31;
1650 unsigned TmpReg = IsPPC64 ? PPC::X0 : PPC::R0;
1651 unsigned ADDIInstr = IsPPC64 ? PPC::ADDI8 : PPC::ADDI;
1652 unsigned ADDInstr = IsPPC64 ? PPC::ADD8 : PPC::ADD4;
1653 unsigned LISInstr = IsPPC64 ? PPC::LIS8 : PPC::LIS;
1654 unsigned ORIInstr = IsPPC64 ? PPC::ORI8 : PPC::ORI;
1656 if (CallerAllocatedAmt && isInt16(CallerAllocatedAmt)) {
1657 BuildMI(MBB, MBBI, dl, TII.get(ADDIInstr), StackReg)
1658 .addReg(StackReg).addImm(CallerAllocatedAmt);
1660 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
1661 .addImm(CallerAllocatedAmt >> 16);
1662 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
1663 .addReg(TmpReg, RegState::Kill)
1664 .addImm(CallerAllocatedAmt & 0xFFFF);
1665 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr))
1670 } else if (RetOpcode == PPC::TCRETURNdi) {
1671 MBBI = prior(MBB.end());
1672 MachineOperand &JumpTarget = MBBI->getOperand(0);
1673 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)).
1674 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1675 } else if (RetOpcode == PPC::TCRETURNri) {
1676 MBBI = prior(MBB.end());
1677 assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
1678 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR));
1679 } else if (RetOpcode == PPC::TCRETURNai) {
1680 MBBI = prior(MBB.end());
1681 MachineOperand &JumpTarget = MBBI->getOperand(0);
1682 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm());
1683 } else if (RetOpcode == PPC::TCRETURNdi8) {
1684 MBBI = prior(MBB.end());
1685 MachineOperand &JumpTarget = MBBI->getOperand(0);
1686 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)).
1687 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1688 } else if (RetOpcode == PPC::TCRETURNri8) {
1689 MBBI = prior(MBB.end());
1690 assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
1691 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8));
1692 } else if (RetOpcode == PPC::TCRETURNai8) {
1693 MBBI = prior(MBB.end());
1694 MachineOperand &JumpTarget = MBBI->getOperand(0);
1695 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm());
1699 unsigned PPCRegisterInfo::getRARegister() const {
1700 return !Subtarget.isPPC64() ? PPC::LR : PPC::LR8;
1703 unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const {
1704 if (!Subtarget.isPPC64())
1705 return hasFP(MF) ? PPC::R31 : PPC::R1;
1707 return hasFP(MF) ? PPC::X31 : PPC::X1;
1710 void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
1712 // Initial state of the frame pointer is R1.
1713 MachineLocation Dst(MachineLocation::VirtualFP);
1714 MachineLocation Src(PPC::R1, 0);
1715 Moves.push_back(MachineMove(0, Dst, Src));
1718 unsigned PPCRegisterInfo::getEHExceptionRegister() const {
1719 return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3;
1722 unsigned PPCRegisterInfo::getEHHandlerRegister() const {
1723 return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4;
1726 int PPCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
1727 // FIXME: Most probably dwarf numbers differs for Linux and Darwin
1728 return PPCGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
1731 #include "PPCGenRegisterInfo.inc"