1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetRegisterInfo
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "reginfo"
17 #include "PPCInstrBuilder.h"
18 #include "PPCMachineFunctionInfo.h"
19 #include "PPCRegisterInfo.h"
20 #include "PPCFrameInfo.h"
21 #include "PPCSubtarget.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/Function.h"
25 #include "llvm/Type.h"
26 #include "llvm/CodeGen/ValueTypes.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineModuleInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineLocation.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/RegisterScavenging.h"
34 #include "llvm/CodeGen/SelectionDAGNodes.h"
35 #include "llvm/Target/TargetFrameInfo.h"
36 #include "llvm/Target/TargetInstrInfo.h"
37 #include "llvm/Target/TargetMachine.h"
38 #include "llvm/Target/TargetOptions.h"
39 #include "llvm/Support/CommandLine.h"
40 #include "llvm/Support/Debug.h"
41 #include "llvm/Support/MathExtras.h"
42 #include "llvm/ADT/BitVector.h"
43 #include "llvm/ADT/STLExtras.h"
47 // FIXME This disables some code that aligns the stack to a boundary
48 // bigger than the default (16 bytes on Darwin) when there is a stack local
49 // of greater alignment. This does not currently work, because the delta
50 // between old and new stack pointers is added to offsets that reference
51 // incoming parameters after the prolog is generated, and the code that
52 // does that doesn't handle a variable delta. You don't want to do that
53 // anyway; a better approach is to reserve another register that retains
54 // to the incoming stack pointer, and reference parameters relative to that.
57 // FIXME (64-bit): Eventually enable by default.
58 cl::opt<bool> EnablePPC32RS("enable-ppc32-regscavenger",
60 cl::desc("Enable PPC32 register scavenger"),
62 cl::opt<bool> EnablePPC64RS("enable-ppc64-regscavenger",
64 cl::desc("Enable PPC64 register scavenger"),
66 #define EnableRegisterScavenging \
67 ((EnablePPC32RS && !Subtarget.isPPC64()) || \
68 (EnablePPC64RS && Subtarget.isPPC64()))
70 // FIXME (64-bit): Should be inlined.
72 PPCRegisterInfo::requiresRegisterScavenging(const MachineFunction &) const {
73 return EnableRegisterScavenging;
76 /// getRegisterNumbering - Given the enum value for some register, e.g.
77 /// PPC::F14, return the number that it corresponds to (e.g. 14).
78 unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
82 case R0 : case X0 : case F0 : case V0 : case CR0: case CR0LT: return 0;
83 case R1 : case X1 : case F1 : case V1 : case CR1: case CR0GT: return 1;
84 case R2 : case X2 : case F2 : case V2 : case CR2: case CR0EQ: return 2;
85 case R3 : case X3 : case F3 : case V3 : case CR3: case CR0UN: return 3;
86 case R4 : case X4 : case F4 : case V4 : case CR4: case CR1LT: return 4;
87 case R5 : case X5 : case F5 : case V5 : case CR5: case CR1GT: return 5;
88 case R6 : case X6 : case F6 : case V6 : case CR6: case CR1EQ: return 6;
89 case R7 : case X7 : case F7 : case V7 : case CR7: case CR1UN: return 7;
90 case R8 : case X8 : case F8 : case V8 : case CR2LT: return 8;
91 case R9 : case X9 : case F9 : case V9 : case CR2GT: return 9;
92 case R10: case X10: case F10: case V10: case CR2EQ: return 10;
93 case R11: case X11: case F11: case V11: case CR2UN: return 11;
94 case R12: case X12: case F12: case V12: case CR3LT: return 12;
95 case R13: case X13: case F13: case V13: case CR3GT: return 13;
96 case R14: case X14: case F14: case V14: case CR3EQ: return 14;
97 case R15: case X15: case F15: case V15: case CR3UN: return 15;
98 case R16: case X16: case F16: case V16: case CR4LT: return 16;
99 case R17: case X17: case F17: case V17: case CR4GT: return 17;
100 case R18: case X18: case F18: case V18: case CR4EQ: return 18;
101 case R19: case X19: case F19: case V19: case CR4UN: return 19;
102 case R20: case X20: case F20: case V20: case CR5LT: return 20;
103 case R21: case X21: case F21: case V21: case CR5GT: return 21;
104 case R22: case X22: case F22: case V22: case CR5EQ: return 22;
105 case R23: case X23: case F23: case V23: case CR5UN: return 23;
106 case R24: case X24: case F24: case V24: case CR6LT: return 24;
107 case R25: case X25: case F25: case V25: case CR6GT: return 25;
108 case R26: case X26: case F26: case V26: case CR6EQ: return 26;
109 case R27: case X27: case F27: case V27: case CR6UN: return 27;
110 case R28: case X28: case F28: case V28: case CR7LT: return 28;
111 case R29: case X29: case F29: case V29: case CR7GT: return 29;
112 case R30: case X30: case F30: case V30: case CR7EQ: return 30;
113 case R31: case X31: case F31: case V31: case CR7UN: return 31;
115 cerr << "Unhandled reg in PPCRegisterInfo::getRegisterNumbering!\n";
120 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST,
121 const TargetInstrInfo &tii)
122 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
123 Subtarget(ST), TII(tii) {
124 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
125 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
126 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
127 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
128 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
129 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
130 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
131 ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
134 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8;
135 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8;
136 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8;
137 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX;
138 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32;
142 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
143 // 32-bit Darwin calling convention.
144 static const unsigned Macho32_CalleeSavedRegs[] = {
145 PPC::R13, PPC::R14, PPC::R15,
146 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
147 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
148 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
149 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
151 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
152 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
153 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
154 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
157 PPC::CR2, PPC::CR3, PPC::CR4,
158 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
159 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
160 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
162 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
163 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
164 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
169 static const unsigned ELF32_CalleeSavedRegs[] = {
170 PPC::R13, PPC::R14, PPC::R15,
171 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
172 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
173 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
174 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
177 PPC::F10, PPC::F11, PPC::F12, PPC::F13,
178 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
179 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
180 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
181 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
184 PPC::CR2, PPC::CR3, PPC::CR4,
185 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
186 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
187 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
189 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
190 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
191 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
195 // 64-bit Darwin calling convention.
196 static const unsigned Macho64_CalleeSavedRegs[] = {
198 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
199 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
200 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
201 PPC::X28, PPC::X29, PPC::X30, PPC::X31,
203 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
204 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
205 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
206 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
209 PPC::CR2, PPC::CR3, PPC::CR4,
210 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
211 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
212 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
214 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
215 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
216 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
221 if (Subtarget.isMachoABI())
222 return Subtarget.isPPC64() ? Macho64_CalleeSavedRegs :
223 Macho32_CalleeSavedRegs;
226 return ELF32_CalleeSavedRegs;
229 const TargetRegisterClass* const*
230 PPCRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
231 // 32-bit Macho calling convention.
232 static const TargetRegisterClass * const Macho32_CalleeSavedRegClasses[] = {
233 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
234 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
235 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
236 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
237 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
239 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
240 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
241 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
242 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
243 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
245 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
247 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
248 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
249 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
251 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
252 &PPC::CRBITRCRegClass,
253 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
254 &PPC::CRBITRCRegClass,
255 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
256 &PPC::CRBITRCRegClass,
258 &PPC::GPRCRegClass, 0
261 static const TargetRegisterClass * const ELF32_CalleeSavedRegClasses[] = {
262 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
263 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
264 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
265 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
266 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
269 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
270 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
271 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
272 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
273 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
274 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
276 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
278 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
279 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
280 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
282 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
283 &PPC::CRBITRCRegClass,
284 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
285 &PPC::CRBITRCRegClass,
286 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
287 &PPC::CRBITRCRegClass,
289 &PPC::GPRCRegClass, 0
292 // 64-bit Macho calling convention.
293 static const TargetRegisterClass * const Macho64_CalleeSavedRegClasses[] = {
294 &PPC::G8RCRegClass,&PPC::G8RCRegClass,
295 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
296 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
297 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
298 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
300 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
301 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
302 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
303 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
304 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
306 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
308 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
309 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
310 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
312 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
313 &PPC::CRBITRCRegClass,
314 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
315 &PPC::CRBITRCRegClass,
316 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
317 &PPC::CRBITRCRegClass,
319 &PPC::G8RCRegClass, 0
322 if (Subtarget.isMachoABI())
323 return Subtarget.isPPC64() ? Macho64_CalleeSavedRegClasses :
324 Macho32_CalleeSavedRegClasses;
327 return ELF32_CalleeSavedRegClasses;
330 // needsFP - Return true if the specified function should have a dedicated frame
331 // pointer register. This is true if the function has variable sized allocas or
332 // if frame pointer elimination is disabled.
334 static bool needsFP(const MachineFunction &MF) {
335 const MachineFrameInfo *MFI = MF.getFrameInfo();
336 return NoFramePointerElim || MFI->hasVarSizedObjects() ||
337 (PerformTailCallOpt && MF.getInfo<PPCFunctionInfo>()->hasFastCall());
340 static bool spillsCR(const MachineFunction &MF) {
341 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
342 return FuncInfo->isCRSpilled();
345 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
346 BitVector Reserved(getNumRegs());
347 Reserved.set(PPC::R0);
348 Reserved.set(PPC::R1);
349 Reserved.set(PPC::LR);
350 Reserved.set(PPC::LR8);
352 // In Linux, r2 is reserved for the OS.
353 if (!Subtarget.isDarwin())
354 Reserved.set(PPC::R2);
356 // On PPC64, r13 is the thread pointer. Never allocate this register. Note
357 // that this is over conservative, as it also prevents allocation of R31 when
358 // the FP is not needed.
359 if (Subtarget.isPPC64()) {
360 Reserved.set(PPC::R13);
361 Reserved.set(PPC::R31);
363 if (!EnableRegisterScavenging)
364 Reserved.set(PPC::R0); // FIXME (64-bit): Remove
366 Reserved.set(PPC::X0);
367 Reserved.set(PPC::X1);
368 Reserved.set(PPC::X13);
369 Reserved.set(PPC::X31);
373 Reserved.set(PPC::R31);
378 //===----------------------------------------------------------------------===//
379 // Stack Frame Processing methods
380 //===----------------------------------------------------------------------===//
382 // hasFP - Return true if the specified function actually has a dedicated frame
383 // pointer register. This is true if the function needs a frame pointer and has
384 // a non-zero stack size.
385 bool PPCRegisterInfo::hasFP(const MachineFunction &MF) const {
386 const MachineFrameInfo *MFI = MF.getFrameInfo();
387 return MFI->getStackSize() && needsFP(MF);
390 /// MustSaveLR - Return true if this function requires that we save the LR
391 /// register onto the stack in the prolog and restore it in the epilog of the
393 static bool MustSaveLR(const MachineFunction &MF) {
394 const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>();
396 // We need an save/restore of LR if there is any use/def of LR explicitly, or
397 // if there is some use of the LR stack slot (e.g. for builtin_return_address.
398 return MFI->usesLR() || MFI->isLRStoreRequired() ||
399 // FIXME: Anything that has a call should clobber the LR register,
400 // isn't this redundant??
401 MF.getFrameInfo()->hasCalls();
406 void PPCRegisterInfo::
407 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
408 MachineBasicBlock::iterator I) const {
409 if (PerformTailCallOpt && I->getOpcode() == PPC::ADJCALLSTACKUP) {
410 // Add (actually substract) back the amount the callee popped on return.
411 if (int CalleeAmt = I->getOperand(1).getImm()) {
412 MachineInstr * New = NULL;
413 bool is64Bit = Subtarget.isPPC64();
415 unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1;
416 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0;
417 unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI;
418 unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4;
419 unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS;
420 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI;
422 if (isInt16(CalleeAmt)) {
423 New = BuildMI(TII.get(ADDIInstr), StackReg).addReg(StackReg).
427 MachineBasicBlock::iterator MBBI = I;
428 BuildMI(MBB, MBBI, TII.get(LISInstr), TmpReg)
429 .addImm(CalleeAmt >> 16);
430 BuildMI(MBB, MBBI, TII.get(ORIInstr), TmpReg)
431 .addReg(TmpReg, false, false, true)
432 .addImm(CalleeAmt & 0xFFFF);
433 BuildMI(MBB, MBBI, TII.get(ADDInstr))
440 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
444 /// findScratchRegister - Find a 'free' PPC register. Try for a call-clobbered
445 /// register first and then a spilled callee-saved register if that fails.
447 unsigned findScratchRegister(MachineBasicBlock::iterator II, RegScavenger *RS,
448 const TargetRegisterClass *RC, int SPAdj) {
449 assert(RS && "Register scavenging must be on");
450 unsigned Reg = RS->FindUnusedReg(RC, true);
451 // FIXME: move ARM callee-saved reg scan to target independent code, then
452 // search for already spilled CS register here.
454 Reg = RS->scavengeRegister(RC, II, SPAdj);
458 /// lowerDynamicAlloc - Generate the code for allocating an object in the
459 /// current frame. The sequence of code with be in the general form
461 /// addi R0, SP, #frameSize ; get the address of the previous frame
462 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size
463 /// addi Rnew, SP, #maxCalFrameSize ; get the top of the allocation
465 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II,
466 int SPAdj, RegScavenger *RS) const {
467 // Get the instruction.
468 MachineInstr &MI = *II;
469 // Get the instruction's basic block.
470 MachineBasicBlock &MBB = *MI.getParent();
471 // Get the basic block's function.
472 MachineFunction &MF = *MBB.getParent();
473 // Get the frame info.
474 MachineFrameInfo *MFI = MF.getFrameInfo();
475 // Determine whether 64-bit pointers are used.
476 bool LP64 = Subtarget.isPPC64();
478 // Get the maximum call stack size.
479 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
480 // Get the total frame size.
481 unsigned FrameSize = MFI->getStackSize();
483 // Get stack alignments.
484 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
485 unsigned MaxAlign = MFI->getMaxAlignment();
486 assert(MaxAlign <= TargetAlign &&
487 "Dynamic alloca with large aligns not supported");
489 // Determine the previous frame's address. If FrameSize can't be
490 // represented as 16 bits or we need special alignment, then we load the
491 // previous frame's address from 0(SP). Why not do an addis of the hi?
492 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
493 // Constructing the constant and adding would take 3 instructions.
494 // Fortunately, a frame greater than 32K is rare.
495 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
496 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
497 const TargetRegisterClass *RC = LP64 ? G8RC : GPRC;
499 // FIXME (64-bit): Use "findScratchRegister"
501 if (EnableRegisterScavenging)
502 Reg = findScratchRegister(II, RS, RC, SPAdj);
506 if (MaxAlign < TargetAlign && isInt16(FrameSize)) {
507 BuildMI(MBB, II, TII.get(PPC::ADDI), Reg)
511 if (EnableRegisterScavenging) // FIXME (64-bit): Use "true" part.
512 BuildMI(MBB, II, TII.get(PPC::LD), Reg)
516 BuildMI(MBB, II, TII.get(PPC::LD), PPC::X0)
520 BuildMI(MBB, II, TII.get(PPC::LWZ), Reg)
525 // Grow the stack and update the stack pointer link, then determine the
526 // address of new allocated space.
528 if (EnableRegisterScavenging) // FIXME (64-bit): Use "true" part.
529 BuildMI(MBB, II, TII.get(PPC::STDUX))
530 .addReg(Reg, false, false, true)
532 .addReg(MI.getOperand(1).getReg());
534 BuildMI(MBB, II, TII.get(PPC::STDUX))
535 .addReg(PPC::X0, false, false, true)
537 .addReg(MI.getOperand(1).getReg());
539 if (!MI.getOperand(1).isKill())
540 BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
542 .addImm(maxCallFrameSize);
544 // Implicitly kill the register.
545 BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
547 .addImm(maxCallFrameSize)
548 .addReg(MI.getOperand(1).getReg(), false, true, true);
550 BuildMI(MBB, II, TII.get(PPC::STWUX))
551 .addReg(Reg, false, false, true)
553 .addReg(MI.getOperand(1).getReg());
555 if (!MI.getOperand(1).isKill())
556 BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
558 .addImm(maxCallFrameSize);
560 // Implicitly kill the register.
561 BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
563 .addImm(maxCallFrameSize)
564 .addReg(MI.getOperand(1).getReg(), false, true, true);
567 // Discard the DYNALLOC instruction.
571 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of
572 /// reserving a whole register (R0), we scrounge for one here. This generates
575 /// mfcr rA ; Move the conditional register into GPR rA.
576 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot.
577 /// stw rA, FI ; Store rA to the frame.
579 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II,
580 unsigned FrameIndex, int SPAdj,
581 RegScavenger *RS) const {
582 // Get the instruction.
583 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>, <FI>
584 // Get the instruction's basic block.
585 MachineBasicBlock &MBB = *MI.getParent();
587 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
588 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
589 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC;
590 unsigned Reg = findScratchRegister(II, RS, RC, SPAdj);
592 // We need to store the CR in the low 4-bits of the saved value. First, issue
593 // an MFCR to save all of the CRBits. Add an implicit kill of the CR.
594 if (!MI.getOperand(0).isKill())
595 BuildMI(MBB, II, TII.get(PPC::MFCR), Reg);
597 // Implicitly kill the CR register.
598 BuildMI(MBB, II, TII.get(PPC::MFCR), Reg)
599 .addReg(MI.getOperand(0).getReg(), false, true, true);
601 // If the saved register wasn't CR0, shift the bits left so that they are in
603 unsigned SrcReg = MI.getOperand(0).getReg();
604 if (SrcReg != PPC::CR0)
605 // rlwinm rA, rA, ShiftBits, 0, 31.
606 BuildMI(MBB, II, TII.get(PPC::RLWINM), Reg)
607 .addReg(Reg, false, false, true)
608 .addImm(PPCRegisterInfo::getRegisterNumbering(SrcReg) * 4)
612 addFrameReference(BuildMI(MBB, II, TII.get(PPC::STW))
613 .addReg(Reg, false, false, MI.getOperand(1).getImm()),
616 // Discard the pseudo instruction.
620 void PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
621 int SPAdj, RegScavenger *RS) const {
622 assert(SPAdj == 0 && "Unexpected");
624 // Get the instruction.
625 MachineInstr &MI = *II;
626 // Get the instruction's basic block.
627 MachineBasicBlock &MBB = *MI.getParent();
628 // Get the basic block's function.
629 MachineFunction &MF = *MBB.getParent();
630 // Get the frame info.
631 MachineFrameInfo *MFI = MF.getFrameInfo();
633 // Find out which operand is the frame index.
634 unsigned FIOperandNo = 0;
635 while (!MI.getOperand(FIOperandNo).isFrameIndex()) {
637 assert(FIOperandNo != MI.getNumOperands() &&
638 "Instr doesn't have FrameIndex operand!");
640 // Take into account whether it's an add or mem instruction
641 unsigned OffsetOperandNo = (FIOperandNo == 2) ? 1 : 2;
642 if (MI.getOpcode() == TargetInstrInfo::INLINEASM)
643 OffsetOperandNo = FIOperandNo-1;
645 // Get the frame index.
646 int FrameIndex = MI.getOperand(FIOperandNo).getIndex();
648 // Get the frame pointer save index. Users of this index are primarily
649 // DYNALLOC instructions.
650 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
651 int FPSI = FI->getFramePointerSaveIndex();
652 // Get the instruction opcode.
653 unsigned OpC = MI.getOpcode();
655 // Special case for dynamic alloca.
656 if (FPSI && FrameIndex == FPSI &&
657 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
658 lowerDynamicAlloc(II, SPAdj, RS);
662 // Special case for pseudo-op SPILL_CR.
663 if (EnableRegisterScavenging) // FIXME (64-bit): Enable by default.
664 if (OpC == PPC::SPILL_CR) {
665 lowerCRSpilling(II, FrameIndex, SPAdj, RS);
669 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
670 MI.getOperand(FIOperandNo).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1,
673 // Figure out if the offset in the instruction is shifted right two bits. This
674 // is true for instructions like "STD", which the machine implicitly adds two
676 bool isIXAddr = false;
686 // Now add the frame object offset to the offset from r1.
687 int Offset = MFI->getObjectOffset(FrameIndex);
689 Offset += MI.getOperand(OffsetOperandNo).getImm();
691 Offset += MI.getOperand(OffsetOperandNo).getImm() << 2;
693 // If we're not using a Frame Pointer that has been set to the value of the
694 // SP before having the stack size subtracted from it, then add the stack size
695 // to Offset to get the correct offset.
696 Offset += MFI->getStackSize();
698 // If we can, encode the offset directly into the instruction. If this is a
699 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If
700 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits
701 // clear can be encoded. This is extremely uncommon, because normally you
702 // only "std" to a stack slot that is at least 4-byte aligned, but it can
703 // happen in invalid code.
704 if (isInt16(Offset) && (!isIXAddr || (Offset & 3) == 0)) {
706 Offset >>= 2; // The actual encoded value has the low two bits zero.
707 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
711 // The offset doesn't fit into a single register, scavenge one to build the
713 // FIXME: figure out what SPAdj is doing here.
715 // FIXME (64-bit): Use "findScratchRegister".
717 if (EnableRegisterScavenging)
718 SReg = findScratchRegister(II, RS, &PPC::GPRCRegClass, SPAdj);
722 // Insert a set of rA with the full offset value before the ld, st, or add
723 BuildMI(MBB, II, TII.get(PPC::LIS), SReg)
724 .addImm(Offset >> 16);
725 BuildMI(MBB, II, TII.get(PPC::ORI), SReg)
726 .addReg(SReg, false, false, true)
729 // Convert into indexed form of the instruction:
731 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
732 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
733 unsigned OperandBase;
735 if (OpC != TargetInstrInfo::INLINEASM) {
736 assert(ImmToIdxMap.count(OpC) &&
737 "No indexed form of load or store available!");
738 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second;
739 MI.setDesc(TII.get(NewOpcode));
742 OperandBase = OffsetOperandNo;
745 unsigned StackReg = MI.getOperand(FIOperandNo).getReg();
746 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false);
747 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false);
750 /// VRRegNo - Map from a numbered VR register to its enum value.
752 static const unsigned short VRRegNo[] = {
753 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
754 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
755 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
756 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
759 /// RemoveVRSaveCode - We have found that this function does not need any code
760 /// to manipulate the VRSAVE register, even though it uses vector registers.
761 /// This can happen when the only registers used are known to be live in or out
762 /// of the function. Remove all of the VRSAVE related code from the function.
763 static void RemoveVRSaveCode(MachineInstr *MI) {
764 MachineBasicBlock *Entry = MI->getParent();
765 MachineFunction *MF = Entry->getParent();
767 // We know that the MTVRSAVE instruction immediately follows MI. Remove it.
768 MachineBasicBlock::iterator MBBI = MI;
770 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
771 MBBI->eraseFromParent();
773 bool RemovedAllMTVRSAVEs = true;
774 // See if we can find and remove the MTVRSAVE instruction from all of the
776 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
777 // If last instruction is a return instruction, add an epilogue
778 if (!I->empty() && I->back().getDesc().isReturn()) {
779 bool FoundIt = false;
780 for (MBBI = I->end(); MBBI != I->begin(); ) {
782 if (MBBI->getOpcode() == PPC::MTVRSAVE) {
783 MBBI->eraseFromParent(); // remove it.
788 RemovedAllMTVRSAVEs &= FoundIt;
792 // If we found and removed all MTVRSAVE instructions, remove the read of
794 if (RemovedAllMTVRSAVEs) {
796 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
798 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
799 MBBI->eraseFromParent();
802 // Finally, nuke the UPDATE_VRSAVE.
803 MI->eraseFromParent();
806 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
807 // instruction selector. Based on the vector registers that have been used,
808 // transform this into the appropriate ORI instruction.
809 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) {
810 MachineFunction *MF = MI->getParent()->getParent();
812 unsigned UsedRegMask = 0;
813 for (unsigned i = 0; i != 32; ++i)
814 if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i]))
815 UsedRegMask |= 1 << (31-i);
817 // Live in and live out values already must be in the mask, so don't bother
819 for (MachineRegisterInfo::livein_iterator
820 I = MF->getRegInfo().livein_begin(),
821 E = MF->getRegInfo().livein_end(); I != E; ++I) {
822 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first);
823 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg.
824 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
826 for (MachineRegisterInfo::liveout_iterator
827 I = MF->getRegInfo().liveout_begin(),
828 E = MF->getRegInfo().liveout_end(); I != E; ++I) {
829 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I);
830 if (VRRegNo[RegNo] == *I) // If this really is a vector reg.
831 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
834 // If no registers are used, turn this into a copy.
835 if (UsedRegMask == 0) {
836 // Remove all VRSAVE code.
837 RemoveVRSaveCode(MI);
841 unsigned SrcReg = MI->getOperand(1).getReg();
842 unsigned DstReg = MI->getOperand(0).getReg();
844 if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
845 if (DstReg != SrcReg)
846 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg)
848 .addImm(UsedRegMask);
850 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg)
851 .addReg(SrcReg, false, false, true)
852 .addImm(UsedRegMask);
853 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
854 if (DstReg != SrcReg)
855 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
857 .addImm(UsedRegMask >> 16);
859 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
860 .addReg(SrcReg, false, false, true)
861 .addImm(UsedRegMask >> 16);
863 if (DstReg != SrcReg)
864 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
866 .addImm(UsedRegMask >> 16);
868 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
869 .addReg(SrcReg, false, false, true)
870 .addImm(UsedRegMask >> 16);
872 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg)
873 .addReg(DstReg, false, false, true)
874 .addImm(UsedRegMask & 0xFFFF);
877 // Remove the old UPDATE_VRSAVE instruction.
878 MI->eraseFromParent();
881 /// determineFrameLayout - Determine the size of the frame and maximum call
883 void PPCRegisterInfo::determineFrameLayout(MachineFunction &MF) const {
884 MachineFrameInfo *MFI = MF.getFrameInfo();
886 // Get the number of bytes to allocate from the FrameInfo
887 unsigned FrameSize = MFI->getStackSize();
889 // Get the alignments provided by the target, and the maximum alignment
890 // (if any) of the fixed frame objects.
891 unsigned MaxAlign = MFI->getMaxAlignment();
892 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
893 unsigned AlignMask = TargetAlign - 1; //
895 // If we are a leaf function, and use up to 224 bytes of stack space,
896 // don't have a frame pointer, calls, or dynamic alloca then we do not need
897 // to adjust the stack pointer (we fit in the Red Zone).
898 if (FrameSize <= 224 && // Fits in red zone.
899 !MFI->hasVarSizedObjects() && // No dynamic alloca.
900 !MFI->hasCalls() && // No calls.
901 (!ALIGN_STACK || MaxAlign <= TargetAlign)) { // No special alignment.
903 MFI->setStackSize(0);
907 // Get the maximum call frame size of all the calls.
908 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
910 // Maximum call frame needs to be at least big enough for linkage and 8 args.
911 unsigned minCallFrameSize =
912 PPCFrameInfo::getMinCallFrameSize(Subtarget.isPPC64(),
913 Subtarget.isMachoABI());
914 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
916 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
917 // that allocations will be aligned.
918 if (MFI->hasVarSizedObjects())
919 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
921 // Update maximum call frame size.
922 MFI->setMaxCallFrameSize(maxCallFrameSize);
924 // Include call frame size in total.
925 FrameSize += maxCallFrameSize;
927 // Make sure the frame is aligned.
928 FrameSize = (FrameSize + AlignMask) & ~AlignMask;
930 // Update frame info.
931 MFI->setStackSize(FrameSize);
935 PPCRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
936 RegScavenger *RS) const {
937 // Save and clear the LR state.
938 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
939 unsigned LR = getRARegister();
940 FI->setUsesLR(MF.getRegInfo().isPhysRegUsed(LR));
941 MF.getRegInfo().setPhysRegUnused(LR);
943 // Save R31 if necessary
944 int FPSI = FI->getFramePointerSaveIndex();
945 bool IsPPC64 = Subtarget.isPPC64();
946 bool IsELF32_ABI = Subtarget.isELF32_ABI();
947 bool IsMachoABI = Subtarget.isMachoABI();
948 MachineFrameInfo *MFI = MF.getFrameInfo();
950 // If the frame pointer save index hasn't been defined yet.
951 if (!FPSI && (NoFramePointerElim || MFI->hasVarSizedObjects()) &&
953 // Find out what the fix offset of the frame pointer save area.
954 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64,
956 // Allocate the frame index for frame pointer save area.
957 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset);
959 FI->setFramePointerSaveIndex(FPSI);
962 // Reserve stack space to move the linkage area to in case of a tail call.
964 if (PerformTailCallOpt && (TCSPDelta=FI->getTailCallSPDelta()) < 0) {
965 int AddFPOffsetAmount = IsELF32_ABI ? -4 : 0;
966 MF.getFrameInfo()->CreateFixedObject( -1 * TCSPDelta,
967 AddFPOffsetAmount + TCSPDelta);
969 // Reserve a slot closest to SP or frame pointer if we have a dynalloc or
970 // a large stack, which will require scavenging a register to materialize a
972 // FIXME: this doesn't actually check stack size, so is a bit pessimistic
973 // FIXME: doesn't detect whether or not we need to spill vXX, which requires
976 if (EnableRegisterScavenging) // FIXME (64-bit): Enable.
977 if (needsFP(MF) || spillsCR(MF)) {
978 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
979 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
980 const TargetRegisterClass *RC = IsPPC64 ? G8RC : GPRC;
981 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
982 RC->getAlignment()));
987 PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
988 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
989 MachineBasicBlock::iterator MBBI = MBB.begin();
990 MachineFrameInfo *MFI = MF.getFrameInfo();
991 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
992 bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) ||
993 !MF.getFunction()->doesNotThrow() ||
994 UnwindTablesMandatory;
996 // Prepare for frame info.
997 unsigned FrameLabelId = 0;
999 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
1001 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
1002 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
1003 HandleVRSaveUpdate(MBBI, TII);
1008 // Move MBBI back to the beginning of the function.
1011 // Work out frame sizes.
1012 determineFrameLayout(MF);
1013 unsigned FrameSize = MFI->getStackSize();
1015 int NegFrameSize = -FrameSize;
1017 // Get processor type.
1018 bool IsPPC64 = Subtarget.isPPC64();
1019 // Get operating system
1020 bool IsMachoABI = Subtarget.isMachoABI();
1021 // Check if the link register (LR) has been used.
1022 bool UsesLR = MustSaveLR(MF);
1023 // Do we have a frame pointer for this function?
1024 bool HasFP = hasFP(MF) && FrameSize;
1026 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI);
1027 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI);
1031 BuildMI(MBB, MBBI, TII.get(PPC::MFLR8), PPC::X0);
1034 BuildMI(MBB, MBBI, TII.get(PPC::STD))
1040 BuildMI(MBB, MBBI, TII.get(PPC::STD))
1042 .addImm(LROffset / 4)
1046 BuildMI(MBB, MBBI, TII.get(PPC::MFLR), PPC::R0);
1049 BuildMI(MBB, MBBI, TII.get(PPC::STW))
1055 BuildMI(MBB, MBBI, TII.get(PPC::STW))
1061 // Skip if a leaf routine.
1062 if (!FrameSize) return;
1064 // Get stack alignments.
1065 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
1066 unsigned MaxAlign = MFI->getMaxAlignment();
1068 if (needsFrameMoves) {
1069 // Mark effective beginning of when frame pointer becomes valid.
1070 FrameLabelId = MMI->NextLabelID();
1071 BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(FrameLabelId).addImm(0);
1074 // Adjust stack pointer: r1 += NegFrameSize.
1075 // If there is a preferred stack alignment, align R1 now
1078 if (ALIGN_STACK && MaxAlign > TargetAlign) {
1079 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!");
1080 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!");
1082 BuildMI(MBB, MBBI, TII.get(PPC::RLWINM), PPC::R0)
1085 .addImm(32 - Log2_32(MaxAlign))
1087 BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC) ,PPC::R0)
1088 .addReg(PPC::R0, false, false, true)
1089 .addImm(NegFrameSize);
1090 BuildMI(MBB, MBBI, TII.get(PPC::STWUX))
1094 } else if (isInt16(NegFrameSize)) {
1095 BuildMI(MBB, MBBI, TII.get(PPC::STWU), PPC::R1)
1097 .addImm(NegFrameSize)
1100 BuildMI(MBB, MBBI, TII.get(PPC::LIS), PPC::R0)
1101 .addImm(NegFrameSize >> 16);
1102 BuildMI(MBB, MBBI, TII.get(PPC::ORI), PPC::R0)
1103 .addReg(PPC::R0, false, false, true)
1104 .addImm(NegFrameSize & 0xFFFF);
1105 BuildMI(MBB, MBBI, TII.get(PPC::STWUX))
1111 if (ALIGN_STACK && MaxAlign > TargetAlign) {
1112 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!");
1113 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!");
1115 BuildMI(MBB, MBBI, TII.get(PPC::RLDICL), PPC::X0)
1118 .addImm(64 - Log2_32(MaxAlign));
1119 BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC8), PPC::X0)
1121 .addImm(NegFrameSize);
1122 BuildMI(MBB, MBBI, TII.get(PPC::STDUX))
1126 } else if (isInt16(NegFrameSize)) {
1127 BuildMI(MBB, MBBI, TII.get(PPC::STDU), PPC::X1)
1129 .addImm(NegFrameSize / 4)
1132 BuildMI(MBB, MBBI, TII.get(PPC::LIS8), PPC::X0)
1133 .addImm(NegFrameSize >> 16);
1134 BuildMI(MBB, MBBI, TII.get(PPC::ORI8), PPC::X0)
1135 .addReg(PPC::X0, false, false, true)
1136 .addImm(NegFrameSize & 0xFFFF);
1137 BuildMI(MBB, MBBI, TII.get(PPC::STDUX))
1144 if (needsFrameMoves) {
1145 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
1148 // Show update of SP.
1149 MachineLocation SPDst(MachineLocation::VirtualFP);
1150 MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize);
1151 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
1153 MachineLocation SP(IsPPC64 ? PPC::X31 : PPC::R31);
1154 Moves.push_back(MachineMove(FrameLabelId, SP, SP));
1158 MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset);
1159 MachineLocation FPSrc(IsPPC64 ? PPC::X31 : PPC::R31);
1160 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc));
1163 // Add callee saved registers to move list.
1164 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1165 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
1166 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
1167 unsigned Reg = CSI[I].getReg();
1168 if (Reg == PPC::LR || Reg == PPC::LR8) continue;
1169 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
1170 MachineLocation CSSrc(Reg);
1171 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
1174 MachineLocation LRDst(MachineLocation::VirtualFP, LROffset);
1175 MachineLocation LRSrc(IsPPC64 ? PPC::LR8 : PPC::LR);
1176 Moves.push_back(MachineMove(FrameLabelId, LRDst, LRSrc));
1178 // Mark effective beginning of when frame pointer is ready.
1179 unsigned ReadyLabelId = MMI->NextLabelID();
1180 BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(ReadyLabelId).addImm(0);
1182 MachineLocation FPDst(HasFP ? (IsPPC64 ? PPC::X31 : PPC::R31) :
1183 (IsPPC64 ? PPC::X1 : PPC::R1));
1184 MachineLocation FPSrc(MachineLocation::VirtualFP);
1185 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
1188 // If there is a frame pointer, copy R1 into R31
1191 BuildMI(MBB, MBBI, TII.get(PPC::OR), PPC::R31)
1195 BuildMI(MBB, MBBI, TII.get(PPC::OR8), PPC::X31)
1202 void PPCRegisterInfo::emitEpilogue(MachineFunction &MF,
1203 MachineBasicBlock &MBB) const {
1204 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1205 unsigned RetOpcode = MBBI->getOpcode();
1207 assert( (RetOpcode == PPC::BLR ||
1208 RetOpcode == PPC::TCRETURNri ||
1209 RetOpcode == PPC::TCRETURNdi ||
1210 RetOpcode == PPC::TCRETURNai ||
1211 RetOpcode == PPC::TCRETURNri8 ||
1212 RetOpcode == PPC::TCRETURNdi8 ||
1213 RetOpcode == PPC::TCRETURNai8) &&
1214 "Can only insert epilog into returning blocks");
1216 // Get alignment info so we know how to restore r1
1217 const MachineFrameInfo *MFI = MF.getFrameInfo();
1218 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
1219 unsigned MaxAlign = MFI->getMaxAlignment();
1221 // Get the number of bytes allocated from the FrameInfo.
1222 int FrameSize = MFI->getStackSize();
1224 // Get processor type.
1225 bool IsPPC64 = Subtarget.isPPC64();
1226 // Get operating system
1227 bool IsMachoABI = Subtarget.isMachoABI();
1228 // Check if the link register (LR) has been used.
1229 bool UsesLR = MustSaveLR(MF);
1230 // Do we have a frame pointer for this function?
1231 bool HasFP = hasFP(MF) && FrameSize;
1233 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI);
1234 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI);
1236 bool UsesTCRet = RetOpcode == PPC::TCRETURNri ||
1237 RetOpcode == PPC::TCRETURNdi ||
1238 RetOpcode == PPC::TCRETURNai ||
1239 RetOpcode == PPC::TCRETURNri8 ||
1240 RetOpcode == PPC::TCRETURNdi8 ||
1241 RetOpcode == PPC::TCRETURNai8;
1243 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1246 int MaxTCRetDelta = FI->getTailCallSPDelta();
1247 MachineOperand &StackAdjust = MBBI->getOperand(1);
1248 assert( StackAdjust.isImmediate() && "Expecting immediate value.");
1249 // Adjust stack pointer.
1250 int StackAdj = StackAdjust.getImm();
1251 int Delta = StackAdj - MaxTCRetDelta;
1252 assert((Delta >= 0) && "Delta must be positive");
1253 if (MaxTCRetDelta>0)
1254 FrameSize += (StackAdj +Delta);
1256 FrameSize += StackAdj;
1260 // The loaded (or persistent) stack pointer value is offset by the 'stwu'
1261 // on entry to the function. Add this offset back now.
1263 // If this function contained a fastcc call and PerformTailCallOpt is
1264 // enabled (=> hasFastCall()==true) the fastcc call might contain a tail
1265 // call which invalidates the stack pointer value in SP(0). So we use the
1266 // value of R31 in this case.
1267 if (FI->hasFastCall() && isInt16(FrameSize)) {
1268 assert(hasFP(MF) && "Expecting a valid the frame pointer.");
1269 BuildMI(MBB, MBBI, TII.get(PPC::ADDI), PPC::R1)
1270 .addReg(PPC::R31).addImm(FrameSize);
1271 } else if(FI->hasFastCall()) {
1272 BuildMI(MBB, MBBI, TII.get(PPC::LIS), PPC::R0)
1273 .addImm(FrameSize >> 16);
1274 BuildMI(MBB, MBBI, TII.get(PPC::ORI), PPC::R0)
1275 .addReg(PPC::R0, false, false, true)
1276 .addImm(FrameSize & 0xFFFF);
1277 BuildMI(MBB, MBBI, TII.get(PPC::ADD4))
1281 } else if (isInt16(FrameSize) &&
1282 (!ALIGN_STACK || TargetAlign >= MaxAlign) &&
1283 !MFI->hasVarSizedObjects()) {
1284 BuildMI(MBB, MBBI, TII.get(PPC::ADDI), PPC::R1)
1285 .addReg(PPC::R1).addImm(FrameSize);
1287 BuildMI(MBB, MBBI, TII.get(PPC::LWZ),PPC::R1).addImm(0).addReg(PPC::R1);
1290 if (FI->hasFastCall() && isInt16(FrameSize)) {
1291 assert(hasFP(MF) && "Expecting a valid the frame pointer.");
1292 BuildMI(MBB, MBBI, TII.get(PPC::ADDI8), PPC::X1)
1293 .addReg(PPC::X31).addImm(FrameSize);
1294 } else if(FI->hasFastCall()) {
1295 BuildMI(MBB, MBBI, TII.get(PPC::LIS8), PPC::X0)
1296 .addImm(FrameSize >> 16);
1297 BuildMI(MBB, MBBI, TII.get(PPC::ORI8), PPC::X0)
1298 .addReg(PPC::X0, false, false, true)
1299 .addImm(FrameSize & 0xFFFF);
1300 BuildMI(MBB, MBBI, TII.get(PPC::ADD8))
1304 } else if (isInt16(FrameSize) && TargetAlign >= MaxAlign &&
1305 !MFI->hasVarSizedObjects()) {
1306 BuildMI(MBB, MBBI, TII.get(PPC::ADDI8), PPC::X1)
1307 .addReg(PPC::X1).addImm(FrameSize);
1309 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X1).addImm(0).addReg(PPC::X1);
1316 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X0)
1317 .addImm(LROffset/4).addReg(PPC::X1);
1320 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X31)
1321 .addImm(FPOffset/4).addReg(PPC::X1);
1324 BuildMI(MBB, MBBI, TII.get(PPC::MTLR8)).addReg(PPC::X0);
1327 BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R0)
1328 .addImm(LROffset).addReg(PPC::R1);
1331 BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R31)
1332 .addImm(FPOffset).addReg(PPC::R1);
1335 BuildMI(MBB, MBBI, TII.get(PPC::MTLR)).addReg(PPC::R0);
1338 // Callee pop calling convention. Pop parameter/linkage area. Used for tail
1339 // call optimization
1340 if (PerformTailCallOpt && RetOpcode == PPC::BLR &&
1341 MF.getFunction()->getCallingConv() == CallingConv::Fast) {
1342 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1343 unsigned CallerAllocatedAmt = FI->getMinReservedArea();
1344 unsigned StackReg = IsPPC64 ? PPC::X1 : PPC::R1;
1345 unsigned FPReg = IsPPC64 ? PPC::X31 : PPC::R31;
1346 unsigned TmpReg = IsPPC64 ? PPC::X0 : PPC::R0;
1347 unsigned ADDIInstr = IsPPC64 ? PPC::ADDI8 : PPC::ADDI;
1348 unsigned ADDInstr = IsPPC64 ? PPC::ADD8 : PPC::ADD4;
1349 unsigned LISInstr = IsPPC64 ? PPC::LIS8 : PPC::LIS;
1350 unsigned ORIInstr = IsPPC64 ? PPC::ORI8 : PPC::ORI;
1352 if (CallerAllocatedAmt && isInt16(CallerAllocatedAmt)) {
1353 BuildMI(MBB, MBBI, TII.get(ADDIInstr), StackReg)
1354 .addReg(StackReg).addImm(CallerAllocatedAmt);
1356 BuildMI(MBB, MBBI, TII.get(LISInstr), TmpReg)
1357 .addImm(CallerAllocatedAmt >> 16);
1358 BuildMI(MBB, MBBI, TII.get(ORIInstr), TmpReg)
1359 .addReg(TmpReg, false, false, true)
1360 .addImm(CallerAllocatedAmt & 0xFFFF);
1361 BuildMI(MBB, MBBI, TII.get(ADDInstr))
1366 } else if (RetOpcode == PPC::TCRETURNdi) {
1367 MBBI = prior(MBB.end());
1368 MachineOperand &JumpTarget = MBBI->getOperand(0);
1369 BuildMI(MBB, MBBI, TII.get(PPC::TAILB)).
1370 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1371 } else if (RetOpcode == PPC::TCRETURNri) {
1372 MBBI = prior(MBB.end());
1373 MachineOperand &JumpTarget = MBBI->getOperand(0);
1374 assert(JumpTarget.isReg() && "Expecting register operand.");
1375 BuildMI(MBB, MBBI, TII.get(PPC::TAILBCTR));
1376 } else if (RetOpcode == PPC::TCRETURNai) {
1377 MBBI = prior(MBB.end());
1378 MachineOperand &JumpTarget = MBBI->getOperand(0);
1379 BuildMI(MBB, MBBI, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm());
1380 } else if (RetOpcode == PPC::TCRETURNdi8) {
1381 MBBI = prior(MBB.end());
1382 MachineOperand &JumpTarget = MBBI->getOperand(0);
1383 BuildMI(MBB, MBBI, TII.get(PPC::TAILB8)).
1384 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1385 } else if (RetOpcode == PPC::TCRETURNri8) {
1386 MBBI = prior(MBB.end());
1387 MachineOperand &JumpTarget = MBBI->getOperand(0);
1388 assert(JumpTarget.isReg() && "Expecting register operand.");
1389 BuildMI(MBB, MBBI, TII.get(PPC::TAILBCTR8));
1390 } else if (RetOpcode == PPC::TCRETURNai8) {
1391 MBBI = prior(MBB.end());
1392 MachineOperand &JumpTarget = MBBI->getOperand(0);
1393 BuildMI(MBB, MBBI, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm());
1397 unsigned PPCRegisterInfo::getRARegister() const {
1398 return !Subtarget.isPPC64() ? PPC::LR : PPC::LR8;
1401 unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const {
1402 if (!Subtarget.isPPC64())
1403 return hasFP(MF) ? PPC::R31 : PPC::R1;
1405 return hasFP(MF) ? PPC::X31 : PPC::X1;
1408 void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
1410 // Initial state of the frame pointer is R1.
1411 MachineLocation Dst(MachineLocation::VirtualFP);
1412 MachineLocation Src(PPC::R1, 0);
1413 Moves.push_back(MachineMove(0, Dst, Src));
1416 unsigned PPCRegisterInfo::getEHExceptionRegister() const {
1417 return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3;
1420 unsigned PPCRegisterInfo::getEHHandlerRegister() const {
1421 return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4;
1424 int PPCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
1425 // FIXME: Most probably dwarf numbers differs for Linux and Darwin
1426 return PPCGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
1429 #include "PPCGenRegisterInfo.inc"