1 //===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetRegisterInfo
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "reginfo"
16 #include "PPCRegisterInfo.h"
18 #include "PPCFrameLowering.h"
19 #include "PPCInstrBuilder.h"
20 #include "PPCMachineFunctionInfo.h"
21 #include "PPCSubtarget.h"
22 #include "llvm/ADT/BitVector.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineModuleInfo.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/RegisterScavenging.h"
30 #include "llvm/CodeGen/ValueTypes.h"
31 #include "llvm/IR/CallingConv.h"
32 #include "llvm/IR/Constants.h"
33 #include "llvm/IR/Function.h"
34 #include "llvm/IR/Type.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/ErrorHandling.h"
38 #include "llvm/Support/MathExtras.h"
39 #include "llvm/Support/raw_ostream.h"
40 #include "llvm/Target/TargetFrameLowering.h"
41 #include "llvm/Target/TargetInstrInfo.h"
42 #include "llvm/Target/TargetMachine.h"
43 #include "llvm/Target/TargetOptions.h"
46 #define GET_REGINFO_TARGET_DESC
47 #include "PPCGenRegisterInfo.inc"
51 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST,
52 const TargetInstrInfo &tii)
53 : PPCGenRegisterInfo(ST.isPPC64() ? PPC::LR8 : PPC::LR,
55 ST.isPPC64() ? 0 : 1),
56 Subtarget(ST), TII(tii) {
57 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
58 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
59 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
60 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
61 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
62 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
63 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
64 ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
67 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8;
68 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8;
69 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8;
70 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX;
71 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32;
74 /// getPointerRegClass - Return the register class to use to hold pointers.
75 /// This is used for addressing modes.
76 const TargetRegisterClass *
77 PPCRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
80 if (Subtarget.isPPC64())
81 return &PPC::G8RC_NOX0RegClass;
82 return &PPC::GPRC_NOR0RegClass;
85 if (Subtarget.isPPC64())
86 return &PPC::G8RCRegClass;
87 return &PPC::GPRCRegClass;
91 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
92 if (Subtarget.isDarwinABI())
93 return Subtarget.isPPC64() ? CSR_Darwin64_SaveList :
94 CSR_Darwin32_SaveList;
96 return Subtarget.isPPC64() ? CSR_SVR464_SaveList : CSR_SVR432_SaveList;
100 PPCRegisterInfo::getCallPreservedMask(CallingConv::ID CC) const {
101 if (Subtarget.isDarwinABI())
102 return Subtarget.isPPC64() ? CSR_Darwin64_RegMask :
103 CSR_Darwin32_RegMask;
105 return Subtarget.isPPC64() ? CSR_SVR464_RegMask : CSR_SVR432_RegMask;
109 PPCRegisterInfo::getNoPreservedMask() const {
110 // The naming here is inverted: The CSR_NoRegs_Altivec has the
111 // Altivec registers masked so that they're not saved and restored around
112 // instructions with this preserved mask.
114 if (!Subtarget.hasAltivec())
115 return CSR_NoRegs_Altivec_RegMask;
117 return CSR_NoRegs_RegMask;
120 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
121 BitVector Reserved(getNumRegs());
122 const PPCFrameLowering *PPCFI =
123 static_cast<const PPCFrameLowering*>(MF.getTarget().getFrameLowering());
125 // The ZERO register is not really a register, but the representation of r0
126 // when used in instructions that treat r0 as the constant 0.
127 Reserved.set(PPC::ZERO);
128 Reserved.set(PPC::ZERO8);
130 // The FP register is also not really a register, but is the representation
131 // of the frame pointer register used by ISD::FRAMEADDR.
132 Reserved.set(PPC::FP);
133 Reserved.set(PPC::FP8);
135 Reserved.set(PPC::R0);
136 Reserved.set(PPC::R1);
137 Reserved.set(PPC::LR);
138 Reserved.set(PPC::LR8);
139 Reserved.set(PPC::RM);
141 // The SVR4 ABI reserves r2 and r13
142 if (Subtarget.isSVR4ABI()) {
143 Reserved.set(PPC::R2); // System-reserved register
144 Reserved.set(PPC::R13); // Small Data Area pointer register
147 // On PPC64, r13 is the thread pointer. Never allocate this register.
148 if (Subtarget.isPPC64()) {
149 Reserved.set(PPC::R13);
151 Reserved.set(PPC::X0);
152 Reserved.set(PPC::X1);
153 Reserved.set(PPC::X13);
155 if (PPCFI->needsFP(MF))
156 Reserved.set(PPC::X31);
158 // The 64-bit SVR4 ABI reserves r2 for the TOC pointer.
159 if (Subtarget.isSVR4ABI()) {
160 Reserved.set(PPC::X2);
164 if (PPCFI->needsFP(MF))
165 Reserved.set(PPC::R31);
171 PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
172 MachineFunction &MF) const {
173 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
174 const unsigned DefaultSafety = 1;
176 switch (RC->getID()) {
179 case PPC::G8RC_NOX0RegClassID:
180 case PPC::GPRC_NOR0RegClassID:
181 case PPC::G8RCRegClassID:
182 case PPC::GPRCRegClassID: {
183 unsigned FP = TFI->hasFP(MF) ? 1 : 0;
184 return 32 - FP - DefaultSafety;
186 case PPC::F8RCRegClassID:
187 case PPC::F4RCRegClassID:
188 case PPC::VRRCRegClassID:
189 return 32 - DefaultSafety;
190 case PPC::CRRCRegClassID:
191 return 8 - DefaultSafety;
195 //===----------------------------------------------------------------------===//
196 // Stack Frame Processing methods
197 //===----------------------------------------------------------------------===//
199 /// lowerDynamicAlloc - Generate the code for allocating an object in the
200 /// current frame. The sequence of code with be in the general form
202 /// addi R0, SP, \#frameSize ; get the address of the previous frame
203 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size
204 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation
206 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const {
207 // Get the instruction.
208 MachineInstr &MI = *II;
209 // Get the instruction's basic block.
210 MachineBasicBlock &MBB = *MI.getParent();
211 // Get the basic block's function.
212 MachineFunction &MF = *MBB.getParent();
213 // Get the frame info.
214 MachineFrameInfo *MFI = MF.getFrameInfo();
215 // Determine whether 64-bit pointers are used.
216 bool LP64 = Subtarget.isPPC64();
217 DebugLoc dl = MI.getDebugLoc();
219 // Get the maximum call stack size.
220 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
221 // Get the total frame size.
222 unsigned FrameSize = MFI->getStackSize();
224 // Get stack alignments.
225 unsigned TargetAlign = MF.getTarget().getFrameLowering()->getStackAlignment();
226 unsigned MaxAlign = MFI->getMaxAlignment();
227 if (MaxAlign > TargetAlign)
228 report_fatal_error("Dynamic alloca with large aligns not supported");
230 // Determine the previous frame's address. If FrameSize can't be
231 // represented as 16 bits or we need special alignment, then we load the
232 // previous frame's address from 0(SP). Why not do an addis of the hi?
233 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
234 // Constructing the constant and adding would take 3 instructions.
235 // Fortunately, a frame greater than 32K is rare.
236 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
237 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
238 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
240 if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) {
241 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg)
245 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg)
249 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg)
254 // Grow the stack and update the stack pointer link, then determine the
255 // address of new allocated space.
257 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1)
258 .addReg(Reg, RegState::Kill)
260 .addReg(MI.getOperand(1).getReg());
261 if (!MI.getOperand(1).isKill())
262 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
264 .addImm(maxCallFrameSize);
266 // Implicitly kill the register.
267 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
269 .addImm(maxCallFrameSize)
270 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill);
272 BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1)
273 .addReg(Reg, RegState::Kill)
275 .addReg(MI.getOperand(1).getReg());
277 if (!MI.getOperand(1).isKill())
278 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
280 .addImm(maxCallFrameSize);
282 // Implicitly kill the register.
283 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
285 .addImm(maxCallFrameSize)
286 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill);
289 // Discard the DYNALLOC instruction.
293 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of
294 /// reserving a whole register (R0), we scrounge for one here. This generates
297 /// mfcr rA ; Move the conditional register into GPR rA.
298 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot.
299 /// stw rA, FI ; Store rA to the frame.
301 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II,
302 unsigned FrameIndex) const {
303 // Get the instruction.
304 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>
305 // Get the instruction's basic block.
306 MachineBasicBlock &MBB = *MI.getParent();
307 DebugLoc dl = MI.getDebugLoc();
309 // FIXME: Once LLVM supports creating virtual registers here, or the register
310 // scavenger can return multiple registers, stop using reserved registers
313 bool LP64 = Subtarget.isPPC64();
314 unsigned Reg = LP64 ? PPC::X0 : PPC::R0;
315 unsigned SrcReg = MI.getOperand(0).getReg();
317 // We need to store the CR in the low 4-bits of the saved value. First, issue
318 // an MFCRpsued to save all of the CRBits and, if needed, kill the SrcReg.
319 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFCR8pseud : PPC::MFCRpseud), Reg)
320 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
322 // If the saved register wasn't CR0, shift the bits left so that they are in
324 if (SrcReg != PPC::CR0)
325 // rlwinm rA, rA, ShiftBits, 0, 31.
326 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
327 .addReg(Reg, RegState::Kill)
328 .addImm(getPPCRegisterNumbering(SrcReg) * 4)
332 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW))
333 .addReg(Reg, getKillRegState(MI.getOperand(1).getImm())),
336 // Discard the pseudo instruction.
340 void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II,
341 unsigned FrameIndex) const {
342 // Get the instruction.
343 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset>
344 // Get the instruction's basic block.
345 MachineBasicBlock &MBB = *MI.getParent();
346 DebugLoc dl = MI.getDebugLoc();
348 // FIXME: Once LLVM supports creating virtual registers here, or the register
349 // scavenger can return multiple registers, stop using reserved registers
352 bool LP64 = Subtarget.isPPC64();
353 unsigned Reg = LP64 ? PPC::X0 : PPC::R0;
354 unsigned DestReg = MI.getOperand(0).getReg();
355 assert(MI.definesRegister(DestReg) &&
356 "RESTORE_CR does not define its destination");
358 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ),
361 // If the reloaded register isn't CR0, shift the bits right so that they are
362 // in the right CR's slot.
363 if (DestReg != PPC::CR0) {
364 unsigned ShiftBits = getPPCRegisterNumbering(DestReg)*4;
365 // rlwinm r11, r11, 32-ShiftBits, 0, 31.
366 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
367 .addReg(Reg).addImm(32-ShiftBits).addImm(0)
371 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTCRF8 : PPC::MTCRF), DestReg)
374 // Discard the pseudo instruction.
378 void PPCRegisterInfo::lowerVRSAVESpilling(MachineBasicBlock::iterator II,
379 unsigned FrameIndex) const {
380 // Get the instruction.
381 MachineInstr &MI = *II; // ; SPILL_VRSAVE <SrcReg>, <offset>
382 // Get the instruction's basic block.
383 MachineBasicBlock &MBB = *MI.getParent();
384 DebugLoc dl = MI.getDebugLoc();
386 // FIXME: Once LLVM supports creating virtual registers here, or the register
387 // scavenger can return multiple registers, stop using reserved registers
390 unsigned Reg = PPC::R0;
391 unsigned SrcReg = MI.getOperand(0).getReg();
393 BuildMI(MBB, II, dl, TII.get(PPC::MFVRSAVEv), Reg)
394 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
396 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::STW))
397 .addReg(Reg, getKillRegState(MI.getOperand(1).getImm())),
400 // Discard the pseudo instruction.
404 void PPCRegisterInfo::lowerVRSAVERestore(MachineBasicBlock::iterator II,
405 unsigned FrameIndex) const {
406 // Get the instruction.
407 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_VRSAVE <offset>
408 // Get the instruction's basic block.
409 MachineBasicBlock &MBB = *MI.getParent();
410 DebugLoc dl = MI.getDebugLoc();
412 // FIXME: Once LLVM supports creating virtual registers here, or the register
413 // scavenger can return multiple registers, stop using reserved registers
416 unsigned Reg = PPC::R0;
417 unsigned DestReg = MI.getOperand(0).getReg();
418 assert(MI.definesRegister(DestReg) &&
419 "RESTORE_VRSAVE does not define its destination");
421 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::LWZ),
424 BuildMI(MBB, II, dl, TII.get(PPC::MTVRSAVEv), DestReg)
427 // Discard the pseudo instruction.
432 PPCRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
433 unsigned Reg, int &FrameIdx) const {
435 // For the nonvolatile condition registers (CR2, CR3, CR4) in an SVR4
436 // ABI, return true to prevent allocating an additional frame slot.
437 // For 64-bit, the CR save area is at SP+8; the value of FrameIdx = 0
438 // is arbitrary and will be subsequently ignored. For 32-bit, we have
439 // previously created the stack slot if needed, so return its FrameIdx.
440 if (Subtarget.isSVR4ABI() && PPC::CR2 <= Reg && Reg <= PPC::CR4) {
441 if (Subtarget.isPPC64())
444 const PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
445 FrameIdx = FI->getCRSpillFrameIndex();
453 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
454 int SPAdj, unsigned FIOperandNum,
455 RegScavenger *RS) const {
456 assert(SPAdj == 0 && "Unexpected");
458 // Get the instruction.
459 MachineInstr &MI = *II;
460 // Get the instruction's basic block.
461 MachineBasicBlock &MBB = *MI.getParent();
462 // Get the basic block's function.
463 MachineFunction &MF = *MBB.getParent();
464 // Get the frame info.
465 MachineFrameInfo *MFI = MF.getFrameInfo();
466 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
467 DebugLoc dl = MI.getDebugLoc();
469 // Take into account whether it's an add or mem instruction
470 unsigned OffsetOperandNo = (FIOperandNum == 2) ? 1 : 2;
471 if (MI.isInlineAsm())
472 OffsetOperandNo = FIOperandNum-1;
474 // Get the frame index.
475 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
477 // Get the frame pointer save index. Users of this index are primarily
478 // DYNALLOC instructions.
479 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
480 int FPSI = FI->getFramePointerSaveIndex();
481 // Get the instruction opcode.
482 unsigned OpC = MI.getOpcode();
484 // Special case for dynamic alloca.
485 if (FPSI && FrameIndex == FPSI &&
486 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
487 lowerDynamicAlloc(II);
491 // Special case for pseudo-ops SPILL_CR and RESTORE_CR, etc.
492 if (OpC == PPC::SPILL_CR) {
493 lowerCRSpilling(II, FrameIndex);
495 } else if (OpC == PPC::RESTORE_CR) {
496 lowerCRRestore(II, FrameIndex);
498 } else if (OpC == PPC::SPILL_VRSAVE) {
499 lowerVRSAVESpilling(II, FrameIndex);
501 } else if (OpC == PPC::RESTORE_VRSAVE) {
502 lowerVRSAVERestore(II, FrameIndex);
506 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
508 bool is64Bit = Subtarget.isPPC64();
509 MI.getOperand(FIOperandNum).ChangeToRegister(TFI->hasFP(MF) ?
510 (is64Bit ? PPC::X31 : PPC::R31) :
511 (is64Bit ? PPC::X1 : PPC::R1),
514 // Figure out if the offset in the instruction is shifted right two bits. This
515 // is true for instructions like "STD", which the machine implicitly adds two
517 bool isIXAddr = false;
527 bool noImmForm = false;
545 // Now add the frame object offset to the offset from r1.
546 int Offset = MFI->getObjectOffset(FrameIndex);
548 Offset += MI.getOperand(OffsetOperandNo).getImm();
550 Offset += MI.getOperand(OffsetOperandNo).getImm() << 2;
552 // If we're not using a Frame Pointer that has been set to the value of the
553 // SP before having the stack size subtracted from it, then add the stack size
554 // to Offset to get the correct offset.
555 // Naked functions have stack size 0, although getStackSize may not reflect that
556 // because we didn't call all the pieces that compute it for naked functions.
557 if (!MF.getFunction()->getAttributes().
558 hasAttribute(AttributeSet::FunctionIndex, Attribute::Naked))
559 Offset += MFI->getStackSize();
561 // If we can, encode the offset directly into the instruction. If this is a
562 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If
563 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits
564 // clear can be encoded. This is extremely uncommon, because normally you
565 // only "std" to a stack slot that is at least 4-byte aligned, but it can
566 // happen in invalid code.
567 if (OpC == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm
569 isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0))) {
571 Offset >>= 2; // The actual encoded value has the low two bits zero.
572 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
576 // The offset doesn't fit into a single register, scavenge one to build the
579 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
580 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
581 unsigned SReg = MF.getRegInfo().createVirtualRegister(is64Bit ? G8RC : GPRC);
583 // Insert a set of rA with the full offset value before the ld, st, or add
584 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SReg)
585 .addImm(Offset >> 16);
586 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg)
587 .addReg(SReg, RegState::Kill)
590 // Convert into indexed form of the instruction:
592 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
593 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
594 unsigned OperandBase;
598 else if (OpC != TargetOpcode::INLINEASM) {
599 assert(ImmToIdxMap.count(OpC) &&
600 "No indexed form of load or store available!");
601 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second;
602 MI.setDesc(TII.get(NewOpcode));
605 OperandBase = OffsetOperandNo;
608 unsigned StackReg = MI.getOperand(FIOperandNum).getReg();
609 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false);
610 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true);
613 unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
614 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
616 if (!Subtarget.isPPC64())
617 return TFI->hasFP(MF) ? PPC::R31 : PPC::R1;
619 return TFI->hasFP(MF) ? PPC::X31 : PPC::X1;
622 unsigned PPCRegisterInfo::getEHExceptionRegister() const {
623 return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3;
626 unsigned PPCRegisterInfo::getEHHandlerRegister() const {
627 return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4;