1 //===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetRegisterInfo
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "reginfo"
16 #include "PPCRegisterInfo.h"
18 #include "PPCFrameLowering.h"
19 #include "PPCInstrBuilder.h"
20 #include "PPCMachineFunctionInfo.h"
21 #include "PPCSubtarget.h"
22 #include "llvm/ADT/BitVector.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineModuleInfo.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/RegisterScavenging.h"
30 #include "llvm/CodeGen/ValueTypes.h"
31 #include "llvm/IR/CallingConv.h"
32 #include "llvm/IR/Constants.h"
33 #include "llvm/IR/Function.h"
34 #include "llvm/IR/Type.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/ErrorHandling.h"
38 #include "llvm/Support/MathExtras.h"
39 #include "llvm/Support/raw_ostream.h"
40 #include "llvm/Target/TargetFrameLowering.h"
41 #include "llvm/Target/TargetInstrInfo.h"
42 #include "llvm/Target/TargetMachine.h"
43 #include "llvm/Target/TargetOptions.h"
46 #define GET_REGINFO_TARGET_DESC
47 #include "PPCGenRegisterInfo.inc"
52 EnableBasePointer("ppc-use-base-pointer", cl::Hidden, cl::init(true),
53 cl::desc("Enable use of a base pointer for complex stack frames"));
56 AlwaysBasePointer("ppc-always-use-base-pointer", cl::Hidden, cl::init(false),
57 cl::desc("Force the use of a base pointer in every function"));
59 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST)
60 : PPCGenRegisterInfo(ST.isPPC64() ? PPC::LR8 : PPC::LR,
62 ST.isPPC64() ? 0 : 1),
64 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
65 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
66 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
67 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
68 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
69 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
70 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
71 ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
72 ImmToIdxMap[PPC::LWA_32] = PPC::LWAX_32;
75 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8;
76 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8;
77 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8;
78 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX;
79 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8;
82 /// getPointerRegClass - Return the register class to use to hold pointers.
83 /// This is used for addressing modes.
84 const TargetRegisterClass *
85 PPCRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
87 // Note that PPCInstrInfo::FoldImmediate also directly uses this Kind value
88 // when it checks for ZERO folding.
90 if (Subtarget.isPPC64())
91 return &PPC::G8RC_NOX0RegClass;
92 return &PPC::GPRC_NOR0RegClass;
95 if (Subtarget.isPPC64())
96 return &PPC::G8RCRegClass;
97 return &PPC::GPRCRegClass;
101 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
102 if (Subtarget.isDarwinABI())
103 return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ?
104 CSR_Darwin64_Altivec_SaveList :
105 CSR_Darwin64_SaveList) :
106 (Subtarget.hasAltivec() ?
107 CSR_Darwin32_Altivec_SaveList :
108 CSR_Darwin32_SaveList);
110 return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ?
111 CSR_SVR464_Altivec_SaveList :
112 CSR_SVR464_SaveList) :
113 (Subtarget.hasAltivec() ?
114 CSR_SVR432_Altivec_SaveList :
115 CSR_SVR432_SaveList);
119 PPCRegisterInfo::getCallPreservedMask(CallingConv::ID CC) const {
120 if (Subtarget.isDarwinABI())
121 return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ?
122 CSR_Darwin64_Altivec_RegMask :
123 CSR_Darwin64_RegMask) :
124 (Subtarget.hasAltivec() ?
125 CSR_Darwin32_Altivec_RegMask :
126 CSR_Darwin32_RegMask);
128 return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ?
129 CSR_SVR464_Altivec_RegMask :
130 CSR_SVR464_RegMask) :
131 (Subtarget.hasAltivec() ?
132 CSR_SVR432_Altivec_RegMask :
137 PPCRegisterInfo::getNoPreservedMask() const {
138 return CSR_NoRegs_RegMask;
141 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
142 BitVector Reserved(getNumRegs());
143 const PPCFrameLowering *PPCFI =
144 static_cast<const PPCFrameLowering*>(MF.getTarget().getFrameLowering());
146 // The ZERO register is not really a register, but the representation of r0
147 // when used in instructions that treat r0 as the constant 0.
148 Reserved.set(PPC::ZERO);
149 Reserved.set(PPC::ZERO8);
151 // The FP register is also not really a register, but is the representation
152 // of the frame pointer register used by ISD::FRAMEADDR.
153 Reserved.set(PPC::FP);
154 Reserved.set(PPC::FP8);
156 // The BP register is also not really a register, but is the representation
157 // of the base pointer register used by setjmp.
158 Reserved.set(PPC::BP);
159 Reserved.set(PPC::BP8);
161 // The counter registers must be reserved so that counter-based loops can
162 // be correctly formed (and the mtctr instructions are not DCE'd).
163 Reserved.set(PPC::CTR);
164 Reserved.set(PPC::CTR8);
166 Reserved.set(PPC::R1);
167 Reserved.set(PPC::LR);
168 Reserved.set(PPC::LR8);
169 Reserved.set(PPC::RM);
171 if (!Subtarget.isDarwinABI() || !Subtarget.hasAltivec())
172 Reserved.set(PPC::VRSAVE);
174 // The SVR4 ABI reserves r2 and r13
175 if (Subtarget.isSVR4ABI()) {
176 Reserved.set(PPC::R2); // System-reserved register
177 Reserved.set(PPC::R13); // Small Data Area pointer register
180 // On PPC64, r13 is the thread pointer. Never allocate this register.
181 if (Subtarget.isPPC64()) {
182 Reserved.set(PPC::R13);
184 Reserved.set(PPC::X1);
185 Reserved.set(PPC::X13);
187 if (PPCFI->needsFP(MF))
188 Reserved.set(PPC::X31);
190 if (hasBasePointer(MF))
191 Reserved.set(PPC::X30);
193 // The 64-bit SVR4 ABI reserves r2 for the TOC pointer.
194 if (Subtarget.isSVR4ABI()) {
195 Reserved.set(PPC::X2);
199 if (PPCFI->needsFP(MF))
200 Reserved.set(PPC::R31);
202 if (hasBasePointer(MF))
203 Reserved.set(PPC::R30);
205 // Reserve Altivec registers when Altivec is unavailable.
206 if (!Subtarget.hasAltivec())
207 for (TargetRegisterClass::iterator I = PPC::VRRCRegClass.begin(),
208 IE = PPC::VRRCRegClass.end(); I != IE; ++I)
215 PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
216 MachineFunction &MF) const {
217 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
218 const unsigned DefaultSafety = 1;
220 switch (RC->getID()) {
223 case PPC::G8RC_NOX0RegClassID:
224 case PPC::GPRC_NOR0RegClassID:
225 case PPC::G8RCRegClassID:
226 case PPC::GPRCRegClassID: {
227 unsigned FP = TFI->hasFP(MF) ? 1 : 0;
228 return 32 - FP - DefaultSafety;
230 case PPC::F8RCRegClassID:
231 case PPC::F4RCRegClassID:
232 case PPC::VRRCRegClassID:
233 return 32 - DefaultSafety;
234 case PPC::CRRCRegClassID:
235 return 8 - DefaultSafety;
239 //===----------------------------------------------------------------------===//
240 // Stack Frame Processing methods
241 //===----------------------------------------------------------------------===//
243 /// lowerDynamicAlloc - Generate the code for allocating an object in the
244 /// current frame. The sequence of code with be in the general form
246 /// addi R0, SP, \#frameSize ; get the address of the previous frame
247 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size
248 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation
250 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const {
251 // Get the instruction.
252 MachineInstr &MI = *II;
253 // Get the instruction's basic block.
254 MachineBasicBlock &MBB = *MI.getParent();
255 // Get the basic block's function.
256 MachineFunction &MF = *MBB.getParent();
257 // Get the frame info.
258 MachineFrameInfo *MFI = MF.getFrameInfo();
259 // Get the instruction info.
260 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
261 // Determine whether 64-bit pointers are used.
262 bool LP64 = Subtarget.isPPC64();
263 DebugLoc dl = MI.getDebugLoc();
265 // Get the maximum call stack size.
266 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
267 // Get the total frame size.
268 unsigned FrameSize = MFI->getStackSize();
270 // Get stack alignments.
271 unsigned TargetAlign = MF.getTarget().getFrameLowering()->getStackAlignment();
272 unsigned MaxAlign = MFI->getMaxAlignment();
273 assert((maxCallFrameSize & (MaxAlign-1)) == 0 &&
274 "Maximum call-frame size not sufficiently aligned");
276 // Determine the previous frame's address. If FrameSize can't be
277 // represented as 16 bits or we need special alignment, then we load the
278 // previous frame's address from 0(SP). Why not do an addis of the hi?
279 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
280 // Constructing the constant and adding would take 3 instructions.
281 // Fortunately, a frame greater than 32K is rare.
282 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
283 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
284 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
286 if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) {
287 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg)
291 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg)
295 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg)
300 bool KillNegSizeReg = MI.getOperand(1).isKill();
301 unsigned NegSizeReg = MI.getOperand(1).getReg();
303 // Grow the stack and update the stack pointer link, then determine the
304 // address of new allocated space.
306 if (MaxAlign > TargetAlign) {
307 unsigned UnalNegSizeReg = NegSizeReg;
308 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC);
310 // Unfortunately, there is no andi, only andi., and we can't insert that
311 // here because we might clobber cr0 while it is live.
312 BuildMI(MBB, II, dl, TII.get(PPC::LI8), NegSizeReg)
313 .addImm(~(MaxAlign-1));
315 unsigned NegSizeReg1 = NegSizeReg;
316 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC);
317 BuildMI(MBB, II, dl, TII.get(PPC::AND8), NegSizeReg)
318 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg))
319 .addReg(NegSizeReg1, RegState::Kill);
320 KillNegSizeReg = true;
323 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1)
324 .addReg(Reg, RegState::Kill)
326 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg));
327 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
329 .addImm(maxCallFrameSize);
331 if (MaxAlign > TargetAlign) {
332 unsigned UnalNegSizeReg = NegSizeReg;
333 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC);
335 // Unfortunately, there is no andi, only andi., and we can't insert that
336 // here because we might clobber cr0 while it is live.
337 BuildMI(MBB, II, dl, TII.get(PPC::LI), NegSizeReg)
338 .addImm(~(MaxAlign-1));
340 unsigned NegSizeReg1 = NegSizeReg;
341 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC);
342 BuildMI(MBB, II, dl, TII.get(PPC::AND), NegSizeReg)
343 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg))
344 .addReg(NegSizeReg1, RegState::Kill);
345 KillNegSizeReg = true;
348 BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1)
349 .addReg(Reg, RegState::Kill)
351 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg));
352 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
354 .addImm(maxCallFrameSize);
357 // Discard the DYNALLOC instruction.
361 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of
362 /// reserving a whole register (R0), we scrounge for one here. This generates
365 /// mfcr rA ; Move the conditional register into GPR rA.
366 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot.
367 /// stw rA, FI ; Store rA to the frame.
369 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II,
370 unsigned FrameIndex) const {
371 // Get the instruction.
372 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>
373 // Get the instruction's basic block.
374 MachineBasicBlock &MBB = *MI.getParent();
375 MachineFunction &MF = *MBB.getParent();
376 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
377 DebugLoc dl = MI.getDebugLoc();
379 bool LP64 = Subtarget.isPPC64();
380 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
381 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
383 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
384 unsigned SrcReg = MI.getOperand(0).getReg();
386 // We need to store the CR in the low 4-bits of the saved value. First, issue
387 // an MFOCRF to save all of the CRBits and, if needed, kill the SrcReg.
388 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg)
389 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
391 // If the saved register wasn't CR0, shift the bits left so that they are in
393 if (SrcReg != PPC::CR0) {
395 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
397 // rlwinm rA, rA, ShiftBits, 0, 31.
398 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
399 .addReg(Reg1, RegState::Kill)
400 .addImm(getEncodingValue(SrcReg) * 4)
405 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW))
406 .addReg(Reg, RegState::Kill),
409 // Discard the pseudo instruction.
413 void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II,
414 unsigned FrameIndex) const {
415 // Get the instruction.
416 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset>
417 // Get the instruction's basic block.
418 MachineBasicBlock &MBB = *MI.getParent();
419 MachineFunction &MF = *MBB.getParent();
420 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
421 DebugLoc dl = MI.getDebugLoc();
423 bool LP64 = Subtarget.isPPC64();
424 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
425 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
427 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
428 unsigned DestReg = MI.getOperand(0).getReg();
429 assert(MI.definesRegister(DestReg) &&
430 "RESTORE_CR does not define its destination");
432 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ),
435 // If the reloaded register isn't CR0, shift the bits right so that they are
436 // in the right CR's slot.
437 if (DestReg != PPC::CR0) {
439 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
441 unsigned ShiftBits = getEncodingValue(DestReg)*4;
442 // rlwinm r11, r11, 32-ShiftBits, 0, 31.
443 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
444 .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0)
448 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), DestReg)
449 .addReg(Reg, RegState::Kill);
451 // Discard the pseudo instruction.
455 static unsigned getCRFromCRBit(unsigned SrcReg) {
457 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
458 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
460 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
461 SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
463 else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT ||
464 SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN)
466 else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
467 SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
469 else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
470 SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
472 else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT ||
473 SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN)
475 else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
476 SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
478 else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
479 SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
482 assert(Reg != 0 && "Invalid CR bit register");
486 void PPCRegisterInfo::lowerCRBitSpilling(MachineBasicBlock::iterator II,
487 unsigned FrameIndex) const {
488 // Get the instruction.
489 MachineInstr &MI = *II; // ; SPILL_CRBIT <SrcReg>, <offset>
490 // Get the instruction's basic block.
491 MachineBasicBlock &MBB = *MI.getParent();
492 MachineFunction &MF = *MBB.getParent();
493 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
494 DebugLoc dl = MI.getDebugLoc();
496 bool LP64 = Subtarget.isPPC64();
497 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
498 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
500 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
501 unsigned SrcReg = MI.getOperand(0).getReg();
503 BuildMI(MBB, II, dl, TII.get(TargetOpcode::KILL),
504 getCRFromCRBit(SrcReg))
505 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
507 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg)
508 .addReg(getCRFromCRBit(SrcReg));
510 // If the saved register wasn't CR0LT, shift the bits left so that the bit to
511 // store is the first one. Mask all but that bit.
513 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
515 // rlwinm rA, rA, ShiftBits, 0, 0.
516 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
517 .addReg(Reg1, RegState::Kill)
518 .addImm(getEncodingValue(SrcReg))
519 .addImm(0).addImm(0);
521 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW))
522 .addReg(Reg, RegState::Kill),
525 // Discard the pseudo instruction.
529 void PPCRegisterInfo::lowerCRBitRestore(MachineBasicBlock::iterator II,
530 unsigned FrameIndex) const {
531 // Get the instruction.
532 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CRBIT <offset>
533 // Get the instruction's basic block.
534 MachineBasicBlock &MBB = *MI.getParent();
535 MachineFunction &MF = *MBB.getParent();
536 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
537 DebugLoc dl = MI.getDebugLoc();
539 bool LP64 = Subtarget.isPPC64();
540 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
541 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
543 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
544 unsigned DestReg = MI.getOperand(0).getReg();
545 assert(MI.definesRegister(DestReg) &&
546 "RESTORE_CRBIT does not define its destination");
548 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ),
551 BuildMI(MBB, II, dl, TII.get(TargetOpcode::IMPLICIT_DEF), DestReg);
553 unsigned RegO = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
554 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), RegO)
555 .addReg(getCRFromCRBit(DestReg));
557 unsigned ShiftBits = getEncodingValue(DestReg);
558 // rlwimi r11, r10, 32-ShiftBits, ..., ...
559 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWIMI8 : PPC::RLWIMI), RegO)
560 .addReg(RegO, RegState::Kill).addReg(Reg, RegState::Kill)
561 .addImm(ShiftBits ? 32-ShiftBits : 0)
562 .addImm(ShiftBits).addImm(ShiftBits);
564 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF),
565 getCRFromCRBit(DestReg))
566 .addReg(RegO, RegState::Kill)
567 // Make sure we have a use dependency all the way through this
568 // sequence of instructions. We can't have the other bits in the CR
569 // modified in between the mfocrf and the mtocrf.
570 .addReg(getCRFromCRBit(DestReg), RegState::Implicit);
572 // Discard the pseudo instruction.
576 void PPCRegisterInfo::lowerVRSAVESpilling(MachineBasicBlock::iterator II,
577 unsigned FrameIndex) const {
578 // Get the instruction.
579 MachineInstr &MI = *II; // ; SPILL_VRSAVE <SrcReg>, <offset>
580 // Get the instruction's basic block.
581 MachineBasicBlock &MBB = *MI.getParent();
582 MachineFunction &MF = *MBB.getParent();
583 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
584 DebugLoc dl = MI.getDebugLoc();
586 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
587 unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC);
588 unsigned SrcReg = MI.getOperand(0).getReg();
590 BuildMI(MBB, II, dl, TII.get(PPC::MFVRSAVEv), Reg)
591 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
593 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::STW))
594 .addReg(Reg, RegState::Kill),
597 // Discard the pseudo instruction.
601 void PPCRegisterInfo::lowerVRSAVERestore(MachineBasicBlock::iterator II,
602 unsigned FrameIndex) const {
603 // Get the instruction.
604 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_VRSAVE <offset>
605 // Get the instruction's basic block.
606 MachineBasicBlock &MBB = *MI.getParent();
607 MachineFunction &MF = *MBB.getParent();
608 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
609 DebugLoc dl = MI.getDebugLoc();
611 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
612 unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC);
613 unsigned DestReg = MI.getOperand(0).getReg();
614 assert(MI.definesRegister(DestReg) &&
615 "RESTORE_VRSAVE does not define its destination");
617 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::LWZ),
620 BuildMI(MBB, II, dl, TII.get(PPC::MTVRSAVEv), DestReg)
621 .addReg(Reg, RegState::Kill);
623 // Discard the pseudo instruction.
628 PPCRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
629 unsigned Reg, int &FrameIdx) const {
631 // For the nonvolatile condition registers (CR2, CR3, CR4) in an SVR4
632 // ABI, return true to prevent allocating an additional frame slot.
633 // For 64-bit, the CR save area is at SP+8; the value of FrameIdx = 0
634 // is arbitrary and will be subsequently ignored. For 32-bit, we have
635 // previously created the stack slot if needed, so return its FrameIdx.
636 if (Subtarget.isSVR4ABI() && PPC::CR2 <= Reg && Reg <= PPC::CR4) {
637 if (Subtarget.isPPC64())
640 const PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
641 FrameIdx = FI->getCRSpillFrameIndex();
648 // Figure out if the offset in the instruction must be a multiple of 4.
649 // This is true for instructions like "STD".
650 static bool usesIXAddr(const MachineInstr &MI) {
651 unsigned OpC = MI.getOpcode();
664 // Return the OffsetOperandNo given the FIOperandNum (and the instruction).
665 static unsigned getOffsetONFromFION(const MachineInstr &MI,
666 unsigned FIOperandNum) {
667 // Take into account whether it's an add or mem instruction
668 unsigned OffsetOperandNo = (FIOperandNum == 2) ? 1 : 2;
669 if (MI.isInlineAsm())
670 OffsetOperandNo = FIOperandNum-1;
672 return OffsetOperandNo;
676 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
677 int SPAdj, unsigned FIOperandNum,
678 RegScavenger *RS) const {
679 assert(SPAdj == 0 && "Unexpected");
681 // Get the instruction.
682 MachineInstr &MI = *II;
683 // Get the instruction's basic block.
684 MachineBasicBlock &MBB = *MI.getParent();
685 // Get the basic block's function.
686 MachineFunction &MF = *MBB.getParent();
687 // Get the instruction info.
688 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
689 // Get the frame info.
690 MachineFrameInfo *MFI = MF.getFrameInfo();
691 DebugLoc dl = MI.getDebugLoc();
693 unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum);
695 // Get the frame index.
696 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
698 // Get the frame pointer save index. Users of this index are primarily
699 // DYNALLOC instructions.
700 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
701 int FPSI = FI->getFramePointerSaveIndex();
702 // Get the instruction opcode.
703 unsigned OpC = MI.getOpcode();
705 // Special case for dynamic alloca.
706 if (FPSI && FrameIndex == FPSI &&
707 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
708 lowerDynamicAlloc(II);
712 // Special case for pseudo-ops SPILL_CR and RESTORE_CR, etc.
713 if (OpC == PPC::SPILL_CR) {
714 lowerCRSpilling(II, FrameIndex);
716 } else if (OpC == PPC::RESTORE_CR) {
717 lowerCRRestore(II, FrameIndex);
719 } else if (OpC == PPC::SPILL_CRBIT) {
720 lowerCRBitSpilling(II, FrameIndex);
722 } else if (OpC == PPC::RESTORE_CRBIT) {
723 lowerCRBitRestore(II, FrameIndex);
725 } else if (OpC == PPC::SPILL_VRSAVE) {
726 lowerVRSAVESpilling(II, FrameIndex);
728 } else if (OpC == PPC::RESTORE_VRSAVE) {
729 lowerVRSAVERestore(II, FrameIndex);
733 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
734 MI.getOperand(FIOperandNum).ChangeToRegister(
735 FrameIndex < 0 ? getBaseRegister(MF) : getFrameRegister(MF), false);
737 // Figure out if the offset in the instruction is shifted right two bits.
738 bool isIXAddr = usesIXAddr(MI);
740 // If the instruction is not present in ImmToIdxMap, then it has no immediate
741 // form (and must be r+r).
742 bool noImmForm = !MI.isInlineAsm() && !ImmToIdxMap.count(OpC);
744 // Now add the frame object offset to the offset from r1.
745 int Offset = MFI->getObjectOffset(FrameIndex);
746 Offset += MI.getOperand(OffsetOperandNo).getImm();
748 // If we're not using a Frame Pointer that has been set to the value of the
749 // SP before having the stack size subtracted from it, then add the stack size
750 // to Offset to get the correct offset.
751 // Naked functions have stack size 0, although getStackSize may not reflect that
752 // because we didn't call all the pieces that compute it for naked functions.
753 if (!MF.getFunction()->getAttributes().
754 hasAttribute(AttributeSet::FunctionIndex, Attribute::Naked)) {
755 if (!(hasBasePointer(MF) && FrameIndex < 0))
756 Offset += MFI->getStackSize();
759 // If we can, encode the offset directly into the instruction. If this is a
760 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If
761 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits
762 // clear can be encoded. This is extremely uncommon, because normally you
763 // only "std" to a stack slot that is at least 4-byte aligned, but it can
764 // happen in invalid code.
765 assert(OpC != PPC::DBG_VALUE &&
766 "This should be handle in a target independent way");
767 if (!noImmForm && isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0)) {
768 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
772 // The offset doesn't fit into a single register, scavenge one to build the
775 bool is64Bit = Subtarget.isPPC64();
776 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
777 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
778 const TargetRegisterClass *RC = is64Bit ? G8RC : GPRC;
779 unsigned SRegHi = MF.getRegInfo().createVirtualRegister(RC),
780 SReg = MF.getRegInfo().createVirtualRegister(RC);
782 // Insert a set of rA with the full offset value before the ld, st, or add
783 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SRegHi)
784 .addImm(Offset >> 16);
785 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg)
786 .addReg(SRegHi, RegState::Kill)
789 // Convert into indexed form of the instruction:
791 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
792 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
793 unsigned OperandBase;
797 else if (OpC != TargetOpcode::INLINEASM) {
798 assert(ImmToIdxMap.count(OpC) &&
799 "No indexed form of load or store available!");
800 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second;
801 MI.setDesc(TII.get(NewOpcode));
804 OperandBase = OffsetOperandNo;
807 unsigned StackReg = MI.getOperand(FIOperandNum).getReg();
808 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false);
809 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true);
812 unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
813 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
815 if (!Subtarget.isPPC64())
816 return TFI->hasFP(MF) ? PPC::R31 : PPC::R1;
818 return TFI->hasFP(MF) ? PPC::X31 : PPC::X1;
821 unsigned PPCRegisterInfo::getBaseRegister(const MachineFunction &MF) const {
822 if (!hasBasePointer(MF))
823 return getFrameRegister(MF);
825 return Subtarget.isPPC64() ? PPC::X30 : PPC::R30;
828 bool PPCRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
829 if (!EnableBasePointer)
831 if (AlwaysBasePointer)
834 // If we need to realign the stack, then the stack pointer can no longer
835 // serve as an offset into the caller's stack space. As a result, we need a
837 return needsStackRealignment(MF);
840 bool PPCRegisterInfo::canRealignStack(const MachineFunction &MF) const {
841 if (MF.getFunction()->hasFnAttribute("no-realign-stack"))
847 bool PPCRegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
848 const MachineFrameInfo *MFI = MF.getFrameInfo();
849 const Function *F = MF.getFunction();
850 unsigned StackAlign = MF.getTarget().getFrameLowering()->getStackAlignment();
851 bool requiresRealignment =
852 ((MFI->getMaxAlignment() > StackAlign) ||
853 F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
854 Attribute::StackAlignment));
856 return requiresRealignment && canRealignStack(MF);
859 /// Returns true if the instruction's frame index
860 /// reference would be better served by a base register other than FP
861 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
862 /// references it should create new base registers for.
863 bool PPCRegisterInfo::
864 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
865 assert(Offset < 0 && "Local offset must be negative");
867 unsigned FIOperandNum = 0;
868 while (!MI->getOperand(FIOperandNum).isFI()) {
870 assert(FIOperandNum < MI->getNumOperands() &&
871 "Instr doesn't have FrameIndex operand!");
874 unsigned OffsetOperandNo = getOffsetONFromFION(*MI, FIOperandNum);
875 Offset += MI->getOperand(OffsetOperandNo).getImm();
877 // It's the load/store FI references that cause issues, as it can be difficult
878 // to materialize the offset if it won't fit in the literal field. Estimate
879 // based on the size of the local frame and some conservative assumptions
880 // about the rest of the stack frame (note, this is pre-regalloc, so
881 // we don't know everything for certain yet) whether this offset is likely
882 // to be out of range of the immediate. Return true if so.
884 // We only generate virtual base registers for loads and stores that have
885 // an r+i form. Return false for everything else.
886 unsigned OpC = MI->getOpcode();
887 if (!ImmToIdxMap.count(OpC))
890 // Don't generate a new virtual base register just to add zero to it.
891 if ((OpC == PPC::ADDI || OpC == PPC::ADDI8) &&
892 MI->getOperand(2).getImm() == 0)
895 MachineBasicBlock &MBB = *MI->getParent();
896 MachineFunction &MF = *MBB.getParent();
898 const PPCFrameLowering *PPCFI =
899 static_cast<const PPCFrameLowering*>(MF.getTarget().getFrameLowering());
901 PPCFI->determineFrameLayout(MF, false, true);
903 // If we likely don't need a stack frame, then we probably don't need a
904 // virtual base register either.
908 // Estimate an offset from the stack pointer.
909 // The incoming offset is relating to the SP at the start of the function,
910 // but when we access the local it'll be relative to the SP after local
911 // allocation, so adjust our SP-relative offset by that allocation size.
914 // The frame pointer will point to the end of the stack, so estimate the
915 // offset as the difference between the object offset and the FP location.
916 return !isFrameOffsetLegal(MI, Offset);
919 /// Insert defining instruction(s) for BaseReg to
920 /// be a pointer to FrameIdx at the beginning of the basic block.
921 void PPCRegisterInfo::
922 materializeFrameBaseRegister(MachineBasicBlock *MBB,
923 unsigned BaseReg, int FrameIdx,
924 int64_t Offset) const {
925 unsigned ADDriOpc = Subtarget.isPPC64() ? PPC::ADDI8 : PPC::ADDI;
927 MachineBasicBlock::iterator Ins = MBB->begin();
928 DebugLoc DL; // Defaults to "unknown"
929 if (Ins != MBB->end())
930 DL = Ins->getDebugLoc();
932 const MachineFunction &MF = *MBB->getParent();
933 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
934 const MCInstrDesc &MCID = TII.get(ADDriOpc);
935 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
936 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
938 BuildMI(*MBB, Ins, DL, MCID, BaseReg)
939 .addFrameIndex(FrameIdx).addImm(Offset);
943 PPCRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I,
944 unsigned BaseReg, int64_t Offset) const {
945 MachineInstr &MI = *I;
947 unsigned FIOperandNum = 0;
948 while (!MI.getOperand(FIOperandNum).isFI()) {
950 assert(FIOperandNum < MI.getNumOperands() &&
951 "Instr doesn't have FrameIndex operand!");
954 MI.getOperand(FIOperandNum).ChangeToRegister(BaseReg, false);
955 unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum);
956 Offset += MI.getOperand(OffsetOperandNo).getImm();
957 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
960 bool PPCRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
961 int64_t Offset) const {
962 return MI->getOpcode() == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm
963 (isInt<16>(Offset) && (!usesIXAddr(*MI) || (Offset & 3) == 0));