1 //===- PPC32RegisterInfo.cpp - PowerPC32 Register Information ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC32 implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "reginfo"
16 #include "PowerPCInstrBuilder.h"
17 #include "PPC32RegisterInfo.h"
18 #include "llvm/Constants.h"
19 #include "llvm/Type.h"
20 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/Target/TargetFrameInfo.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/ADT/STLExtras.h"
34 PPC32RegisterInfo::PPC32RegisterInfo()
35 : PPC32GenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP) {
36 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
37 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
38 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
39 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
40 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
41 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
42 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
43 ImmToIdxMap[PPC::ADDI] = PPC::ADD;
46 static const TargetRegisterClass *getClass(unsigned SrcReg) {
47 if (PPC32::GPRCRegisterClass->contains(SrcReg))
48 return PPC32::GPRCRegisterClass;
49 if (PPC32::FPRCRegisterClass->contains(SrcReg))
50 return PPC32::FPRCRegisterClass;
51 assert(PPC32::CRRCRegisterClass->contains(SrcReg) &&"Reg not FPR, GPR, CRRC");
52 return PPC32::CRRCRegisterClass;
55 static unsigned getIdx(const TargetRegisterClass *RC) {
56 if (RC == PPC32::GPRCRegisterClass) {
57 switch (RC->getSize()) {
58 default: assert(0 && "Invalid data size!");
63 } else if (RC == PPC32::FPRCRegisterClass) {
64 switch (RC->getSize()) {
65 default: assert(0 && "Invalid data size!");
69 } else if (RC == PPC32::CRRCRegisterClass) {
70 switch (RC->getSize()) {
71 default: assert(0 && "Invalid data size!");
75 std::cerr << "Invalid register class to getIdx()!\n";
80 PPC32RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
81 MachineBasicBlock::iterator MI,
82 unsigned SrcReg, int FrameIdx,
83 const TargetRegisterClass *RC) const {
84 static const unsigned Opcode[] = {
85 PPC::STB, PPC::STH, PPC::STW, PPC::STFS, PPC::STFD
87 const TargetRegisterClass *RegClass = getClass(SrcReg);
88 unsigned OC = Opcode[getIdx(RegClass)];
89 if (SrcReg == PPC::LR) {
90 BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11);
91 addFrameReference(BuildMI(MBB, MI, OC, 3).addReg(PPC::R11),FrameIdx);
92 } else if (RegClass == PPC32::CRRCRegisterClass) {
93 BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R11);
94 addFrameReference(BuildMI(MBB, MI, OC, 3).addReg(PPC::R11),FrameIdx);
96 addFrameReference(BuildMI(MBB, MI, OC, 3).addReg(SrcReg),FrameIdx);
101 PPC32RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
102 MachineBasicBlock::iterator MI,
103 unsigned DestReg, int FrameIdx,
104 const TargetRegisterClass *RC) const {
105 static const unsigned Opcode[] = {
106 PPC::LBZ, PPC::LHZ, PPC::LWZ, PPC::LFS, PPC::LFD
108 const TargetRegisterClass *RegClass = getClass(DestReg);
109 unsigned OC = Opcode[getIdx(RegClass)];
110 if (DestReg == PPC::LR) {
111 addFrameReference(BuildMI(MBB, MI, OC, 2, PPC::R11), FrameIdx);
112 BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11);
113 } else if (RegClass == PPC32::CRRCRegisterClass) {
114 addFrameReference(BuildMI(MBB, MI, OC, 2, PPC::R11), FrameIdx);
115 BuildMI(MBB, MI, PPC::MTCRF, 1, DestReg).addReg(PPC::R11);
117 addFrameReference(BuildMI(MBB, MI, OC, 2, DestReg), FrameIdx);
121 void PPC32RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
122 MachineBasicBlock::iterator MI,
123 unsigned DestReg, unsigned SrcReg,
124 const TargetRegisterClass *RC) const {
127 if (RC == PPC32::GPRCRegisterClass) {
128 BuildMI(MBB, MI, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
129 } else if (RC == PPC32::FPRCRegisterClass) {
130 BuildMI(MBB, MI, PPC::FMR, 1, DestReg).addReg(SrcReg);
131 } else if (RC == PPC32::CRRCRegisterClass) {
132 BuildMI(MBB, MI, PPC::MCRF, 1, DestReg).addReg(SrcReg);
134 std::cerr << "Attempt to copy register that is not GPR or FPR";
139 unsigned PPC32RegisterInfo::isLoadFromStackSlot(MachineInstr *MI,
140 int &FrameIndex) const {
141 switch (MI->getOpcode()) {
145 if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImmedValue() &&
146 MI->getOperand(2).isFrameIndex()) {
147 FrameIndex = MI->getOperand(2).getFrameIndex();
148 return MI->getOperand(0).getReg();
155 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
156 /// copy instructions, turning them into load/store instructions.
157 MachineInstr *PPC32RegisterInfo::foldMemoryOperand(MachineInstr *MI,
159 int FrameIndex) const {
160 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
161 // it takes more than one instruction to store it.
162 unsigned Opc = MI->getOpcode();
164 if ((Opc == PPC::OR &&
165 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
166 if (OpNum == 0) { // move -> store
167 unsigned InReg = MI->getOperand(1).getReg();
168 return addFrameReference(BuildMI(PPC::STW,
169 3).addReg(InReg), FrameIndex);
170 } else { // move -> load
171 unsigned OutReg = MI->getOperand(0).getReg();
172 return addFrameReference(BuildMI(PPC::LWZ, 2, OutReg), FrameIndex);
175 } else if (Opc == PPC::FMR) {
176 // We currently always spill FP values as doubles. :(
177 if (OpNum == 0) { // move -> store
178 unsigned InReg = MI->getOperand(1).getReg();
179 return addFrameReference(BuildMI(PPC::STFD,
180 3).addReg(InReg), FrameIndex);
181 } else { // move -> load
182 unsigned OutReg = MI->getOperand(0).getReg();
183 return addFrameReference(BuildMI(PPC::LFD, 2, OutReg), FrameIndex);
189 //===----------------------------------------------------------------------===//
190 // Stack Frame Processing methods
191 //===----------------------------------------------------------------------===//
193 // hasFP - Return true if the specified function should have a dedicated frame
194 // pointer register. This is true if the function has variable sized allocas or
195 // if frame pointer elimination is disabled.
197 static bool hasFP(MachineFunction &MF) {
198 return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
201 void PPC32RegisterInfo::
202 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
203 MachineBasicBlock::iterator I) const {
205 // If we have a frame pointer, convert as follows:
206 // ADJCALLSTACKDOWN -> addi, r1, r1, -amount
207 // ADJCALLSTACKUP -> addi, r1, r1, amount
208 MachineInstr *Old = I;
209 unsigned Amount = Old->getOperand(0).getImmedValue();
211 // We need to keep the stack aligned properly. To do this, we round the
212 // amount of space needed for the outgoing arguments up to the next
213 // alignment boundary.
214 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
215 Amount = (Amount+Align-1)/Align*Align;
217 // Replace the pseudo instruction with a new instruction...
218 if (Old->getOpcode() == PPC::ADJCALLSTACKDOWN) {
219 MBB.insert(I, BuildMI(PPC::ADDI, 2, PPC::R1).addReg(PPC::R1)
222 assert(Old->getOpcode() == PPC::ADJCALLSTACKUP);
223 MBB.insert(I, BuildMI(PPC::ADDI, 2, PPC::R1).addReg(PPC::R1)
232 PPC32RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
234 MachineInstr &MI = *II;
235 MachineBasicBlock &MBB = *MI.getParent();
236 MachineFunction &MF = *MBB.getParent();
238 while (!MI.getOperand(i).isFrameIndex()) {
240 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
243 int FrameIndex = MI.getOperand(i).getFrameIndex();
245 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
246 MI.SetMachineOperandReg(i, hasFP(MF) ? PPC::R31 : PPC::R1);
248 // Take into account whether it's an add or mem instruction
249 unsigned OffIdx = (i == 2) ? 1 : 2;
251 // Now add the frame object offset to the offset from r1.
252 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
253 MI.getOperand(OffIdx).getImmedValue();
255 // If we're not using a Frame Pointer that has been set to the value of the
256 // SP before having the stack size subtracted from it, then add the stack size
257 // to Offset to get the correct offset.
258 Offset += MF.getFrameInfo()->getStackSize();
260 if (Offset > 32767 || Offset < -32768) {
261 // Insert a set of r0 with the full offset value before the ld, st, or add
262 MachineBasicBlock *MBB = MI.getParent();
263 MBB->insert(II, BuildMI(PPC::LIS, 1, PPC::R0).addSImm(Offset >> 16));
264 MBB->insert(II, BuildMI(PPC::ORI, 2, PPC::R0).addReg(PPC::R0)
266 // convert into indexed form of the instruction
267 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
268 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
269 assert(ImmToIdxMap.count(MI.getOpcode()) &&
270 "No indexed form of load or store available!");
271 unsigned NewOpcode = ImmToIdxMap.find(MI.getOpcode())->second;
272 MI.setOpcode(NewOpcode);
273 MI.SetMachineOperandReg(1, MI.getOperand(i).getReg());
274 MI.SetMachineOperandReg(2, PPC::R0);
276 MI.SetMachineOperandConst(OffIdx,MachineOperand::MO_SignExtendedImmed,Offset);
281 void PPC32RegisterInfo::emitPrologue(MachineFunction &MF) const {
282 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
283 MachineBasicBlock::iterator MBBI = MBB.begin();
284 MachineFrameInfo *MFI = MF.getFrameInfo();
287 // Get the number of bytes to allocate from the FrameInfo
288 unsigned NumBytes = MFI->getStackSize();
290 // If we have calls, we cannot use the red zone to store callee save registers
291 // and we must set up a stack frame, so calculate the necessary size here.
292 if (MFI->hasCalls()) {
293 // We reserve argument space for call sites in the function immediately on
294 // entry to the current function. This eliminates the need for add/sub
295 // brackets around call sites.
296 NumBytes += MFI->getMaxCallFrameSize();
299 // If we are a leaf function, and use up to 224 bytes of stack space,
300 // and don't have a frame pointer, then we do not need to adjust the stack
301 // pointer (we fit in the Red Zone).
302 if ((NumBytes == 0) || (NumBytes <= 224 && !hasFP(MF) && !MFI->hasCalls())) {
303 MFI->setStackSize(0);
307 // Add the size of R1 to NumBytes size for the store of R1 to the bottom
308 // of the stack and round the size to a multiple of the alignment.
309 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
310 unsigned GPRSize = 4;
311 unsigned Size = hasFP(MF) ? GPRSize + GPRSize : GPRSize;
312 NumBytes = (NumBytes+Size+Align-1)/Align*Align;
314 // Update frame info to pretend that this is part of the stack...
315 MFI->setStackSize(NumBytes);
317 // Adjust stack pointer: r1 -= numbytes.
318 if (NumBytes <= 32768) {
319 MI=BuildMI(PPC::STWU,3).addReg(PPC::R1).addSImm(-NumBytes).addReg(PPC::R1);
320 MBB.insert(MBBI, MI);
322 int NegNumbytes = -NumBytes;
323 MI = BuildMI(PPC::LIS, 1, PPC::R0).addSImm(NegNumbytes >> 16);
324 MBB.insert(MBBI, MI);
325 MI = BuildMI(PPC::ORI, 2, PPC::R0).addReg(PPC::R0)
326 .addImm(NegNumbytes & 0xFFFF);
327 MBB.insert(MBBI, MI);
328 MI = BuildMI(PPC::STWUX, 3).addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
329 MBB.insert(MBBI, MI);
333 MI = BuildMI(PPC::STW, 3).addReg(PPC::R31).addSImm(GPRSize).addReg(PPC::R1);
334 MBB.insert(MBBI, MI);
335 MI = BuildMI(PPC::OR, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1);
336 MBB.insert(MBBI, MI);
340 void PPC32RegisterInfo::emitEpilogue(MachineFunction &MF,
341 MachineBasicBlock &MBB) const {
342 const MachineFrameInfo *MFI = MF.getFrameInfo();
343 MachineBasicBlock::iterator MBBI = prior(MBB.end());
345 assert(MBBI->getOpcode() == PPC::BLR &&
346 "Can only insert epilog into returning blocks");
348 // Get the number of bytes allocated from the FrameInfo...
349 unsigned NumBytes = MFI->getStackSize();
350 unsigned GPRSize = 4;
354 MI = BuildMI(PPC::LWZ, 2, PPC::R31).addSImm(GPRSize).addReg(PPC::R31);
355 MBB.insert(MBBI, MI);
357 MI = BuildMI(PPC::LWZ, 2, PPC::R1).addSImm(0).addReg(PPC::R1);
358 MBB.insert(MBBI, MI);
362 #include "PPC32GenRegisterInfo.inc"