1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetRegisterInfo
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "reginfo"
17 #include "PPCInstrBuilder.h"
18 #include "PPCMachineFunctionInfo.h"
19 #include "PPCRegisterInfo.h"
20 #include "PPCFrameInfo.h"
21 #include "PPCSubtarget.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Type.h"
24 #include "llvm/CodeGen/ValueTypes.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineModuleInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineLocation.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/RegisterScavenging.h"
32 #include "llvm/CodeGen/SelectionDAGNodes.h"
33 #include "llvm/Target/TargetFrameInfo.h"
34 #include "llvm/Target/TargetInstrInfo.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
37 #include "llvm/Support/CommandLine.h"
38 #include "llvm/Support/Debug.h"
39 #include "llvm/Support/MathExtras.h"
40 #include "llvm/ADT/BitVector.h"
41 #include "llvm/ADT/STLExtras.h"
45 // FIXME This disables some code that aligns the stack to a boundary
46 // bigger than the default (16 bytes on Darwin) when there is a stack local
47 // of greater alignment. This does not currently work, because the delta
48 // between old and new stack pointers is added to offsets that reference
49 // incoming parameters after the prolog is generated, and the code that
50 // does that doesn't handle a variable delta. You don't want to do that
51 // anyway; a better approach is to reserve another register that retains
52 // to the incoming stack pointer, and reference parameters relative to that.
55 // FIXME (64-bit): Eventually enable by default.
56 cl::opt<bool> EnablePPC32RS("enable-ppc32-regscavenger",
58 cl::desc("Enable PPC32 register scavenger"),
60 cl::opt<bool> EnablePPC64RS("enable-ppc64-regscavenger",
62 cl::desc("Enable PPC64 register scavenger"),
64 #define EnableRegisterScavenging \
65 ((EnablePPC32RS && !Subtarget.isPPC64()) || \
66 (EnablePPC64RS && Subtarget.isPPC64()))
68 // FIXME (64-bit): Should be inlined.
70 PPCRegisterInfo::requiresRegisterScavenging(const MachineFunction &) const {
71 return EnableRegisterScavenging;
74 /// getRegisterNumbering - Given the enum value for some register, e.g.
75 /// PPC::F14, return the number that it corresponds to (e.g. 14).
76 unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
80 case R0 : case X0 : case F0 : case V0 : case CR0: case CR0LT: return 0;
81 case R1 : case X1 : case F1 : case V1 : case CR1: case CR0GT: return 1;
82 case R2 : case X2 : case F2 : case V2 : case CR2: case CR0EQ: return 2;
83 case R3 : case X3 : case F3 : case V3 : case CR3: case CR0UN: return 3;
84 case R4 : case X4 : case F4 : case V4 : case CR4: case CR1LT: return 4;
85 case R5 : case X5 : case F5 : case V5 : case CR5: case CR1GT: return 5;
86 case R6 : case X6 : case F6 : case V6 : case CR6: case CR1EQ: return 6;
87 case R7 : case X7 : case F7 : case V7 : case CR7: case CR1UN: return 7;
88 case R8 : case X8 : case F8 : case V8 : case CR2LT: return 8;
89 case R9 : case X9 : case F9 : case V9 : case CR2GT: return 9;
90 case R10: case X10: case F10: case V10: case CR2EQ: return 10;
91 case R11: case X11: case F11: case V11: case CR2UN: return 11;
92 case R12: case X12: case F12: case V12: case CR3LT: return 12;
93 case R13: case X13: case F13: case V13: case CR3GT: return 13;
94 case R14: case X14: case F14: case V14: case CR3EQ: return 14;
95 case R15: case X15: case F15: case V15: case CR3UN: return 15;
96 case R16: case X16: case F16: case V16: case CR4LT: return 16;
97 case R17: case X17: case F17: case V17: case CR4GT: return 17;
98 case R18: case X18: case F18: case V18: case CR4EQ: return 18;
99 case R19: case X19: case F19: case V19: case CR4UN: return 19;
100 case R20: case X20: case F20: case V20: case CR5LT: return 20;
101 case R21: case X21: case F21: case V21: case CR5GT: return 21;
102 case R22: case X22: case F22: case V22: case CR5EQ: return 22;
103 case R23: case X23: case F23: case V23: case CR5UN: return 23;
104 case R24: case X24: case F24: case V24: case CR6LT: return 24;
105 case R25: case X25: case F25: case V25: case CR6GT: return 25;
106 case R26: case X26: case F26: case V26: case CR6EQ: return 26;
107 case R27: case X27: case F27: case V27: case CR6UN: return 27;
108 case R28: case X28: case F28: case V28: case CR7LT: return 28;
109 case R29: case X29: case F29: case V29: case CR7GT: return 29;
110 case R30: case X30: case F30: case V30: case CR7EQ: return 30;
111 case R31: case X31: case F31: case V31: case CR7UN: return 31;
113 cerr << "Unhandled reg in PPCRegisterInfo::getRegisterNumbering!\n";
118 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST,
119 const TargetInstrInfo &tii)
120 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
121 Subtarget(ST), TII(tii) {
122 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
123 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
124 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
125 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
126 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
127 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
128 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
129 ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
132 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8;
133 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8;
134 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8;
135 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX;
136 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32;
139 void PPCRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
140 MachineBasicBlock::iterator I,
142 const MachineInstr *Orig) const {
143 MachineInstr *MI = Orig->clone();
144 MI->getOperand(0).setReg(DestReg);
149 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
150 // 32-bit Darwin calling convention.
151 static const unsigned Macho32_CalleeSavedRegs[] = {
152 PPC::R13, PPC::R14, PPC::R15,
153 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
154 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
155 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
156 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
158 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
159 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
160 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
161 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
164 PPC::CR2, PPC::CR3, PPC::CR4,
165 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
166 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
167 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
169 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
170 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
171 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
176 static const unsigned ELF32_CalleeSavedRegs[] = {
177 PPC::R13, PPC::R14, PPC::R15,
178 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
179 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
180 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
181 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
184 PPC::F10, PPC::F11, PPC::F12, PPC::F13,
185 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
186 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
187 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
188 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
191 PPC::CR2, PPC::CR3, PPC::CR4,
192 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
193 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
194 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
196 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
197 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
198 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
202 // 64-bit Darwin calling convention.
203 static const unsigned Macho64_CalleeSavedRegs[] = {
205 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
206 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
207 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
208 PPC::X28, PPC::X29, PPC::X30, PPC::X31,
210 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
211 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
212 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
213 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
216 PPC::CR2, PPC::CR3, PPC::CR4,
217 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
218 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
219 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
221 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
222 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
223 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
228 if (Subtarget.isMachoABI())
229 return Subtarget.isPPC64() ? Macho64_CalleeSavedRegs :
230 Macho32_CalleeSavedRegs;
233 return ELF32_CalleeSavedRegs;
236 const TargetRegisterClass* const*
237 PPCRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
238 // 32-bit Macho calling convention.
239 static const TargetRegisterClass * const Macho32_CalleeSavedRegClasses[] = {
240 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
241 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
242 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
243 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
244 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
246 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
247 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
248 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
249 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
250 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
252 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
254 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
255 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
256 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
258 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
259 &PPC::CRBITRCRegClass,
260 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
261 &PPC::CRBITRCRegClass,
262 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
263 &PPC::CRBITRCRegClass,
265 &PPC::GPRCRegClass, 0
268 static const TargetRegisterClass * const ELF32_CalleeSavedRegClasses[] = {
269 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
270 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
271 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
272 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
273 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
276 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
277 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
278 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
279 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
280 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
281 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
283 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
285 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
286 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
287 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
289 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
290 &PPC::CRBITRCRegClass,
291 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
292 &PPC::CRBITRCRegClass,
293 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
294 &PPC::CRBITRCRegClass,
296 &PPC::GPRCRegClass, 0
299 // 64-bit Macho calling convention.
300 static const TargetRegisterClass * const Macho64_CalleeSavedRegClasses[] = {
301 &PPC::G8RCRegClass,&PPC::G8RCRegClass,
302 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
303 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
304 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
305 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
307 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
308 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
309 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
310 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
311 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
313 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
315 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
316 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
317 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
319 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
320 &PPC::CRBITRCRegClass,
321 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
322 &PPC::CRBITRCRegClass,
323 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
324 &PPC::CRBITRCRegClass,
326 &PPC::G8RCRegClass, 0
329 if (Subtarget.isMachoABI())
330 return Subtarget.isPPC64() ? Macho64_CalleeSavedRegClasses :
331 Macho32_CalleeSavedRegClasses;
334 return ELF32_CalleeSavedRegClasses;
337 // needsFP - Return true if the specified function should have a dedicated frame
338 // pointer register. This is true if the function has variable sized allocas or
339 // if frame pointer elimination is disabled.
341 static bool needsFP(const MachineFunction &MF) {
342 const MachineFrameInfo *MFI = MF.getFrameInfo();
343 return NoFramePointerElim || MFI->hasVarSizedObjects();
346 static bool spillsCR(const MachineFunction &MF) {
347 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
348 return FuncInfo->isCRSpilled();
351 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
352 BitVector Reserved(getNumRegs());
353 Reserved.set(PPC::R0);
354 Reserved.set(PPC::R1);
355 Reserved.set(PPC::LR);
356 Reserved.set(PPC::LR8);
358 // In Linux, r2 is reserved for the OS.
359 if (!Subtarget.isDarwin())
360 Reserved.set(PPC::R2);
362 // On PPC64, r13 is the thread pointer. Never allocate this register. Note
363 // that this is over conservative, as it also prevents allocation of R31 when
364 // the FP is not needed.
365 if (Subtarget.isPPC64()) {
366 Reserved.set(PPC::R13);
367 Reserved.set(PPC::R31);
369 if (!EnableRegisterScavenging)
370 Reserved.set(PPC::R0); // FIXME (64-bit): Remove
372 Reserved.set(PPC::X0);
373 Reserved.set(PPC::X1);
374 Reserved.set(PPC::X13);
375 Reserved.set(PPC::X31);
379 Reserved.set(PPC::R31);
384 //===----------------------------------------------------------------------===//
385 // Stack Frame Processing methods
386 //===----------------------------------------------------------------------===//
388 // hasFP - Return true if the specified function actually has a dedicated frame
389 // pointer register. This is true if the function needs a frame pointer and has
390 // a non-zero stack size.
391 bool PPCRegisterInfo::hasFP(const MachineFunction &MF) const {
392 const MachineFrameInfo *MFI = MF.getFrameInfo();
393 return MFI->getStackSize() && needsFP(MF);
396 /// MustSaveLR - Return true if this function requires that we save the LR
397 /// register onto the stack in the prolog and restore it in the epilog of the
399 static bool MustSaveLR(const MachineFunction &MF) {
400 const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>();
402 // We need an save/restore of LR if there is any use/def of LR explicitly, or
403 // if there is some use of the LR stack slot (e.g. for builtin_return_address.
404 return MFI->usesLR() || MFI->isLRStoreRequired() ||
405 // FIXME: Anything that has a call should clobber the LR register,
406 // isn't this redundant??
407 MF.getFrameInfo()->hasCalls();
410 void PPCRegisterInfo::
411 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
412 MachineBasicBlock::iterator I) const {
413 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
417 /// findScratchRegister - Find a 'free' PPC register. Try for a call-clobbered
418 /// register first and then a spilled callee-saved register if that fails.
420 unsigned findScratchRegister(MachineBasicBlock::iterator II, RegScavenger *RS,
421 const TargetRegisterClass *RC, int SPAdj) {
422 assert(RS && "Register scavenging must be on");
423 unsigned Reg = RS->FindUnusedReg(RC, true);
424 // FIXME: move ARM callee-saved reg scan to target independent code, then
425 // search for already spilled CS register here.
427 Reg = RS->scavengeRegister(RC, II, SPAdj);
431 /// lowerDynamicAlloc - Generate the code for allocating an object in the
432 /// current frame. The sequence of code with be in the general form
434 /// addi R0, SP, #frameSize ; get the address of the previous frame
435 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size
436 /// addi Rnew, SP, #maxCalFrameSize ; get the top of the allocation
438 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II,
439 int SPAdj, RegScavenger *RS) const {
440 // Get the instruction.
441 MachineInstr &MI = *II;
442 // Get the instruction's basic block.
443 MachineBasicBlock &MBB = *MI.getParent();
444 // Get the basic block's function.
445 MachineFunction &MF = *MBB.getParent();
446 // Get the frame info.
447 MachineFrameInfo *MFI = MF.getFrameInfo();
448 // Determine whether 64-bit pointers are used.
449 bool LP64 = Subtarget.isPPC64();
451 // Get the maximum call stack size.
452 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
453 // Get the total frame size.
454 unsigned FrameSize = MFI->getStackSize();
456 // Get stack alignments.
457 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
458 unsigned MaxAlign = MFI->getMaxAlignment();
459 assert(MaxAlign <= TargetAlign &&
460 "Dynamic alloca with large aligns not supported");
462 // Determine the previous frame's address. If FrameSize can't be
463 // represented as 16 bits or we need special alignment, then we load the
464 // previous frame's address from 0(SP). Why not do an addis of the hi?
465 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
466 // Constructing the constant and adding would take 3 instructions.
467 // Fortunately, a frame greater than 32K is rare.
468 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
469 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
470 const TargetRegisterClass *RC = LP64 ? G8RC : GPRC;
472 // FIXME (64-bit): Use "findScratchRegister"
474 if (EnableRegisterScavenging)
475 Reg = findScratchRegister(II, RS, RC, SPAdj);
479 if (MaxAlign < TargetAlign && isInt16(FrameSize)) {
480 BuildMI(MBB, II, TII.get(PPC::ADDI), Reg)
484 if (EnableRegisterScavenging) // FIXME (64-bit): Use "true" part.
485 BuildMI(MBB, II, TII.get(PPC::LD), Reg)
489 BuildMI(MBB, II, TII.get(PPC::LD), PPC::X0)
493 BuildMI(MBB, II, TII.get(PPC::LWZ), Reg)
498 // Grow the stack and update the stack pointer link, then determine the
499 // address of new allocated space.
501 if (EnableRegisterScavenging) // FIXME (64-bit): Use "true" part.
502 BuildMI(MBB, II, TII.get(PPC::STDUX))
503 .addReg(Reg, false, false, true)
505 .addReg(MI.getOperand(1).getReg());
507 BuildMI(MBB, II, TII.get(PPC::STDUX))
508 .addReg(PPC::X0, false, false, true)
510 .addReg(MI.getOperand(1).getReg());
512 if (!MI.getOperand(1).isKill())
513 BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
515 .addImm(maxCallFrameSize);
517 // Implicitly kill the register.
518 BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
520 .addImm(maxCallFrameSize)
521 .addReg(MI.getOperand(1).getReg(), false, true, true);
523 BuildMI(MBB, II, TII.get(PPC::STWUX))
524 .addReg(Reg, false, false, true)
526 .addReg(MI.getOperand(1).getReg());
528 if (!MI.getOperand(1).isKill())
529 BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
531 .addImm(maxCallFrameSize);
533 // Implicitly kill the register.
534 BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
536 .addImm(maxCallFrameSize)
537 .addReg(MI.getOperand(1).getReg(), false, true, true);
540 // Discard the DYNALLOC instruction.
544 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of
545 /// reserving a whole register (R0), we scrounge for one here. This generates
548 /// mfcr rA ; Move the conditional register into GPR rA.
549 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot.
550 /// stw rA, FI ; Store rA to the frame.
552 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II,
553 unsigned FrameIndex, int SPAdj,
554 RegScavenger *RS) const {
555 // Get the instruction.
556 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>, <FI>
557 // Get the instruction's basic block.
558 MachineBasicBlock &MBB = *MI.getParent();
560 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
561 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
562 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC;
563 unsigned Reg = findScratchRegister(II, RS, RC, SPAdj);
565 // We need to store the CR in the low 4-bits of the saved value. First, issue
566 // an MFCR to save all of the CRBits. Add an implicit kill of the CR.
567 if (!MI.getOperand(0).isKill())
568 BuildMI(MBB, II, TII.get(PPC::MFCR), Reg);
570 // Implicitly kill the CR register.
571 BuildMI(MBB, II, TII.get(PPC::MFCR), Reg)
572 .addReg(MI.getOperand(0).getReg(), false, true, true);
574 // If the saved register wasn't CR0, shift the bits left so that they are in
576 unsigned SrcReg = MI.getOperand(0).getReg();
577 if (SrcReg != PPC::CR0)
578 // rlwinm rA, rA, ShiftBits, 0, 31.
579 BuildMI(MBB, II, TII.get(PPC::RLWINM), Reg)
580 .addReg(Reg, false, false, true)
581 .addImm(PPCRegisterInfo::getRegisterNumbering(SrcReg) * 4)
585 addFrameReference(BuildMI(MBB, II, TII.get(PPC::STW))
586 .addReg(Reg, false, false, MI.getOperand(1).getImm()),
589 // Discard the pseudo instruction.
593 void PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
594 int SPAdj, RegScavenger *RS) const {
595 assert(SPAdj == 0 && "Unexpected");
597 // Get the instruction.
598 MachineInstr &MI = *II;
599 // Get the instruction's basic block.
600 MachineBasicBlock &MBB = *MI.getParent();
601 // Get the basic block's function.
602 MachineFunction &MF = *MBB.getParent();
603 // Get the frame info.
604 MachineFrameInfo *MFI = MF.getFrameInfo();
606 // Find out which operand is the frame index.
607 unsigned FIOperandNo = 0;
608 while (!MI.getOperand(FIOperandNo).isFrameIndex()) {
610 assert(FIOperandNo != MI.getNumOperands() &&
611 "Instr doesn't have FrameIndex operand!");
613 // Take into account whether it's an add or mem instruction
614 unsigned OffsetOperandNo = (FIOperandNo == 2) ? 1 : 2;
615 if (MI.getOpcode() == TargetInstrInfo::INLINEASM)
616 OffsetOperandNo = FIOperandNo-1;
618 // Get the frame index.
619 int FrameIndex = MI.getOperand(FIOperandNo).getIndex();
621 // Get the frame pointer save index. Users of this index are primarily
622 // DYNALLOC instructions.
623 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
624 int FPSI = FI->getFramePointerSaveIndex();
625 // Get the instruction opcode.
626 unsigned OpC = MI.getOpcode();
628 // Special case for dynamic alloca.
629 if (FPSI && FrameIndex == FPSI &&
630 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
631 lowerDynamicAlloc(II, SPAdj, RS);
635 // Special case for pseudo-op SPILL_CR.
636 if (EnableRegisterScavenging) // FIXME (64-bit): Enable by default.
637 if (OpC == PPC::SPILL_CR) {
638 lowerCRSpilling(II, FrameIndex, SPAdj, RS);
642 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
643 MI.getOperand(FIOperandNo).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1,
646 // Figure out if the offset in the instruction is shifted right two bits. This
647 // is true for instructions like "STD", which the machine implicitly adds two
649 bool isIXAddr = false;
659 // Now add the frame object offset to the offset from r1.
660 int Offset = MFI->getObjectOffset(FrameIndex);
662 Offset += MI.getOperand(OffsetOperandNo).getImm();
664 Offset += MI.getOperand(OffsetOperandNo).getImm() << 2;
666 // If we're not using a Frame Pointer that has been set to the value of the
667 // SP before having the stack size subtracted from it, then add the stack size
668 // to Offset to get the correct offset.
669 Offset += MFI->getStackSize();
671 // If we can, encode the offset directly into the instruction. If this is a
672 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If
673 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits
674 // clear can be encoded. This is extremely uncommon, because normally you
675 // only "std" to a stack slot that is at least 4-byte aligned, but it can
676 // happen in invalid code.
677 if (isInt16(Offset) && (!isIXAddr || (Offset & 3) == 0)) {
679 Offset >>= 2; // The actual encoded value has the low two bits zero.
680 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
684 // The offset doesn't fit into a single register, scavenge one to build the
686 // FIXME: figure out what SPAdj is doing here.
688 // FIXME (64-bit): Use "findScratchRegister".
690 if (EnableRegisterScavenging)
691 SReg = findScratchRegister(II, RS, &PPC::GPRCRegClass, SPAdj);
695 // Insert a set of rA with the full offset value before the ld, st, or add
696 BuildMI(MBB, II, TII.get(PPC::LIS), SReg)
697 .addImm(Offset >> 16);
698 BuildMI(MBB, II, TII.get(PPC::ORI), SReg)
699 .addReg(SReg, false, false, true)
702 // Convert into indexed form of the instruction:
704 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
705 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
706 unsigned OperandBase;
708 if (OpC != TargetInstrInfo::INLINEASM) {
709 assert(ImmToIdxMap.count(OpC) &&
710 "No indexed form of load or store available!");
711 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second;
712 MI.setDesc(TII.get(NewOpcode));
715 OperandBase = OffsetOperandNo;
718 unsigned StackReg = MI.getOperand(FIOperandNo).getReg();
719 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false);
720 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false);
723 /// VRRegNo - Map from a numbered VR register to its enum value.
725 static const unsigned short VRRegNo[] = {
726 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
727 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
728 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
729 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
732 /// RemoveVRSaveCode - We have found that this function does not need any code
733 /// to manipulate the VRSAVE register, even though it uses vector registers.
734 /// This can happen when the only registers used are known to be live in or out
735 /// of the function. Remove all of the VRSAVE related code from the function.
736 static void RemoveVRSaveCode(MachineInstr *MI) {
737 MachineBasicBlock *Entry = MI->getParent();
738 MachineFunction *MF = Entry->getParent();
740 // We know that the MTVRSAVE instruction immediately follows MI. Remove it.
741 MachineBasicBlock::iterator MBBI = MI;
743 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
744 MBBI->eraseFromParent();
746 bool RemovedAllMTVRSAVEs = true;
747 // See if we can find and remove the MTVRSAVE instruction from all of the
749 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
750 // If last instruction is a return instruction, add an epilogue
751 if (!I->empty() && I->back().getDesc().isReturn()) {
752 bool FoundIt = false;
753 for (MBBI = I->end(); MBBI != I->begin(); ) {
755 if (MBBI->getOpcode() == PPC::MTVRSAVE) {
756 MBBI->eraseFromParent(); // remove it.
761 RemovedAllMTVRSAVEs &= FoundIt;
765 // If we found and removed all MTVRSAVE instructions, remove the read of
767 if (RemovedAllMTVRSAVEs) {
769 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
771 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
772 MBBI->eraseFromParent();
775 // Finally, nuke the UPDATE_VRSAVE.
776 MI->eraseFromParent();
779 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
780 // instruction selector. Based on the vector registers that have been used,
781 // transform this into the appropriate ORI instruction.
782 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) {
783 MachineFunction *MF = MI->getParent()->getParent();
785 unsigned UsedRegMask = 0;
786 for (unsigned i = 0; i != 32; ++i)
787 if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i]))
788 UsedRegMask |= 1 << (31-i);
790 // Live in and live out values already must be in the mask, so don't bother
792 for (MachineRegisterInfo::livein_iterator
793 I = MF->getRegInfo().livein_begin(),
794 E = MF->getRegInfo().livein_end(); I != E; ++I) {
795 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first);
796 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg.
797 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
799 for (MachineRegisterInfo::liveout_iterator
800 I = MF->getRegInfo().liveout_begin(),
801 E = MF->getRegInfo().liveout_end(); I != E; ++I) {
802 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I);
803 if (VRRegNo[RegNo] == *I) // If this really is a vector reg.
804 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
807 // If no registers are used, turn this into a copy.
808 if (UsedRegMask == 0) {
809 // Remove all VRSAVE code.
810 RemoveVRSaveCode(MI);
814 unsigned SrcReg = MI->getOperand(1).getReg();
815 unsigned DstReg = MI->getOperand(0).getReg();
817 if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
818 if (DstReg != SrcReg)
819 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg)
821 .addImm(UsedRegMask);
823 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg)
824 .addReg(SrcReg, false, false, true)
825 .addImm(UsedRegMask);
826 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
827 if (DstReg != SrcReg)
828 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
830 .addImm(UsedRegMask >> 16);
832 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
833 .addReg(SrcReg, false, false, true)
834 .addImm(UsedRegMask >> 16);
836 if (DstReg != SrcReg)
837 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
839 .addImm(UsedRegMask >> 16);
841 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
842 .addReg(SrcReg, false, false, true)
843 .addImm(UsedRegMask >> 16);
845 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg)
846 .addReg(DstReg, false, false, true)
847 .addImm(UsedRegMask & 0xFFFF);
850 // Remove the old UPDATE_VRSAVE instruction.
851 MI->eraseFromParent();
854 /// determineFrameLayout - Determine the size of the frame and maximum call
856 void PPCRegisterInfo::determineFrameLayout(MachineFunction &MF) const {
857 MachineFrameInfo *MFI = MF.getFrameInfo();
859 // Get the number of bytes to allocate from the FrameInfo
860 unsigned FrameSize = MFI->getStackSize();
862 // Get the alignments provided by the target, and the maximum alignment
863 // (if any) of the fixed frame objects.
864 unsigned MaxAlign = MFI->getMaxAlignment();
865 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
866 unsigned AlignMask = TargetAlign - 1; //
868 // If we are a leaf function, and use up to 224 bytes of stack space,
869 // don't have a frame pointer, calls, or dynamic alloca then we do not need
870 // to adjust the stack pointer (we fit in the Red Zone).
871 if (FrameSize <= 224 && // Fits in red zone.
872 !MFI->hasVarSizedObjects() && // No dynamic alloca.
873 !MFI->hasCalls() && // No calls.
874 (!ALIGN_STACK || MaxAlign <= TargetAlign)) { // No special alignment.
876 MFI->setStackSize(0);
880 // Get the maximum call frame size of all the calls.
881 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
883 // Maximum call frame needs to be at least big enough for linkage and 8 args.
884 unsigned minCallFrameSize =
885 PPCFrameInfo::getMinCallFrameSize(Subtarget.isPPC64(),
886 Subtarget.isMachoABI());
887 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
889 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
890 // that allocations will be aligned.
891 if (MFI->hasVarSizedObjects())
892 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
894 // Update maximum call frame size.
895 MFI->setMaxCallFrameSize(maxCallFrameSize);
897 // Include call frame size in total.
898 FrameSize += maxCallFrameSize;
900 // Make sure the frame is aligned.
901 FrameSize = (FrameSize + AlignMask) & ~AlignMask;
903 // Update frame info.
904 MFI->setStackSize(FrameSize);
908 PPCRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
909 RegScavenger *RS) const {
910 // Save and clear the LR state.
911 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
912 unsigned LR = getRARegister();
913 FI->setUsesLR(MF.getRegInfo().isPhysRegUsed(LR));
914 MF.getRegInfo().setPhysRegUnused(LR);
916 // Save R31 if necessary
917 int FPSI = FI->getFramePointerSaveIndex();
918 bool IsPPC64 = Subtarget.isPPC64();
919 bool IsELF32_ABI = Subtarget.isELF32_ABI();
920 bool IsMachoABI = Subtarget.isMachoABI();
921 MachineFrameInfo *MFI = MF.getFrameInfo();
923 // If the frame pointer save index hasn't been defined yet.
924 if (!FPSI && (NoFramePointerElim || MFI->hasVarSizedObjects()) &&
926 // Find out what the fix offset of the frame pointer save area.
927 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64,
929 // Allocate the frame index for frame pointer save area.
930 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset);
932 FI->setFramePointerSaveIndex(FPSI);
935 // Reserve a slot closest to SP or frame pointer if we have a dynalloc or
936 // a large stack, which will require scavenging a register to materialize a
938 // FIXME: this doesn't actually check stack size, so is a bit pessimistic
939 // FIXME: doesn't detect whether or not we need to spill vXX, which requires
942 if (EnableRegisterScavenging) // FIXME (64-bit): Enable.
943 if (needsFP(MF) || spillsCR(MF)) {
944 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
945 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
946 const TargetRegisterClass *RC = IsPPC64 ? G8RC : GPRC;
947 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
948 RC->getAlignment()));
953 PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
954 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
955 MachineBasicBlock::iterator MBBI = MBB.begin();
956 MachineFrameInfo *MFI = MF.getFrameInfo();
957 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
959 // Prepare for frame info.
960 unsigned FrameLabelId = 0;
962 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
964 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
965 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
966 HandleVRSaveUpdate(MBBI, TII);
971 // Move MBBI back to the beginning of the function.
974 // Work out frame sizes.
975 determineFrameLayout(MF);
976 unsigned FrameSize = MFI->getStackSize();
978 int NegFrameSize = -FrameSize;
980 // Get processor type.
981 bool IsPPC64 = Subtarget.isPPC64();
982 // Get operating system
983 bool IsMachoABI = Subtarget.isMachoABI();
984 // Check if the link register (LR) has been used.
985 bool UsesLR = MustSaveLR(MF);
986 // Do we have a frame pointer for this function?
987 bool HasFP = hasFP(MF) && FrameSize;
989 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI);
990 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI);
994 BuildMI(MBB, MBBI, TII.get(PPC::MFLR8), PPC::X0);
997 BuildMI(MBB, MBBI, TII.get(PPC::STD))
1003 BuildMI(MBB, MBBI, TII.get(PPC::STD))
1005 .addImm(LROffset / 4)
1009 BuildMI(MBB, MBBI, TII.get(PPC::MFLR), PPC::R0);
1012 BuildMI(MBB, MBBI, TII.get(PPC::STW))
1018 BuildMI(MBB, MBBI, TII.get(PPC::STW))
1024 // Skip if a leaf routine.
1025 if (!FrameSize) return;
1027 // Get stack alignments.
1028 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
1029 unsigned MaxAlign = MFI->getMaxAlignment();
1031 if (MMI && MMI->needsFrameInfo()) {
1032 // Mark effective beginning of when frame pointer becomes valid.
1033 FrameLabelId = MMI->NextLabelID();
1034 BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(FrameLabelId).addImm(0);
1037 // Adjust stack pointer: r1 += NegFrameSize.
1038 // If there is a preferred stack alignment, align R1 now
1041 if (ALIGN_STACK && MaxAlign > TargetAlign) {
1042 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!");
1043 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!");
1045 BuildMI(MBB, MBBI, TII.get(PPC::RLWINM), PPC::R0)
1048 .addImm(32 - Log2_32(MaxAlign))
1050 BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC) ,PPC::R0)
1051 .addReg(PPC::R0, false, false, true)
1052 .addImm(NegFrameSize);
1053 BuildMI(MBB, MBBI, TII.get(PPC::STWUX))
1057 } else if (isInt16(NegFrameSize)) {
1058 BuildMI(MBB, MBBI, TII.get(PPC::STWU), PPC::R1)
1060 .addImm(NegFrameSize)
1063 BuildMI(MBB, MBBI, TII.get(PPC::LIS), PPC::R0)
1064 .addImm(NegFrameSize >> 16);
1065 BuildMI(MBB, MBBI, TII.get(PPC::ORI), PPC::R0)
1066 .addReg(PPC::R0, false, false, true)
1067 .addImm(NegFrameSize & 0xFFFF);
1068 BuildMI(MBB, MBBI, TII.get(PPC::STWUX))
1074 if (ALIGN_STACK && MaxAlign > TargetAlign) {
1075 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!");
1076 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!");
1078 BuildMI(MBB, MBBI, TII.get(PPC::RLDICL), PPC::X0)
1081 .addImm(64 - Log2_32(MaxAlign));
1082 BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC8), PPC::X0)
1084 .addImm(NegFrameSize);
1085 BuildMI(MBB, MBBI, TII.get(PPC::STDUX))
1089 } else if (isInt16(NegFrameSize)) {
1090 BuildMI(MBB, MBBI, TII.get(PPC::STDU), PPC::X1)
1092 .addImm(NegFrameSize / 4)
1095 BuildMI(MBB, MBBI, TII.get(PPC::LIS8), PPC::X0)
1096 .addImm(NegFrameSize >> 16);
1097 BuildMI(MBB, MBBI, TII.get(PPC::ORI8), PPC::X0)
1098 .addReg(PPC::X0, false, false, true)
1099 .addImm(NegFrameSize & 0xFFFF);
1100 BuildMI(MBB, MBBI, TII.get(PPC::STDUX))
1107 if (MMI && MMI->needsFrameInfo()) {
1108 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
1111 // Show update of SP.
1112 MachineLocation SPDst(MachineLocation::VirtualFP);
1113 MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize);
1114 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
1116 MachineLocation SP(IsPPC64 ? PPC::X31 : PPC::R31);
1117 Moves.push_back(MachineMove(FrameLabelId, SP, SP));
1121 MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset);
1122 MachineLocation FPSrc(IsPPC64 ? PPC::X31 : PPC::R31);
1123 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc));
1126 // Add callee saved registers to move list.
1127 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1128 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
1129 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
1130 unsigned Reg = CSI[I].getReg();
1131 if (Reg == PPC::LR || Reg == PPC::LR8) continue;
1132 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
1133 MachineLocation CSSrc(Reg);
1134 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
1137 MachineLocation LRDst(MachineLocation::VirtualFP, LROffset);
1138 MachineLocation LRSrc(IsPPC64 ? PPC::LR8 : PPC::LR);
1139 Moves.push_back(MachineMove(FrameLabelId, LRDst, LRSrc));
1141 // Mark effective beginning of when frame pointer is ready.
1142 unsigned ReadyLabelId = MMI->NextLabelID();
1143 BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(ReadyLabelId).addImm(0);
1145 MachineLocation FPDst(HasFP ? (IsPPC64 ? PPC::X31 : PPC::R31) :
1146 (IsPPC64 ? PPC::X1 : PPC::R1));
1147 MachineLocation FPSrc(MachineLocation::VirtualFP);
1148 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
1151 // If there is a frame pointer, copy R1 into R31
1154 BuildMI(MBB, MBBI, TII.get(PPC::OR), PPC::R31)
1158 BuildMI(MBB, MBBI, TII.get(PPC::OR8), PPC::X31)
1165 void PPCRegisterInfo::emitEpilogue(MachineFunction &MF,
1166 MachineBasicBlock &MBB) const {
1167 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1168 assert(MBBI->getOpcode() == PPC::BLR &&
1169 "Can only insert epilog into returning blocks");
1171 // Get alignment info so we know how to restore r1
1172 const MachineFrameInfo *MFI = MF.getFrameInfo();
1173 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
1174 unsigned MaxAlign = MFI->getMaxAlignment();
1176 // Get the number of bytes allocated from the FrameInfo.
1177 unsigned FrameSize = MFI->getStackSize();
1179 // Get processor type.
1180 bool IsPPC64 = Subtarget.isPPC64();
1181 // Get operating system
1182 bool IsMachoABI = Subtarget.isMachoABI();
1183 // Check if the link register (LR) has been used.
1184 bool UsesLR = MustSaveLR(MF);
1185 // Do we have a frame pointer for this function?
1186 bool HasFP = hasFP(MF) && FrameSize;
1188 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI);
1189 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI);
1192 // The loaded (or persistent) stack pointer value is offset by the 'stwu'
1193 // on entry to the function. Add this offset back now.
1194 if (!Subtarget.isPPC64()) {
1195 if (isInt16(FrameSize) && (!ALIGN_STACK || TargetAlign >= MaxAlign) &&
1196 !MFI->hasVarSizedObjects()) {
1197 BuildMI(MBB, MBBI, TII.get(PPC::ADDI), PPC::R1)
1198 .addReg(PPC::R1).addImm(FrameSize);
1200 BuildMI(MBB, MBBI, TII.get(PPC::LWZ),PPC::R1).addImm(0).addReg(PPC::R1);
1203 if (isInt16(FrameSize) && TargetAlign >= MaxAlign &&
1204 !MFI->hasVarSizedObjects()) {
1205 BuildMI(MBB, MBBI, TII.get(PPC::ADDI8), PPC::X1)
1206 .addReg(PPC::X1).addImm(FrameSize);
1208 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X1).addImm(0).addReg(PPC::X1);
1215 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X0)
1216 .addImm(LROffset/4).addReg(PPC::X1);
1219 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X31)
1220 .addImm(FPOffset/4).addReg(PPC::X1);
1223 BuildMI(MBB, MBBI, TII.get(PPC::MTLR8)).addReg(PPC::X0);
1226 BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R0)
1227 .addImm(LROffset).addReg(PPC::R1);
1230 BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R31)
1231 .addImm(FPOffset).addReg(PPC::R1);
1234 BuildMI(MBB, MBBI, TII.get(PPC::MTLR)).addReg(PPC::R0);
1238 unsigned PPCRegisterInfo::getRARegister() const {
1239 return !Subtarget.isPPC64() ? PPC::LR : PPC::LR8;
1242 unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const {
1243 if (!Subtarget.isPPC64())
1244 return hasFP(MF) ? PPC::R31 : PPC::R1;
1246 return hasFP(MF) ? PPC::X31 : PPC::X1;
1249 void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
1251 // Initial state of the frame pointer is R1.
1252 MachineLocation Dst(MachineLocation::VirtualFP);
1253 MachineLocation Src(PPC::R1, 0);
1254 Moves.push_back(MachineMove(0, Dst, Src));
1257 unsigned PPCRegisterInfo::getEHExceptionRegister() const {
1258 return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3;
1261 unsigned PPCRegisterInfo::getEHHandlerRegister() const {
1262 return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4;
1265 int PPCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
1266 // FIXME: Most probably dwarf numbers differs for Linux and Darwin
1267 return PPCGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
1270 #include "PPCGenRegisterInfo.inc"