1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "reginfo"
16 #include "PPCInstrBuilder.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "PPCRegisterInfo.h"
19 #include "PPCFrameInfo.h"
20 #include "PPCSubtarget.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Type.h"
23 #include "llvm/CodeGen/ValueTypes.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineModuleInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineLocation.h"
29 #include "llvm/CodeGen/SelectionDAGNodes.h"
30 #include "llvm/Target/TargetFrameInfo.h"
31 #include "llvm/Target/TargetInstrInfo.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Target/TargetOptions.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/ADT/BitVector.h"
38 #include "llvm/ADT/STLExtras.h"
42 /// getRegisterNumbering - Given the enum value for some register, e.g.
43 /// PPC::F14, return the number that it corresponds to (e.g. 14).
44 unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
47 case R0 : case X0 : case F0 : case V0 : case CR0: return 0;
48 case R1 : case X1 : case F1 : case V1 : case CR1: return 1;
49 case R2 : case X2 : case F2 : case V2 : case CR2: return 2;
50 case R3 : case X3 : case F3 : case V3 : case CR3: return 3;
51 case R4 : case X4 : case F4 : case V4 : case CR4: return 4;
52 case R5 : case X5 : case F5 : case V5 : case CR5: return 5;
53 case R6 : case X6 : case F6 : case V6 : case CR6: return 6;
54 case R7 : case X7 : case F7 : case V7 : case CR7: return 7;
55 case R8 : case X8 : case F8 : case V8 : return 8;
56 case R9 : case X9 : case F9 : case V9 : return 9;
57 case R10: case X10: case F10: case V10: return 10;
58 case R11: case X11: case F11: case V11: return 11;
59 case R12: case X12: case F12: case V12: return 12;
60 case R13: case X13: case F13: case V13: return 13;
61 case R14: case X14: case F14: case V14: return 14;
62 case R15: case X15: case F15: case V15: return 15;
63 case R16: case X16: case F16: case V16: return 16;
64 case R17: case X17: case F17: case V17: return 17;
65 case R18: case X18: case F18: case V18: return 18;
66 case R19: case X19: case F19: case V19: return 19;
67 case R20: case X20: case F20: case V20: return 20;
68 case R21: case X21: case F21: case V21: return 21;
69 case R22: case X22: case F22: case V22: return 22;
70 case R23: case X23: case F23: case V23: return 23;
71 case R24: case X24: case F24: case V24: return 24;
72 case R25: case X25: case F25: case V25: return 25;
73 case R26: case X26: case F26: case V26: return 26;
74 case R27: case X27: case F27: case V27: return 27;
75 case R28: case X28: case F28: case V28: return 28;
76 case R29: case X29: case F29: case V29: return 29;
77 case R30: case X30: case F30: case V30: return 30;
78 case R31: case X31: case F31: case V31: return 31;
80 cerr << "Unhandled reg in PPCRegisterInfo::getRegisterNumbering!\n";
85 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST,
86 const TargetInstrInfo &tii)
87 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
88 Subtarget(ST), TII(tii) {
89 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
90 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
91 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
92 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
93 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
94 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
95 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
96 ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
99 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8;
100 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8;
101 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8;
102 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX;
103 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32;
107 PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
108 MachineBasicBlock::iterator MI,
109 unsigned SrcReg, int FrameIdx,
110 const TargetRegisterClass *RC) const {
111 if (RC == PPC::GPRCRegisterClass) {
112 if (SrcReg != PPC::LR) {
113 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW))
114 .addReg(SrcReg, false, false, true), FrameIdx);
116 // FIXME: this spills LR immediately to memory in one step. To do this,
117 // we use R11, which we know cannot be used in the prolog/epilog. This is
119 BuildMI(MBB, MI, TII.get(PPC::MFLR), PPC::R11);
120 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW))
121 .addReg(PPC::R11, false, false, true), FrameIdx);
123 } else if (RC == PPC::G8RCRegisterClass) {
124 if (SrcReg != PPC::LR8) {
125 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STD))
126 .addReg(SrcReg, false, false, true), FrameIdx);
128 // FIXME: this spills LR immediately to memory in one step. To do this,
129 // we use R11, which we know cannot be used in the prolog/epilog. This is
131 BuildMI(MBB, MI, TII.get(PPC::MFLR8), PPC::X11);
132 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STD))
133 .addReg(PPC::X11, false, false, true), FrameIdx);
135 } else if (RC == PPC::F8RCRegisterClass) {
136 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STFD))
137 .addReg(SrcReg, false, false, true), FrameIdx);
138 } else if (RC == PPC::F4RCRegisterClass) {
139 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STFS))
140 .addReg(SrcReg, false, false, true), FrameIdx);
141 } else if (RC == PPC::CRRCRegisterClass) {
142 // FIXME: We use R0 here, because it isn't available for RA.
143 // We need to store the CR in the low 4-bits of the saved value. First,
144 // issue a MFCR to save all of the CRBits.
145 BuildMI(MBB, MI, TII.get(PPC::MFCR), PPC::R0);
147 // If the saved register wasn't CR0, shift the bits left so that they are in
149 if (SrcReg != PPC::CR0) {
150 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4;
151 // rlwinm r0, r0, ShiftBits, 0, 31.
152 BuildMI(MBB, MI, TII.get(PPC::RLWINM), PPC::R0)
153 .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31);
156 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW))
157 .addReg(PPC::R0, false, false, true), FrameIdx);
158 } else if (RC == PPC::VRRCRegisterClass) {
159 // We don't have indexed addressing for vector loads. Emit:
163 // FIXME: We use R0 here, because it isn't available for RA.
164 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::ADDI), PPC::R0),
166 BuildMI(MBB, MI, TII.get(PPC::STVX))
167 .addReg(SrcReg, false, false, true).addReg(PPC::R0).addReg(PPC::R0);
169 assert(0 && "Unknown regclass!");
175 PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
176 MachineBasicBlock::iterator MI,
177 unsigned DestReg, int FrameIdx,
178 const TargetRegisterClass *RC) const {
179 if (RC == PPC::GPRCRegisterClass) {
180 if (DestReg != PPC::LR) {
181 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LWZ), DestReg), FrameIdx);
183 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LWZ), PPC::R11),FrameIdx);
184 BuildMI(MBB, MI, TII.get(PPC::MTLR)).addReg(PPC::R11);
186 } else if (RC == PPC::G8RCRegisterClass) {
187 if (DestReg != PPC::LR8) {
188 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LD), DestReg), FrameIdx);
190 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LD), PPC::R11), FrameIdx);
191 BuildMI(MBB, MI, TII.get(PPC::MTLR8)).addReg(PPC::R11);
193 } else if (RC == PPC::F8RCRegisterClass) {
194 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LFD), DestReg), FrameIdx);
195 } else if (RC == PPC::F4RCRegisterClass) {
196 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LFS), DestReg), FrameIdx);
197 } else if (RC == PPC::CRRCRegisterClass) {
198 // FIXME: We use R0 here, because it isn't available for RA.
199 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LWZ), PPC::R0), FrameIdx);
201 // If the reloaded register isn't CR0, shift the bits right so that they are
202 // in the right CR's slot.
203 if (DestReg != PPC::CR0) {
204 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4;
205 // rlwinm r11, r11, 32-ShiftBits, 0, 31.
206 BuildMI(MBB, MI, TII.get(PPC::RLWINM), PPC::R0)
207 .addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31);
210 BuildMI(MBB, MI, TII.get(PPC::MTCRF), DestReg).addReg(PPC::R0);
211 } else if (RC == PPC::VRRCRegisterClass) {
212 // We don't have indexed addressing for vector loads. Emit:
216 // FIXME: We use R0 here, because it isn't available for RA.
217 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::ADDI), PPC::R0),
219 BuildMI(MBB, MI, TII.get(PPC::LVX),DestReg).addReg(PPC::R0).addReg(PPC::R0);
221 assert(0 && "Unknown regclass!");
226 void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
227 MachineBasicBlock::iterator MI,
228 unsigned DestReg, unsigned SrcReg,
229 const TargetRegisterClass *DestRC,
230 const TargetRegisterClass *SrcRC) const {
231 if (DestRC != SrcRC) {
232 cerr << "Not yet supported!";
236 if (DestRC == PPC::GPRCRegisterClass) {
237 BuildMI(MBB, MI, TII.get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg);
238 } else if (DestRC == PPC::G8RCRegisterClass) {
239 BuildMI(MBB, MI, TII.get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg);
240 } else if (DestRC == PPC::F4RCRegisterClass) {
241 BuildMI(MBB, MI, TII.get(PPC::FMRS), DestReg).addReg(SrcReg);
242 } else if (DestRC == PPC::F8RCRegisterClass) {
243 BuildMI(MBB, MI, TII.get(PPC::FMRD), DestReg).addReg(SrcReg);
244 } else if (DestRC == PPC::CRRCRegisterClass) {
245 BuildMI(MBB, MI, TII.get(PPC::MCRF), DestReg).addReg(SrcReg);
246 } else if (DestRC == PPC::VRRCRegisterClass) {
247 BuildMI(MBB, MI, TII.get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg);
249 cerr << "Attempt to copy register that is not GPR or FPR";
254 void PPCRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
255 MachineBasicBlock::iterator I,
257 const MachineInstr *Orig) const {
258 MachineInstr *MI = Orig->clone();
259 MI->getOperand(0).setReg(DestReg);
264 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
265 // 32-bit Darwin calling convention.
266 static const unsigned Macho32_CalleeSavedRegs[] = {
267 PPC::R13, PPC::R14, PPC::R15,
268 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
269 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
270 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
271 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
273 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
274 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
275 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
276 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
279 PPC::CR2, PPC::CR3, PPC::CR4,
280 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
281 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
282 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
287 static const unsigned ELF32_CalleeSavedRegs[] = {
288 PPC::R13, PPC::R14, PPC::R15,
289 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
290 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
291 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
292 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
295 PPC::F10, PPC::F11, PPC::F12, PPC::F13,
296 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
297 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
298 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
299 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
302 PPC::CR2, PPC::CR3, PPC::CR4,
303 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
304 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
305 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
309 // 64-bit Darwin calling convention.
310 static const unsigned Macho64_CalleeSavedRegs[] = {
312 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
313 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
314 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
315 PPC::X28, PPC::X29, PPC::X30, PPC::X31,
317 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
318 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
319 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
320 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
323 PPC::CR2, PPC::CR3, PPC::CR4,
324 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
325 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
326 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
331 if (Subtarget.isMachoABI())
332 return Subtarget.isPPC64() ? Macho64_CalleeSavedRegs :
333 Macho32_CalleeSavedRegs;
336 return ELF32_CalleeSavedRegs;
339 const TargetRegisterClass* const*
340 PPCRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
341 // 32-bit Macho calling convention.
342 static const TargetRegisterClass * const Macho32_CalleeSavedRegClasses[] = {
343 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
344 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
345 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
346 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
347 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
349 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
350 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
351 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
352 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
353 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
355 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
357 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
358 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
359 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
361 &PPC::GPRCRegClass, 0
364 static const TargetRegisterClass * const ELF32_CalleeSavedRegClasses[] = {
365 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
366 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
367 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
368 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
369 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
372 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
373 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
374 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
375 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
376 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
377 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
379 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
381 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
382 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
383 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
385 &PPC::GPRCRegClass, 0
388 // 64-bit Macho calling convention.
389 static const TargetRegisterClass * const Macho64_CalleeSavedRegClasses[] = {
390 &PPC::G8RCRegClass,&PPC::G8RCRegClass,
391 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
392 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
393 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
394 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
396 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
397 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
398 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
399 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
400 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
402 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
404 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
405 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
406 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
408 &PPC::G8RCRegClass, 0
411 if (Subtarget.isMachoABI())
412 return Subtarget.isPPC64() ? Macho64_CalleeSavedRegClasses :
413 Macho32_CalleeSavedRegClasses;
416 return ELF32_CalleeSavedRegClasses;
419 // needsFP - Return true if the specified function should have a dedicated frame
420 // pointer register. This is true if the function has variable sized allocas or
421 // if frame pointer elimination is disabled.
423 static bool needsFP(const MachineFunction &MF) {
424 const MachineFrameInfo *MFI = MF.getFrameInfo();
425 return NoFramePointerElim || MFI->hasVarSizedObjects();
428 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
429 BitVector Reserved(getNumRegs());
430 Reserved.set(PPC::R0);
431 Reserved.set(PPC::R1);
432 Reserved.set(PPC::LR);
433 // In Linux, r2 is reserved for the OS.
434 if (!Subtarget.isDarwin())
435 Reserved.set(PPC::R2);
436 // On PPC64, r13 is the thread pointer. Never allocate this register.
437 // Note that this is overconservative, as it also prevents allocation of
438 // R31 when the FP is not needed.
439 if (Subtarget.isPPC64()) {
440 Reserved.set(PPC::R13);
441 Reserved.set(PPC::R31);
444 Reserved.set(PPC::R31);
448 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
449 /// copy instructions, turning them into load/store instructions.
450 MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI,
452 int FrameIndex) const {
453 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
454 // it takes more than one instruction to store it.
455 unsigned Opc = MI->getOpcode();
457 MachineInstr *NewMI = NULL;
458 if ((Opc == PPC::OR &&
459 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
460 if (OpNum == 0) { // move -> store
461 unsigned InReg = MI->getOperand(1).getReg();
462 NewMI = addFrameReference(BuildMI(TII.get(PPC::STW)).addReg(InReg),
464 } else { // move -> load
465 unsigned OutReg = MI->getOperand(0).getReg();
466 NewMI = addFrameReference(BuildMI(TII.get(PPC::LWZ), OutReg),
469 } else if ((Opc == PPC::OR8 &&
470 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
471 if (OpNum == 0) { // move -> store
472 unsigned InReg = MI->getOperand(1).getReg();
473 NewMI = addFrameReference(BuildMI(TII.get(PPC::STD)).addReg(InReg),
475 } else { // move -> load
476 unsigned OutReg = MI->getOperand(0).getReg();
477 NewMI = addFrameReference(BuildMI(TII.get(PPC::LD), OutReg), FrameIndex);
479 } else if (Opc == PPC::FMRD) {
480 if (OpNum == 0) { // move -> store
481 unsigned InReg = MI->getOperand(1).getReg();
482 NewMI = addFrameReference(BuildMI(TII.get(PPC::STFD)).addReg(InReg),
484 } else { // move -> load
485 unsigned OutReg = MI->getOperand(0).getReg();
486 NewMI = addFrameReference(BuildMI(TII.get(PPC::LFD), OutReg), FrameIndex);
488 } else if (Opc == PPC::FMRS) {
489 if (OpNum == 0) { // move -> store
490 unsigned InReg = MI->getOperand(1).getReg();
491 NewMI = addFrameReference(BuildMI(TII.get(PPC::STFS)).addReg(InReg),
493 } else { // move -> load
494 unsigned OutReg = MI->getOperand(0).getReg();
495 NewMI = addFrameReference(BuildMI(TII.get(PPC::LFS), OutReg), FrameIndex);
500 NewMI->copyKillDeadInfo(MI);
504 //===----------------------------------------------------------------------===//
505 // Stack Frame Processing methods
506 //===----------------------------------------------------------------------===//
508 // hasFP - Return true if the specified function actually has a dedicated frame
509 // pointer register. This is true if the function needs a frame pointer and has
510 // a non-zero stack size.
511 bool PPCRegisterInfo::hasFP(const MachineFunction &MF) const {
512 const MachineFrameInfo *MFI = MF.getFrameInfo();
513 return MFI->getStackSize() && needsFP(MF);
516 /// usesLR - Returns if the link registers (LR) has been used in the function.
518 bool PPCRegisterInfo::usesLR(MachineFunction &MF) const {
519 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
523 void PPCRegisterInfo::
524 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
525 MachineBasicBlock::iterator I) const {
526 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
530 /// LowerDynamicAlloc - Generate the code for allocating an object in the
531 /// current frame. The sequence of code with be in the general form
533 /// addi R0, SP, #frameSize ; get the address of the previous frame
534 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size
535 /// addi Rnew, SP, #maxCalFrameSize ; get the top of the allocation
537 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const {
538 // Get the instruction.
539 MachineInstr &MI = *II;
540 // Get the instruction's basic block.
541 MachineBasicBlock &MBB = *MI.getParent();
542 // Get the basic block's function.
543 MachineFunction &MF = *MBB.getParent();
544 // Get the frame info.
545 MachineFrameInfo *MFI = MF.getFrameInfo();
546 // Determine whether 64-bit pointers are used.
547 bool LP64 = Subtarget.isPPC64();
549 // Get the maximum call stack size.
550 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
551 // Get the total frame size.
552 unsigned FrameSize = MFI->getStackSize();
554 // Get stack alignments.
555 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
556 unsigned MaxAlign = MFI->getMaxAlignment();
557 assert(MaxAlign <= TargetAlign &&
558 "Dynamic alloca with large aligns not supported");
560 // Determine the previous frame's address. If FrameSize can't be
561 // represented as 16 bits or we need special alignment, then we load the
562 // previous frame's address from 0(SP). Why not do an addis of the hi?
563 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
564 // Constructing the constant and adding would take 3 instructions.
565 // Fortunately, a frame greater than 32K is rare.
566 if (MaxAlign < TargetAlign && isInt16(FrameSize)) {
567 BuildMI(MBB, II, TII.get(PPC::ADDI), PPC::R0)
571 BuildMI(MBB, II, TII.get(PPC::LD), PPC::X0)
575 BuildMI(MBB, II, TII.get(PPC::LWZ), PPC::R0)
580 // Grow the stack and update the stack pointer link, then
581 // determine the address of new allocated space.
583 BuildMI(MBB, II, TII.get(PPC::STDUX))
586 .addReg(MI.getOperand(1).getReg());
587 BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
589 .addImm(maxCallFrameSize);
591 BuildMI(MBB, II, TII.get(PPC::STWUX))
594 .addReg(MI.getOperand(1).getReg());
595 BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
597 .addImm(maxCallFrameSize);
600 // Discard the DYNALLOC instruction.
604 void PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
605 int SPAdj, RegScavenger *RS) const {
606 assert(SPAdj == 0 && "Unexpected");
608 // Get the instruction.
609 MachineInstr &MI = *II;
610 // Get the instruction's basic block.
611 MachineBasicBlock &MBB = *MI.getParent();
612 // Get the basic block's function.
613 MachineFunction &MF = *MBB.getParent();
614 // Get the frame info.
615 MachineFrameInfo *MFI = MF.getFrameInfo();
617 // Find out which operand is the frame index.
619 while (!MI.getOperand(i).isFrameIndex()) {
621 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
623 // Take into account whether it's an add or mem instruction
624 unsigned OffIdx = (i == 2) ? 1 : 2;
625 if (MI.getOpcode() == TargetInstrInfo::INLINEASM)
628 // Get the frame index.
629 int FrameIndex = MI.getOperand(i).getFrameIndex();
631 // Get the frame pointer save index. Users of this index are primarily
632 // DYNALLOC instructions.
633 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
634 int FPSI = FI->getFramePointerSaveIndex();
635 // Get the instruction opcode.
636 unsigned OpC = MI.getOpcode();
638 // Special case for dynamic alloca.
639 if (FPSI && FrameIndex == FPSI &&
640 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
641 lowerDynamicAlloc(II);
645 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
646 MI.getOperand(i).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1, false);
648 // Figure out if the offset in the instruction is shifted right two bits. This
649 // is true for instructions like "STD", which the machine implicitly adds two
651 bool isIXAddr = false;
661 // Now add the frame object offset to the offset from r1.
662 int Offset = MFI->getObjectOffset(FrameIndex);
665 Offset += MI.getOperand(OffIdx).getImmedValue();
667 Offset += MI.getOperand(OffIdx).getImmedValue() << 2;
669 // If we're not using a Frame Pointer that has been set to the value of the
670 // SP before having the stack size subtracted from it, then add the stack size
671 // to Offset to get the correct offset.
672 Offset += MFI->getStackSize();
674 if (!isInt16(Offset)) {
675 // Insert a set of r0 with the full offset value before the ld, st, or add
676 BuildMI(MBB, II, TII.get(PPC::LIS), PPC::R0).addImm(Offset >> 16);
677 BuildMI(MBB, II, TII.get(PPC::ORI), PPC::R0).addReg(PPC::R0).addImm(Offset);
679 // convert into indexed form of the instruction
680 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
681 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
682 assert(ImmToIdxMap.count(OpC) &&
683 "No indexed form of load or store available!");
684 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second;
685 MI.setInstrDescriptor(TII.get(NewOpcode));
686 MI.getOperand(1).ChangeToRegister(MI.getOperand(i).getReg(), false);
687 MI.getOperand(2).ChangeToRegister(PPC::R0, false);
690 assert((Offset & 3) == 0 && "Invalid frame offset!");
691 Offset >>= 2; // The actual encoded value has the low two bits zero.
693 MI.getOperand(OffIdx).ChangeToImmediate(Offset);
697 /// VRRegNo - Map from a numbered VR register to its enum value.
699 static const unsigned short VRRegNo[] = {
700 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
701 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
702 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
703 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
706 /// RemoveVRSaveCode - We have found that this function does not need any code
707 /// to manipulate the VRSAVE register, even though it uses vector registers.
708 /// This can happen when the only registers used are known to be live in or out
709 /// of the function. Remove all of the VRSAVE related code from the function.
710 static void RemoveVRSaveCode(MachineInstr *MI) {
711 MachineBasicBlock *Entry = MI->getParent();
712 MachineFunction *MF = Entry->getParent();
714 // We know that the MTVRSAVE instruction immediately follows MI. Remove it.
715 MachineBasicBlock::iterator MBBI = MI;
717 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
718 MBBI->eraseFromParent();
720 bool RemovedAllMTVRSAVEs = true;
721 // See if we can find and remove the MTVRSAVE instruction from all of the
723 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
724 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
725 // If last instruction is a return instruction, add an epilogue
726 if (!I->empty() && TII.isReturn(I->back().getOpcode())) {
727 bool FoundIt = false;
728 for (MBBI = I->end(); MBBI != I->begin(); ) {
730 if (MBBI->getOpcode() == PPC::MTVRSAVE) {
731 MBBI->eraseFromParent(); // remove it.
736 RemovedAllMTVRSAVEs &= FoundIt;
740 // If we found and removed all MTVRSAVE instructions, remove the read of
742 if (RemovedAllMTVRSAVEs) {
744 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
746 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
747 MBBI->eraseFromParent();
750 // Finally, nuke the UPDATE_VRSAVE.
751 MI->eraseFromParent();
754 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
755 // instruction selector. Based on the vector registers that have been used,
756 // transform this into the appropriate ORI instruction.
757 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) {
758 MachineFunction *MF = MI->getParent()->getParent();
760 unsigned UsedRegMask = 0;
761 for (unsigned i = 0; i != 32; ++i)
762 if (MF->isPhysRegUsed(VRRegNo[i]))
763 UsedRegMask |= 1 << (31-i);
765 // Live in and live out values already must be in the mask, so don't bother
767 for (MachineFunction::livein_iterator I =
768 MF->livein_begin(), E = MF->livein_end(); I != E; ++I) {
769 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first);
770 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg.
771 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
773 for (MachineFunction::liveout_iterator I =
774 MF->liveout_begin(), E = MF->liveout_end(); I != E; ++I) {
775 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I);
776 if (VRRegNo[RegNo] == *I) // If this really is a vector reg.
777 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
780 unsigned SrcReg = MI->getOperand(1).getReg();
781 unsigned DstReg = MI->getOperand(0).getReg();
782 // If no registers are used, turn this into a copy.
783 if (UsedRegMask == 0) {
784 // Remove all VRSAVE code.
785 RemoveVRSaveCode(MI);
787 } else if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
788 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg)
789 .addReg(SrcReg).addImm(UsedRegMask);
790 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
791 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
792 .addReg(SrcReg).addImm(UsedRegMask >> 16);
794 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
795 .addReg(SrcReg).addImm(UsedRegMask >> 16);
796 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg)
797 .addReg(DstReg).addImm(UsedRegMask & 0xFFFF);
800 // Remove the old UPDATE_VRSAVE instruction.
801 MI->eraseFromParent();
804 /// determineFrameLayout - Determine the size of the frame and maximum call
806 void PPCRegisterInfo::determineFrameLayout(MachineFunction &MF) const {
807 MachineFrameInfo *MFI = MF.getFrameInfo();
809 // Get the number of bytes to allocate from the FrameInfo
810 unsigned FrameSize = MFI->getStackSize();
812 // Get the alignments provided by the target, and the maximum alignment
813 // (if any) of the fixed frame objects.
814 unsigned MaxAlign = MFI->getMaxAlignment();
815 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
816 unsigned AlignMask = TargetAlign - 1; //
818 // If we are a leaf function, and use up to 224 bytes of stack space,
819 // don't have a frame pointer, calls, or dynamic alloca then we do not need
820 // to adjust the stack pointer (we fit in the Red Zone).
821 if (FrameSize <= 224 && // Fits in red zone.
822 !MFI->hasVarSizedObjects() && // No dynamic alloca.
823 !MFI->hasCalls() && // No calls.
824 MaxAlign <= TargetAlign) { // No special alignment.
826 MFI->setStackSize(0);
830 // Get the maximum call frame size of all the calls.
831 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
833 // Maximum call frame needs to be at least big enough for linkage and 8 args.
834 unsigned minCallFrameSize =
835 PPCFrameInfo::getMinCallFrameSize(Subtarget.isPPC64(),
836 Subtarget.isMachoABI());
837 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
839 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
840 // that allocations will be aligned.
841 if (MFI->hasVarSizedObjects())
842 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
844 // Update maximum call frame size.
845 MFI->setMaxCallFrameSize(maxCallFrameSize);
847 // Include call frame size in total.
848 FrameSize += maxCallFrameSize;
850 // Make sure the frame is aligned.
851 FrameSize = (FrameSize + AlignMask) & ~AlignMask;
853 // Update frame info.
854 MFI->setStackSize(FrameSize);
857 void PPCRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
860 // Save and clear the LR state.
861 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
862 unsigned LR = getRARegister();
863 FI->setUsesLR(MF.isPhysRegUsed(LR));
864 MF.setPhysRegUnused(LR);
866 // Save R31 if necessary
867 int FPSI = FI->getFramePointerSaveIndex();
868 bool IsPPC64 = Subtarget.isPPC64();
869 bool IsELF32_ABI = Subtarget.isELF32_ABI();
870 bool IsMachoABI = Subtarget.isMachoABI();
871 const MachineFrameInfo *MFI = MF.getFrameInfo();
873 // If the frame pointer save index hasn't been defined yet.
874 if (!FPSI && (NoFramePointerElim || MFI->hasVarSizedObjects())
876 // Find out what the fix offset of the frame pointer save area.
877 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64,
879 // Allocate the frame index for frame pointer save area.
880 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset);
882 FI->setFramePointerSaveIndex(FPSI);
887 void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
888 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
889 MachineBasicBlock::iterator MBBI = MBB.begin();
890 MachineFrameInfo *MFI = MF.getFrameInfo();
891 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
893 // Prepare for frame info.
894 unsigned FrameLabelId = 0;
896 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
898 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
899 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
900 HandleVRSaveUpdate(MBBI, TII);
905 // Move MBBI back to the beginning of the function.
908 // Work out frame sizes.
909 determineFrameLayout(MF);
910 unsigned FrameSize = MFI->getStackSize();
912 int NegFrameSize = -FrameSize;
914 // Get processor type.
915 bool IsPPC64 = Subtarget.isPPC64();
916 // Get operating system
917 bool IsMachoABI = Subtarget.isMachoABI();
918 // Check if the link register (LR) has been used.
919 bool UsesLR = MFI->hasCalls() || usesLR(MF);
920 // Do we have a frame pointer for this function?
921 bool HasFP = hasFP(MF) && FrameSize;
923 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI);
924 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI);
928 BuildMI(MBB, MBBI, TII.get(PPC::MFLR8), PPC::X0);
931 BuildMI(MBB, MBBI, TII.get(PPC::STD))
932 .addReg(PPC::X31).addImm(FPOffset/4).addReg(PPC::X1);
935 BuildMI(MBB, MBBI, TII.get(PPC::STD))
936 .addReg(PPC::X0).addImm(LROffset/4).addReg(PPC::X1);
939 BuildMI(MBB, MBBI, TII.get(PPC::MFLR), PPC::R0);
942 BuildMI(MBB, MBBI, TII.get(PPC::STW))
943 .addReg(PPC::R31).addImm(FPOffset).addReg(PPC::R1);
946 BuildMI(MBB, MBBI, TII.get(PPC::STW))
947 .addReg(PPC::R0).addImm(LROffset).addReg(PPC::R1);
950 // Skip if a leaf routine.
951 if (!FrameSize) return;
953 // Get stack alignments.
954 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
955 unsigned MaxAlign = MFI->getMaxAlignment();
957 if (MMI && MMI->needsFrameInfo()) {
958 // Mark effective beginning of when frame pointer becomes valid.
959 FrameLabelId = MMI->NextLabelID();
960 BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(FrameLabelId);
963 // Adjust stack pointer: r1 += NegFrameSize.
964 // If there is a preferred stack alignment, align R1 now
967 if (MaxAlign > TargetAlign) {
968 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!");
969 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!");
970 BuildMI(MBB, MBBI, TII.get(PPC::RLWINM), PPC::R0)
971 .addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31);
972 BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC) ,PPC::R0).addReg(PPC::R0)
973 .addImm(NegFrameSize);
974 BuildMI(MBB, MBBI, TII.get(PPC::STWUX))
975 .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
976 } else if (isInt16(NegFrameSize)) {
977 BuildMI(MBB, MBBI, TII.get(PPC::STWU),
978 PPC::R1).addReg(PPC::R1).addImm(NegFrameSize).addReg(PPC::R1);
980 BuildMI(MBB, MBBI, TII.get(PPC::LIS), PPC::R0).addImm(NegFrameSize >> 16);
981 BuildMI(MBB, MBBI, TII.get(PPC::ORI), PPC::R0).addReg(PPC::R0)
982 .addImm(NegFrameSize & 0xFFFF);
983 BuildMI(MBB, MBBI, TII.get(PPC::STWUX)).addReg(PPC::R1).addReg(PPC::R1)
987 if (MaxAlign > TargetAlign) {
988 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!");
989 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!");
990 BuildMI(MBB, MBBI, TII.get(PPC::RLDICL), PPC::X0)
991 .addReg(PPC::X1).addImm(0).addImm(64-Log2_32(MaxAlign));
992 BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC8), PPC::X0).addReg(PPC::X0)
993 .addImm(NegFrameSize);
994 BuildMI(MBB, MBBI, TII.get(PPC::STDUX))
995 .addReg(PPC::X1).addReg(PPC::X1).addReg(PPC::X0);
996 } else if (isInt16(NegFrameSize)) {
997 BuildMI(MBB, MBBI, TII.get(PPC::STDU), PPC::X1)
998 .addReg(PPC::X1).addImm(NegFrameSize/4).addReg(PPC::X1);
1000 BuildMI(MBB, MBBI, TII.get(PPC::LIS8), PPC::X0).addImm(NegFrameSize >>16);
1001 BuildMI(MBB, MBBI, TII.get(PPC::ORI8), PPC::X0).addReg(PPC::X0)
1002 .addImm(NegFrameSize & 0xFFFF);
1003 BuildMI(MBB, MBBI, TII.get(PPC::STDUX)).addReg(PPC::X1).addReg(PPC::X1)
1008 if (MMI && MMI->needsFrameInfo()) {
1009 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
1012 // Show update of SP.
1013 MachineLocation SPDst(MachineLocation::VirtualFP);
1014 MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize);
1015 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
1017 MachineLocation SP(IsPPC64 ? PPC::X31 : PPC::R31);
1018 Moves.push_back(MachineMove(FrameLabelId, SP, SP));
1022 MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset);
1023 MachineLocation FPSrc(IsPPC64 ? PPC::X31 : PPC::R31);
1024 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc));
1027 // Add callee saved registers to move list.
1028 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1029 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
1030 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
1031 unsigned Reg = CSI[I].getReg();
1032 if (Reg == PPC::LR || Reg == PPC::LR8) continue;
1033 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
1034 MachineLocation CSSrc(Reg);
1035 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
1038 MachineLocation LRDst(MachineLocation::VirtualFP, LROffset);
1039 MachineLocation LRSrc(IsPPC64 ? PPC::LR8 : PPC::LR);
1040 Moves.push_back(MachineMove(FrameLabelId, LRDst, LRSrc));
1042 // Mark effective beginning of when frame pointer is ready.
1043 unsigned ReadyLabelId = MMI->NextLabelID();
1044 BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(ReadyLabelId);
1046 MachineLocation FPDst(HasFP ? (IsPPC64 ? PPC::X31 : PPC::R31) :
1047 (IsPPC64 ? PPC::X1 : PPC::R1));
1048 MachineLocation FPSrc(MachineLocation::VirtualFP);
1049 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
1052 // If there is a frame pointer, copy R1 into R31
1055 BuildMI(MBB, MBBI, TII.get(PPC::OR), PPC::R31).addReg(PPC::R1)
1058 BuildMI(MBB, MBBI, TII.get(PPC::OR8), PPC::X31).addReg(PPC::X1)
1064 void PPCRegisterInfo::emitEpilogue(MachineFunction &MF,
1065 MachineBasicBlock &MBB) const {
1066 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1067 assert(MBBI->getOpcode() == PPC::BLR &&
1068 "Can only insert epilog into returning blocks");
1070 // Get alignment info so we know how to restore r1
1071 const MachineFrameInfo *MFI = MF.getFrameInfo();
1072 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
1073 unsigned MaxAlign = MFI->getMaxAlignment();
1075 // Get the number of bytes allocated from the FrameInfo.
1076 unsigned FrameSize = MFI->getStackSize();
1078 // Get processor type.
1079 bool IsPPC64 = Subtarget.isPPC64();
1080 // Get operating system
1081 bool IsMachoABI = Subtarget.isMachoABI();
1082 // Check if the link register (LR) has been used.
1083 bool UsesLR = MFI->hasCalls() || usesLR(MF);
1084 // Do we have a frame pointer for this function?
1085 bool HasFP = hasFP(MF) && FrameSize;
1087 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI);
1088 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI);
1091 // The loaded (or persistent) stack pointer value is offset by the 'stwu'
1092 // on entry to the function. Add this offset back now.
1093 if (!Subtarget.isPPC64()) {
1094 if (isInt16(FrameSize) && TargetAlign >= MaxAlign &&
1095 !MFI->hasVarSizedObjects()) {
1096 BuildMI(MBB, MBBI, TII.get(PPC::ADDI), PPC::R1)
1097 .addReg(PPC::R1).addImm(FrameSize);
1099 BuildMI(MBB, MBBI, TII.get(PPC::LWZ),PPC::R1).addImm(0).addReg(PPC::R1);
1102 if (isInt16(FrameSize) && TargetAlign >= MaxAlign &&
1103 !MFI->hasVarSizedObjects()) {
1104 BuildMI(MBB, MBBI, TII.get(PPC::ADDI8), PPC::X1)
1105 .addReg(PPC::X1).addImm(FrameSize);
1107 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X1).addImm(0).addReg(PPC::X1);
1114 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X0)
1115 .addImm(LROffset/4).addReg(PPC::X1);
1118 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X31)
1119 .addImm(FPOffset/4).addReg(PPC::X1);
1122 BuildMI(MBB, MBBI, TII.get(PPC::MTLR8)).addReg(PPC::X0);
1125 BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R0)
1126 .addImm(LROffset).addReg(PPC::R1);
1129 BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R31)
1130 .addImm(FPOffset).addReg(PPC::R1);
1133 BuildMI(MBB, MBBI, TII.get(PPC::MTLR)).addReg(PPC::R0);
1137 unsigned PPCRegisterInfo::getRARegister() const {
1138 return !Subtarget.isPPC64() ? PPC::LR : PPC::LR8;
1141 unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const {
1142 if (!Subtarget.isPPC64())
1143 return hasFP(MF) ? PPC::R31 : PPC::R1;
1145 return hasFP(MF) ? PPC::X31 : PPC::X1;
1148 void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
1150 // Initial state of the frame pointer is R1.
1151 MachineLocation Dst(MachineLocation::VirtualFP);
1152 MachineLocation Src(PPC::R1, 0);
1153 Moves.push_back(MachineMove(0, Dst, Src));
1156 unsigned PPCRegisterInfo::getEHExceptionRegister() const {
1157 return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3;
1160 unsigned PPCRegisterInfo::getEHHandlerRegister() const {
1161 return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4;
1164 #include "PPCGenRegisterInfo.inc"