1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "reginfo"
16 #include "PPCInstrBuilder.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "PPCRegisterInfo.h"
19 #include "PPCFrameInfo.h"
20 #include "PPCSubtarget.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Type.h"
23 #include "llvm/CodeGen/ValueTypes.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineModuleInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineLocation.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/SelectionDAGNodes.h"
31 #include "llvm/Target/TargetFrameInfo.h"
32 #include "llvm/Target/TargetInstrInfo.h"
33 #include "llvm/Target/TargetMachine.h"
34 #include "llvm/Target/TargetOptions.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/ADT/BitVector.h"
39 #include "llvm/ADT/STLExtras.h"
43 /// getRegisterNumbering - Given the enum value for some register, e.g.
44 /// PPC::F14, return the number that it corresponds to (e.g. 14).
45 unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
48 case R0 : case X0 : case F0 : case V0 : case CR0: return 0;
49 case R1 : case X1 : case F1 : case V1 : case CR1: return 1;
50 case R2 : case X2 : case F2 : case V2 : case CR2: return 2;
51 case R3 : case X3 : case F3 : case V3 : case CR3: return 3;
52 case R4 : case X4 : case F4 : case V4 : case CR4: return 4;
53 case R5 : case X5 : case F5 : case V5 : case CR5: return 5;
54 case R6 : case X6 : case F6 : case V6 : case CR6: return 6;
55 case R7 : case X7 : case F7 : case V7 : case CR7: return 7;
56 case R8 : case X8 : case F8 : case V8 : return 8;
57 case R9 : case X9 : case F9 : case V9 : return 9;
58 case R10: case X10: case F10: case V10: return 10;
59 case R11: case X11: case F11: case V11: return 11;
60 case R12: case X12: case F12: case V12: return 12;
61 case R13: case X13: case F13: case V13: return 13;
62 case R14: case X14: case F14: case V14: return 14;
63 case R15: case X15: case F15: case V15: return 15;
64 case R16: case X16: case F16: case V16: return 16;
65 case R17: case X17: case F17: case V17: return 17;
66 case R18: case X18: case F18: case V18: return 18;
67 case R19: case X19: case F19: case V19: return 19;
68 case R20: case X20: case F20: case V20: return 20;
69 case R21: case X21: case F21: case V21: return 21;
70 case R22: case X22: case F22: case V22: return 22;
71 case R23: case X23: case F23: case V23: return 23;
72 case R24: case X24: case F24: case V24: return 24;
73 case R25: case X25: case F25: case V25: return 25;
74 case R26: case X26: case F26: case V26: return 26;
75 case R27: case X27: case F27: case V27: return 27;
76 case R28: case X28: case F28: case V28: return 28;
77 case R29: case X29: case F29: case V29: return 29;
78 case R30: case X30: case F30: case V30: return 30;
79 case R31: case X31: case F31: case V31: return 31;
81 cerr << "Unhandled reg in PPCRegisterInfo::getRegisterNumbering!\n";
86 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST,
87 const TargetInstrInfo &tii)
88 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
89 Subtarget(ST), TII(tii) {
90 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
91 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
92 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
93 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
94 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
95 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
96 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
97 ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
100 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8;
101 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8;
102 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8;
103 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX;
104 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32;
107 void PPCRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
108 MachineBasicBlock::iterator I,
110 const MachineInstr *Orig) const {
111 MachineInstr *MI = Orig->clone();
112 MI->getOperand(0).setReg(DestReg);
117 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
118 // 32-bit Darwin calling convention.
119 static const unsigned Macho32_CalleeSavedRegs[] = {
120 PPC::R13, PPC::R14, PPC::R15,
121 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
122 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
123 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
124 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
126 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
127 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
128 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
129 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
132 PPC::CR2, PPC::CR3, PPC::CR4,
133 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
134 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
135 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
140 static const unsigned ELF32_CalleeSavedRegs[] = {
141 PPC::R13, PPC::R14, PPC::R15,
142 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
143 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
144 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
145 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
148 PPC::F10, PPC::F11, PPC::F12, PPC::F13,
149 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
150 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
151 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
152 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
155 PPC::CR2, PPC::CR3, PPC::CR4,
156 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
157 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
158 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
162 // 64-bit Darwin calling convention.
163 static const unsigned Macho64_CalleeSavedRegs[] = {
165 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
166 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
167 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
168 PPC::X28, PPC::X29, PPC::X30, PPC::X31,
170 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
171 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
172 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
173 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
176 PPC::CR2, PPC::CR3, PPC::CR4,
177 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
178 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
179 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
184 if (Subtarget.isMachoABI())
185 return Subtarget.isPPC64() ? Macho64_CalleeSavedRegs :
186 Macho32_CalleeSavedRegs;
189 return ELF32_CalleeSavedRegs;
192 const TargetRegisterClass* const*
193 PPCRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
194 // 32-bit Macho calling convention.
195 static const TargetRegisterClass * const Macho32_CalleeSavedRegClasses[] = {
196 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
197 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
198 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
199 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
200 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
202 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
203 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
204 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
205 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
206 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
208 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
210 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
211 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
212 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
214 &PPC::GPRCRegClass, 0
217 static const TargetRegisterClass * const ELF32_CalleeSavedRegClasses[] = {
218 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
219 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
220 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
221 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
222 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
225 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
226 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
227 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
228 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
229 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
230 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
232 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
234 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
235 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
236 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
238 &PPC::GPRCRegClass, 0
241 // 64-bit Macho calling convention.
242 static const TargetRegisterClass * const Macho64_CalleeSavedRegClasses[] = {
243 &PPC::G8RCRegClass,&PPC::G8RCRegClass,
244 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
245 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
246 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
247 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
249 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
250 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
251 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
252 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
253 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
255 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
257 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
258 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
259 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
261 &PPC::G8RCRegClass, 0
264 if (Subtarget.isMachoABI())
265 return Subtarget.isPPC64() ? Macho64_CalleeSavedRegClasses :
266 Macho32_CalleeSavedRegClasses;
269 return ELF32_CalleeSavedRegClasses;
272 // needsFP - Return true if the specified function should have a dedicated frame
273 // pointer register. This is true if the function has variable sized allocas or
274 // if frame pointer elimination is disabled.
276 static bool needsFP(const MachineFunction &MF) {
277 const MachineFrameInfo *MFI = MF.getFrameInfo();
278 return NoFramePointerElim || MFI->hasVarSizedObjects();
281 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
282 BitVector Reserved(getNumRegs());
283 Reserved.set(PPC::R0);
284 Reserved.set(PPC::R1);
285 Reserved.set(PPC::LR);
286 // In Linux, r2 is reserved for the OS.
287 if (!Subtarget.isDarwin())
288 Reserved.set(PPC::R2);
289 // On PPC64, r13 is the thread pointer. Never allocate this register.
290 // Note that this is overconservative, as it also prevents allocation of
291 // R31 when the FP is not needed.
292 if (Subtarget.isPPC64()) {
293 Reserved.set(PPC::R13);
294 Reserved.set(PPC::R31);
297 Reserved.set(PPC::R31);
301 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
302 /// copy instructions, turning them into load/store instructions.
303 MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI,
304 SmallVectorImpl<unsigned> &Ops,
305 int FrameIndex) const {
306 if (Ops.size() != 1) return NULL;
308 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
309 // it takes more than one instruction to store it.
310 unsigned Opc = MI->getOpcode();
311 unsigned OpNum = Ops[0];
313 MachineInstr *NewMI = NULL;
314 if ((Opc == PPC::OR &&
315 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
316 if (OpNum == 0) { // move -> store
317 unsigned InReg = MI->getOperand(1).getReg();
318 NewMI = addFrameReference(BuildMI(TII.get(PPC::STW)).addReg(InReg),
320 } else { // move -> load
321 unsigned OutReg = MI->getOperand(0).getReg();
322 NewMI = addFrameReference(BuildMI(TII.get(PPC::LWZ), OutReg),
325 } else if ((Opc == PPC::OR8 &&
326 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
327 if (OpNum == 0) { // move -> store
328 unsigned InReg = MI->getOperand(1).getReg();
329 NewMI = addFrameReference(BuildMI(TII.get(PPC::STD)).addReg(InReg),
331 } else { // move -> load
332 unsigned OutReg = MI->getOperand(0).getReg();
333 NewMI = addFrameReference(BuildMI(TII.get(PPC::LD), OutReg), FrameIndex);
335 } else if (Opc == PPC::FMRD) {
336 if (OpNum == 0) { // move -> store
337 unsigned InReg = MI->getOperand(1).getReg();
338 NewMI = addFrameReference(BuildMI(TII.get(PPC::STFD)).addReg(InReg),
340 } else { // move -> load
341 unsigned OutReg = MI->getOperand(0).getReg();
342 NewMI = addFrameReference(BuildMI(TII.get(PPC::LFD), OutReg), FrameIndex);
344 } else if (Opc == PPC::FMRS) {
345 if (OpNum == 0) { // move -> store
346 unsigned InReg = MI->getOperand(1).getReg();
347 NewMI = addFrameReference(BuildMI(TII.get(PPC::STFS)).addReg(InReg),
349 } else { // move -> load
350 unsigned OutReg = MI->getOperand(0).getReg();
351 NewMI = addFrameReference(BuildMI(TII.get(PPC::LFS), OutReg), FrameIndex);
356 NewMI->copyKillDeadInfo(MI);
360 bool PPCRegisterInfo::canFoldMemoryOperand(MachineInstr *MI,
361 SmallVectorImpl<unsigned> &Ops) const {
362 if (Ops.size() != 1) return false;
364 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
365 // it takes more than one instruction to store it.
366 unsigned Opc = MI->getOpcode();
368 if ((Opc == PPC::OR &&
369 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
371 else if ((Opc == PPC::OR8 &&
372 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
374 else if (Opc == PPC::FMRD || Opc == PPC::FMRS)
380 //===----------------------------------------------------------------------===//
381 // Stack Frame Processing methods
382 //===----------------------------------------------------------------------===//
384 // hasFP - Return true if the specified function actually has a dedicated frame
385 // pointer register. This is true if the function needs a frame pointer and has
386 // a non-zero stack size.
387 bool PPCRegisterInfo::hasFP(const MachineFunction &MF) const {
388 const MachineFrameInfo *MFI = MF.getFrameInfo();
389 return MFI->getStackSize() && needsFP(MF);
392 /// MustSaveLR - Return true if this function requires that we save the LR
393 /// register onto the stack in the prolog and restore it in the epilog of the
395 static bool MustSaveLR(const MachineFunction &MF) {
396 const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>();
398 // We need an save/restore of LR if there is any use/def of LR explicitly, or
399 // if there is some use of the LR stack slot (e.g. for builtin_return_address.
400 return MFI->usesLR() || MFI->isLRStoreRequired() ||
401 // FIXME: Anything that has a call should clobber the LR register,
402 // isn't this redundant??
403 MF.getFrameInfo()->hasCalls();
406 void PPCRegisterInfo::
407 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
408 MachineBasicBlock::iterator I) const {
409 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
413 /// LowerDynamicAlloc - Generate the code for allocating an object in the
414 /// current frame. The sequence of code with be in the general form
416 /// addi R0, SP, #frameSize ; get the address of the previous frame
417 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size
418 /// addi Rnew, SP, #maxCalFrameSize ; get the top of the allocation
420 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const {
421 // Get the instruction.
422 MachineInstr &MI = *II;
423 // Get the instruction's basic block.
424 MachineBasicBlock &MBB = *MI.getParent();
425 // Get the basic block's function.
426 MachineFunction &MF = *MBB.getParent();
427 // Get the frame info.
428 MachineFrameInfo *MFI = MF.getFrameInfo();
429 // Determine whether 64-bit pointers are used.
430 bool LP64 = Subtarget.isPPC64();
432 // Get the maximum call stack size.
433 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
434 // Get the total frame size.
435 unsigned FrameSize = MFI->getStackSize();
437 // Get stack alignments.
438 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
439 unsigned MaxAlign = MFI->getMaxAlignment();
440 assert(MaxAlign <= TargetAlign &&
441 "Dynamic alloca with large aligns not supported");
443 // Determine the previous frame's address. If FrameSize can't be
444 // represented as 16 bits or we need special alignment, then we load the
445 // previous frame's address from 0(SP). Why not do an addis of the hi?
446 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
447 // Constructing the constant and adding would take 3 instructions.
448 // Fortunately, a frame greater than 32K is rare.
449 if (MaxAlign < TargetAlign && isInt16(FrameSize)) {
450 BuildMI(MBB, II, TII.get(PPC::ADDI), PPC::R0)
454 BuildMI(MBB, II, TII.get(PPC::LD), PPC::X0)
458 BuildMI(MBB, II, TII.get(PPC::LWZ), PPC::R0)
463 // Grow the stack and update the stack pointer link, then
464 // determine the address of new allocated space.
466 BuildMI(MBB, II, TII.get(PPC::STDUX))
469 .addReg(MI.getOperand(1).getReg());
470 BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
472 .addImm(maxCallFrameSize);
474 BuildMI(MBB, II, TII.get(PPC::STWUX))
477 .addReg(MI.getOperand(1).getReg());
478 BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
480 .addImm(maxCallFrameSize);
483 // Discard the DYNALLOC instruction.
487 void PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
488 int SPAdj, RegScavenger *RS) const {
489 assert(SPAdj == 0 && "Unexpected");
491 // Get the instruction.
492 MachineInstr &MI = *II;
493 // Get the instruction's basic block.
494 MachineBasicBlock &MBB = *MI.getParent();
495 // Get the basic block's function.
496 MachineFunction &MF = *MBB.getParent();
497 // Get the frame info.
498 MachineFrameInfo *MFI = MF.getFrameInfo();
500 // Find out which operand is the frame index.
501 unsigned FIOperandNo = 0;
502 while (!MI.getOperand(FIOperandNo).isFrameIndex()) {
504 assert(FIOperandNo != MI.getNumOperands() &&
505 "Instr doesn't have FrameIndex operand!");
507 // Take into account whether it's an add or mem instruction
508 unsigned OffsetOperandNo = (FIOperandNo == 2) ? 1 : 2;
509 if (MI.getOpcode() == TargetInstrInfo::INLINEASM)
510 OffsetOperandNo = FIOperandNo-1;
512 // Get the frame index.
513 int FrameIndex = MI.getOperand(FIOperandNo).getIndex();
515 // Get the frame pointer save index. Users of this index are primarily
516 // DYNALLOC instructions.
517 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
518 int FPSI = FI->getFramePointerSaveIndex();
519 // Get the instruction opcode.
520 unsigned OpC = MI.getOpcode();
522 // Special case for dynamic alloca.
523 if (FPSI && FrameIndex == FPSI &&
524 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
525 lowerDynamicAlloc(II);
529 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
530 MI.getOperand(FIOperandNo).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1,
533 // Figure out if the offset in the instruction is shifted right two bits. This
534 // is true for instructions like "STD", which the machine implicitly adds two
536 bool isIXAddr = false;
546 // Now add the frame object offset to the offset from r1.
547 int Offset = MFI->getObjectOffset(FrameIndex);
549 Offset += MI.getOperand(OffsetOperandNo).getImm();
551 Offset += MI.getOperand(OffsetOperandNo).getImm() << 2;
553 // If we're not using a Frame Pointer that has been set to the value of the
554 // SP before having the stack size subtracted from it, then add the stack size
555 // to Offset to get the correct offset.
556 Offset += MFI->getStackSize();
558 // If we can, encode the offset directly into the instruction. If this is a
559 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If
560 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits
561 // clear can be encoded. This is extremely uncommon, because normally you
562 // only "std" to a stack slot that is at least 4-byte aligned, but it can
563 // happen in invalid code.
564 if (isInt16(Offset) && (!isIXAddr || (Offset & 3) == 0)) {
566 Offset >>= 2; // The actual encoded value has the low two bits zero.
567 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
571 // Insert a set of r0 with the full offset value before the ld, st, or add
572 BuildMI(MBB, II, TII.get(PPC::LIS), PPC::R0).addImm(Offset >> 16);
573 BuildMI(MBB, II, TII.get(PPC::ORI), PPC::R0).addReg(PPC::R0).addImm(Offset);
575 // Convert into indexed form of the instruction
576 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
577 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
578 unsigned OperandBase;
579 if (OpC != TargetInstrInfo::INLINEASM) {
580 assert(ImmToIdxMap.count(OpC) &&
581 "No indexed form of load or store available!");
582 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second;
583 MI.setInstrDescriptor(TII.get(NewOpcode));
586 OperandBase = OffsetOperandNo;
589 unsigned StackReg = MI.getOperand(FIOperandNo).getReg();
590 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false);
591 MI.getOperand(OperandBase+1).ChangeToRegister(PPC::R0, false);
594 /// VRRegNo - Map from a numbered VR register to its enum value.
596 static const unsigned short VRRegNo[] = {
597 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
598 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
599 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
600 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
603 /// RemoveVRSaveCode - We have found that this function does not need any code
604 /// to manipulate the VRSAVE register, even though it uses vector registers.
605 /// This can happen when the only registers used are known to be live in or out
606 /// of the function. Remove all of the VRSAVE related code from the function.
607 static void RemoveVRSaveCode(MachineInstr *MI) {
608 MachineBasicBlock *Entry = MI->getParent();
609 MachineFunction *MF = Entry->getParent();
611 // We know that the MTVRSAVE instruction immediately follows MI. Remove it.
612 MachineBasicBlock::iterator MBBI = MI;
614 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
615 MBBI->eraseFromParent();
617 bool RemovedAllMTVRSAVEs = true;
618 // See if we can find and remove the MTVRSAVE instruction from all of the
620 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
621 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
622 // If last instruction is a return instruction, add an epilogue
623 if (!I->empty() && TII.isReturn(I->back().getOpcode())) {
624 bool FoundIt = false;
625 for (MBBI = I->end(); MBBI != I->begin(); ) {
627 if (MBBI->getOpcode() == PPC::MTVRSAVE) {
628 MBBI->eraseFromParent(); // remove it.
633 RemovedAllMTVRSAVEs &= FoundIt;
637 // If we found and removed all MTVRSAVE instructions, remove the read of
639 if (RemovedAllMTVRSAVEs) {
641 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
643 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
644 MBBI->eraseFromParent();
647 // Finally, nuke the UPDATE_VRSAVE.
648 MI->eraseFromParent();
651 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
652 // instruction selector. Based on the vector registers that have been used,
653 // transform this into the appropriate ORI instruction.
654 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) {
655 MachineFunction *MF = MI->getParent()->getParent();
657 unsigned UsedRegMask = 0;
658 for (unsigned i = 0; i != 32; ++i)
659 if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i]))
660 UsedRegMask |= 1 << (31-i);
662 // Live in and live out values already must be in the mask, so don't bother
664 for (MachineRegisterInfo::livein_iterator
665 I = MF->getRegInfo().livein_begin(),
666 E = MF->getRegInfo().livein_end(); I != E; ++I) {
667 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first);
668 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg.
669 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
671 for (MachineRegisterInfo::liveout_iterator
672 I = MF->getRegInfo().liveout_begin(),
673 E = MF->getRegInfo().liveout_end(); I != E; ++I) {
674 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I);
675 if (VRRegNo[RegNo] == *I) // If this really is a vector reg.
676 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
679 unsigned SrcReg = MI->getOperand(1).getReg();
680 unsigned DstReg = MI->getOperand(0).getReg();
681 // If no registers are used, turn this into a copy.
682 if (UsedRegMask == 0) {
683 // Remove all VRSAVE code.
684 RemoveVRSaveCode(MI);
686 } else if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
687 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg)
688 .addReg(SrcReg).addImm(UsedRegMask);
689 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
690 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
691 .addReg(SrcReg).addImm(UsedRegMask >> 16);
693 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
694 .addReg(SrcReg).addImm(UsedRegMask >> 16);
695 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg)
696 .addReg(DstReg).addImm(UsedRegMask & 0xFFFF);
699 // Remove the old UPDATE_VRSAVE instruction.
700 MI->eraseFromParent();
703 /// determineFrameLayout - Determine the size of the frame and maximum call
705 void PPCRegisterInfo::determineFrameLayout(MachineFunction &MF) const {
706 MachineFrameInfo *MFI = MF.getFrameInfo();
708 // Get the number of bytes to allocate from the FrameInfo
709 unsigned FrameSize = MFI->getStackSize();
711 // Get the alignments provided by the target, and the maximum alignment
712 // (if any) of the fixed frame objects.
713 unsigned MaxAlign = MFI->getMaxAlignment();
714 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
715 unsigned AlignMask = TargetAlign - 1; //
717 // If we are a leaf function, and use up to 224 bytes of stack space,
718 // don't have a frame pointer, calls, or dynamic alloca then we do not need
719 // to adjust the stack pointer (we fit in the Red Zone).
720 if (FrameSize <= 224 && // Fits in red zone.
721 !MFI->hasVarSizedObjects() && // No dynamic alloca.
722 !MFI->hasCalls() && // No calls.
723 MaxAlign <= TargetAlign) { // No special alignment.
725 MFI->setStackSize(0);
729 // Get the maximum call frame size of all the calls.
730 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
732 // Maximum call frame needs to be at least big enough for linkage and 8 args.
733 unsigned minCallFrameSize =
734 PPCFrameInfo::getMinCallFrameSize(Subtarget.isPPC64(),
735 Subtarget.isMachoABI());
736 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
738 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
739 // that allocations will be aligned.
740 if (MFI->hasVarSizedObjects())
741 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
743 // Update maximum call frame size.
744 MFI->setMaxCallFrameSize(maxCallFrameSize);
746 // Include call frame size in total.
747 FrameSize += maxCallFrameSize;
749 // Make sure the frame is aligned.
750 FrameSize = (FrameSize + AlignMask) & ~AlignMask;
752 // Update frame info.
753 MFI->setStackSize(FrameSize);
756 void PPCRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
759 // Save and clear the LR state.
760 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
761 unsigned LR = getRARegister();
762 FI->setUsesLR(MF.getRegInfo().isPhysRegUsed(LR));
763 MF.getRegInfo().setPhysRegUnused(LR);
765 // Save R31 if necessary
766 int FPSI = FI->getFramePointerSaveIndex();
767 bool IsPPC64 = Subtarget.isPPC64();
768 bool IsELF32_ABI = Subtarget.isELF32_ABI();
769 bool IsMachoABI = Subtarget.isMachoABI();
770 const MachineFrameInfo *MFI = MF.getFrameInfo();
772 // If the frame pointer save index hasn't been defined yet.
773 if (!FPSI && (NoFramePointerElim || MFI->hasVarSizedObjects()) &&
775 // Find out what the fix offset of the frame pointer save area.
776 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64,
778 // Allocate the frame index for frame pointer save area.
779 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset);
781 FI->setFramePointerSaveIndex(FPSI);
786 void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
787 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
788 MachineBasicBlock::iterator MBBI = MBB.begin();
789 MachineFrameInfo *MFI = MF.getFrameInfo();
790 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
792 // Prepare for frame info.
793 unsigned FrameLabelId = 0;
795 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
797 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
798 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
799 HandleVRSaveUpdate(MBBI, TII);
804 // Move MBBI back to the beginning of the function.
807 // Work out frame sizes.
808 determineFrameLayout(MF);
809 unsigned FrameSize = MFI->getStackSize();
811 int NegFrameSize = -FrameSize;
813 // Get processor type.
814 bool IsPPC64 = Subtarget.isPPC64();
815 // Get operating system
816 bool IsMachoABI = Subtarget.isMachoABI();
817 // Check if the link register (LR) has been used.
818 bool UsesLR = MustSaveLR(MF);
819 // Do we have a frame pointer for this function?
820 bool HasFP = hasFP(MF) && FrameSize;
822 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI);
823 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI);
827 BuildMI(MBB, MBBI, TII.get(PPC::MFLR8), PPC::X0);
830 BuildMI(MBB, MBBI, TII.get(PPC::STD))
831 .addReg(PPC::X31).addImm(FPOffset/4).addReg(PPC::X1);
834 BuildMI(MBB, MBBI, TII.get(PPC::STD))
835 .addReg(PPC::X0).addImm(LROffset/4).addReg(PPC::X1);
838 BuildMI(MBB, MBBI, TII.get(PPC::MFLR), PPC::R0);
841 BuildMI(MBB, MBBI, TII.get(PPC::STW))
842 .addReg(PPC::R31).addImm(FPOffset).addReg(PPC::R1);
845 BuildMI(MBB, MBBI, TII.get(PPC::STW))
846 .addReg(PPC::R0).addImm(LROffset).addReg(PPC::R1);
849 // Skip if a leaf routine.
850 if (!FrameSize) return;
852 // Get stack alignments.
853 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
854 unsigned MaxAlign = MFI->getMaxAlignment();
856 if (MMI && MMI->needsFrameInfo()) {
857 // Mark effective beginning of when frame pointer becomes valid.
858 FrameLabelId = MMI->NextLabelID();
859 BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(FrameLabelId);
862 // Adjust stack pointer: r1 += NegFrameSize.
863 // If there is a preferred stack alignment, align R1 now
866 if (MaxAlign > TargetAlign) {
867 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!");
868 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!");
869 BuildMI(MBB, MBBI, TII.get(PPC::RLWINM), PPC::R0)
870 .addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31);
871 BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC) ,PPC::R0).addReg(PPC::R0)
872 .addImm(NegFrameSize);
873 BuildMI(MBB, MBBI, TII.get(PPC::STWUX))
874 .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
875 } else if (isInt16(NegFrameSize)) {
876 BuildMI(MBB, MBBI, TII.get(PPC::STWU),
877 PPC::R1).addReg(PPC::R1).addImm(NegFrameSize).addReg(PPC::R1);
879 BuildMI(MBB, MBBI, TII.get(PPC::LIS), PPC::R0).addImm(NegFrameSize >> 16);
880 BuildMI(MBB, MBBI, TII.get(PPC::ORI), PPC::R0).addReg(PPC::R0)
881 .addImm(NegFrameSize & 0xFFFF);
882 BuildMI(MBB, MBBI, TII.get(PPC::STWUX)).addReg(PPC::R1).addReg(PPC::R1)
886 if (MaxAlign > TargetAlign) {
887 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!");
888 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!");
889 BuildMI(MBB, MBBI, TII.get(PPC::RLDICL), PPC::X0)
890 .addReg(PPC::X1).addImm(0).addImm(64-Log2_32(MaxAlign));
891 BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC8), PPC::X0).addReg(PPC::X0)
892 .addImm(NegFrameSize);
893 BuildMI(MBB, MBBI, TII.get(PPC::STDUX))
894 .addReg(PPC::X1).addReg(PPC::X1).addReg(PPC::X0);
895 } else if (isInt16(NegFrameSize)) {
896 BuildMI(MBB, MBBI, TII.get(PPC::STDU), PPC::X1)
897 .addReg(PPC::X1).addImm(NegFrameSize/4).addReg(PPC::X1);
899 BuildMI(MBB, MBBI, TII.get(PPC::LIS8), PPC::X0).addImm(NegFrameSize >>16);
900 BuildMI(MBB, MBBI, TII.get(PPC::ORI8), PPC::X0).addReg(PPC::X0)
901 .addImm(NegFrameSize & 0xFFFF);
902 BuildMI(MBB, MBBI, TII.get(PPC::STDUX)).addReg(PPC::X1).addReg(PPC::X1)
907 if (MMI && MMI->needsFrameInfo()) {
908 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
911 // Show update of SP.
912 MachineLocation SPDst(MachineLocation::VirtualFP);
913 MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize);
914 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
916 MachineLocation SP(IsPPC64 ? PPC::X31 : PPC::R31);
917 Moves.push_back(MachineMove(FrameLabelId, SP, SP));
921 MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset);
922 MachineLocation FPSrc(IsPPC64 ? PPC::X31 : PPC::R31);
923 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc));
926 // Add callee saved registers to move list.
927 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
928 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
929 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
930 unsigned Reg = CSI[I].getReg();
931 if (Reg == PPC::LR || Reg == PPC::LR8) continue;
932 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
933 MachineLocation CSSrc(Reg);
934 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
937 MachineLocation LRDst(MachineLocation::VirtualFP, LROffset);
938 MachineLocation LRSrc(IsPPC64 ? PPC::LR8 : PPC::LR);
939 Moves.push_back(MachineMove(FrameLabelId, LRDst, LRSrc));
941 // Mark effective beginning of when frame pointer is ready.
942 unsigned ReadyLabelId = MMI->NextLabelID();
943 BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(ReadyLabelId);
945 MachineLocation FPDst(HasFP ? (IsPPC64 ? PPC::X31 : PPC::R31) :
946 (IsPPC64 ? PPC::X1 : PPC::R1));
947 MachineLocation FPSrc(MachineLocation::VirtualFP);
948 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
951 // If there is a frame pointer, copy R1 into R31
954 BuildMI(MBB, MBBI, TII.get(PPC::OR), PPC::R31).addReg(PPC::R1)
957 BuildMI(MBB, MBBI, TII.get(PPC::OR8), PPC::X31).addReg(PPC::X1)
963 void PPCRegisterInfo::emitEpilogue(MachineFunction &MF,
964 MachineBasicBlock &MBB) const {
965 MachineBasicBlock::iterator MBBI = prior(MBB.end());
966 assert(MBBI->getOpcode() == PPC::BLR &&
967 "Can only insert epilog into returning blocks");
969 // Get alignment info so we know how to restore r1
970 const MachineFrameInfo *MFI = MF.getFrameInfo();
971 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
972 unsigned MaxAlign = MFI->getMaxAlignment();
974 // Get the number of bytes allocated from the FrameInfo.
975 unsigned FrameSize = MFI->getStackSize();
977 // Get processor type.
978 bool IsPPC64 = Subtarget.isPPC64();
979 // Get operating system
980 bool IsMachoABI = Subtarget.isMachoABI();
981 // Check if the link register (LR) has been used.
982 bool UsesLR = MustSaveLR(MF);
983 // Do we have a frame pointer for this function?
984 bool HasFP = hasFP(MF) && FrameSize;
986 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI);
987 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI);
990 // The loaded (or persistent) stack pointer value is offset by the 'stwu'
991 // on entry to the function. Add this offset back now.
992 if (!Subtarget.isPPC64()) {
993 if (isInt16(FrameSize) && TargetAlign >= MaxAlign &&
994 !MFI->hasVarSizedObjects()) {
995 BuildMI(MBB, MBBI, TII.get(PPC::ADDI), PPC::R1)
996 .addReg(PPC::R1).addImm(FrameSize);
998 BuildMI(MBB, MBBI, TII.get(PPC::LWZ),PPC::R1).addImm(0).addReg(PPC::R1);
1001 if (isInt16(FrameSize) && TargetAlign >= MaxAlign &&
1002 !MFI->hasVarSizedObjects()) {
1003 BuildMI(MBB, MBBI, TII.get(PPC::ADDI8), PPC::X1)
1004 .addReg(PPC::X1).addImm(FrameSize);
1006 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X1).addImm(0).addReg(PPC::X1);
1013 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X0)
1014 .addImm(LROffset/4).addReg(PPC::X1);
1017 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X31)
1018 .addImm(FPOffset/4).addReg(PPC::X1);
1021 BuildMI(MBB, MBBI, TII.get(PPC::MTLR8)).addReg(PPC::X0);
1024 BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R0)
1025 .addImm(LROffset).addReg(PPC::R1);
1028 BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R31)
1029 .addImm(FPOffset).addReg(PPC::R1);
1032 BuildMI(MBB, MBBI, TII.get(PPC::MTLR)).addReg(PPC::R0);
1036 unsigned PPCRegisterInfo::getRARegister() const {
1037 return !Subtarget.isPPC64() ? PPC::LR : PPC::LR8;
1040 unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const {
1041 if (!Subtarget.isPPC64())
1042 return hasFP(MF) ? PPC::R31 : PPC::R1;
1044 return hasFP(MF) ? PPC::X31 : PPC::X1;
1047 void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
1049 // Initial state of the frame pointer is R1.
1050 MachineLocation Dst(MachineLocation::VirtualFP);
1051 MachineLocation Src(PPC::R1, 0);
1052 Moves.push_back(MachineMove(0, Dst, Src));
1055 unsigned PPCRegisterInfo::getEHExceptionRegister() const {
1056 return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3;
1059 unsigned PPCRegisterInfo::getEHHandlerRegister() const {
1060 return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4;
1063 int PPCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
1064 // FIXME: Most probably dwarf numbers differs for Linux and Darwin
1065 return PPCGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
1068 #include "PPCGenRegisterInfo.inc"