1 //===-- PPCRegisterInfo.h - PowerPC Register Information Impl ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetRegisterInfo
13 //===----------------------------------------------------------------------===//
15 #ifndef POWERPC32_REGISTERINFO_H
16 #define POWERPC32_REGISTERINFO_H
19 #include "llvm/ADT/DenseMap.h"
21 #define GET_REGINFO_HEADER
22 #include "PPCGenRegisterInfo.inc"
26 class TargetInstrInfo;
29 class PPCRegisterInfo : public PPCGenRegisterInfo {
30 DenseMap<unsigned, unsigned> ImmToIdxMap;
31 const PPCSubtarget &Subtarget;
33 PPCRegisterInfo(const PPCSubtarget &SubTarget);
35 /// getPointerRegClass - Return the register class to use to hold pointers.
36 /// This is used for addressing modes.
37 virtual const TargetRegisterClass *
38 getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const;
40 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
41 MachineFunction &MF) const;
43 /// Code Generation virtual methods...
44 const uint16_t *getCalleeSavedRegs(const MachineFunction* MF = 0) const;
45 const uint32_t *getCallPreservedMask(CallingConv::ID CC) const;
46 const uint32_t *getNoPreservedMask() const;
48 BitVector getReservedRegs(const MachineFunction &MF) const;
50 /// We require the register scavenger.
51 bool requiresRegisterScavenging(const MachineFunction &MF) const {
55 bool requiresFrameIndexScavenging(const MachineFunction &MF) const {
59 bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
63 virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const {
67 void lowerDynamicAlloc(MachineBasicBlock::iterator II) const;
68 void lowerCRSpilling(MachineBasicBlock::iterator II,
69 unsigned FrameIndex) const;
70 void lowerCRRestore(MachineBasicBlock::iterator II,
71 unsigned FrameIndex) const;
72 void lowerVRSAVESpilling(MachineBasicBlock::iterator II,
73 unsigned FrameIndex) const;
74 void lowerVRSAVERestore(MachineBasicBlock::iterator II,
75 unsigned FrameIndex) const;
77 bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
79 void eliminateFrameIndex(MachineBasicBlock::iterator II,
80 int SPAdj, unsigned FIOperandNum,
81 RegScavenger *RS = NULL) const;
83 // Support for virtual base registers.
84 bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const;
85 void materializeFrameBaseRegister(MachineBasicBlock *MBB,
86 unsigned BaseReg, int FrameIdx,
87 int64_t Offset) const;
88 void resolveFrameIndex(MachineBasicBlock::iterator I,
89 unsigned BaseReg, int64_t Offset) const;
90 bool isFrameOffsetLegal(const MachineInstr *MI, int64_t Offset) const;
92 // Debug information queries.
93 unsigned getFrameRegister(const MachineFunction &MF) const;
95 // Base pointer (stack realignment) support.
96 unsigned getBaseRegister(const MachineFunction &MF) const;
97 bool hasBasePointer(const MachineFunction &MF) const;
98 bool canRealignStack(const MachineFunction &MF) const;
99 bool needsStackRealignment(const MachineFunction &MF) const;
102 } // end namespace llvm