1 //===-- PPCRegisterInfo.h - PowerPC Register Information Impl ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetRegisterInfo
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_POWERPC_PPCREGISTERINFO_H
16 #define LLVM_LIB_TARGET_POWERPC_PPCREGISTERINFO_H
19 #include "llvm/ADT/DenseMap.h"
21 #define GET_REGINFO_HEADER
22 #include "PPCGenRegisterInfo.inc"
26 class TargetInstrInfo;
29 class PPCRegisterInfo : public PPCGenRegisterInfo {
30 DenseMap<unsigned, unsigned> ImmToIdxMap;
31 const PPCSubtarget &Subtarget;
33 PPCRegisterInfo(const PPCSubtarget &SubTarget);
35 /// getPointerRegClass - Return the register class to use to hold pointers.
36 /// This is used for addressing modes.
37 const TargetRegisterClass *
38 getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override;
40 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
41 MachineFunction &MF) const override;
43 const TargetRegisterClass*
44 getLargestLegalSuperClass(const TargetRegisterClass *RC) const override;
46 /// Code Generation virtual methods...
48 getCalleeSavedRegs(const MachineFunction* MF =nullptr) const override;
49 const uint32_t *getCallPreservedMask(CallingConv::ID CC) const override;
50 const uint32_t *getNoPreservedMask() const;
52 BitVector getReservedRegs(const MachineFunction &MF) const override;
54 /// We require the register scavenger.
55 bool requiresRegisterScavenging(const MachineFunction &MF) const override {
59 bool requiresFrameIndexScavenging(const MachineFunction &MF) const override {
63 bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override {
67 bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override {
71 void lowerDynamicAlloc(MachineBasicBlock::iterator II) const;
72 void lowerCRSpilling(MachineBasicBlock::iterator II,
73 unsigned FrameIndex) const;
74 void lowerCRRestore(MachineBasicBlock::iterator II,
75 unsigned FrameIndex) const;
76 void lowerCRBitSpilling(MachineBasicBlock::iterator II,
77 unsigned FrameIndex) const;
78 void lowerCRBitRestore(MachineBasicBlock::iterator II,
79 unsigned FrameIndex) const;
80 void lowerVRSAVESpilling(MachineBasicBlock::iterator II,
81 unsigned FrameIndex) const;
82 void lowerVRSAVERestore(MachineBasicBlock::iterator II,
83 unsigned FrameIndex) const;
85 bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
86 int &FrameIdx) const override;
87 void eliminateFrameIndex(MachineBasicBlock::iterator II,
88 int SPAdj, unsigned FIOperandNum,
89 RegScavenger *RS = nullptr) const override;
91 // Support for virtual base registers.
92 bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
93 void materializeFrameBaseRegister(MachineBasicBlock *MBB,
94 unsigned BaseReg, int FrameIdx,
95 int64_t Offset) const override;
96 void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
97 int64_t Offset) const override;
98 bool isFrameOffsetLegal(const MachineInstr *MI,
99 int64_t Offset) const override;
101 // Debug information queries.
102 unsigned getFrameRegister(const MachineFunction &MF) const override;
104 // Base pointer (stack realignment) support.
105 unsigned getBaseRegister(const MachineFunction &MF) const;
106 bool hasBasePointer(const MachineFunction &MF) const;
107 bool canRealignStack(const MachineFunction &MF) const;
108 bool needsStackRealignment(const MachineFunction &MF) const override;
111 } // end namespace llvm