1 //===-- PPCRegisterInfo.h - PowerPC Register Information Impl ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetRegisterInfo
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_POWERPC_PPCREGISTERINFO_H
16 #define LLVM_LIB_TARGET_POWERPC_PPCREGISTERINFO_H
19 #include "llvm/ADT/DenseMap.h"
21 #define GET_REGINFO_HEADER
22 #include "PPCGenRegisterInfo.inc"
26 inline static unsigned getCRFromCRBit(unsigned SrcReg) {
28 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
29 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
31 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
32 SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
34 else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT ||
35 SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN)
37 else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
38 SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
40 else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
41 SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
43 else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT ||
44 SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN)
46 else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
47 SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
49 else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
50 SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
53 assert(Reg != 0 && "Invalid CR bit register");
58 class PPCRegisterInfo : public PPCGenRegisterInfo {
59 DenseMap<unsigned, unsigned> ImmToIdxMap;
60 const PPCTargetMachine &TM;
62 PPCRegisterInfo(const PPCTargetMachine &TM);
64 /// getPointerRegClass - Return the register class to use to hold pointers.
65 /// This is used for addressing modes.
66 const TargetRegisterClass *
67 getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override;
69 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
70 MachineFunction &MF) const override;
72 const TargetRegisterClass *
73 getLargestLegalSuperClass(const TargetRegisterClass *RC,
74 const MachineFunction &MF) const override;
76 /// Code Generation virtual methods...
77 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
78 const uint32_t *getCallPreservedMask(const MachineFunction &MF,
79 CallingConv::ID CC) const override;
80 const uint32_t *getNoPreservedMask() const;
82 void adjustStackMapLiveOutMask(uint32_t *Mask) const override;
84 BitVector getReservedRegs(const MachineFunction &MF) const override;
86 /// We require the register scavenger.
87 bool requiresRegisterScavenging(const MachineFunction &MF) const override {
91 bool requiresFrameIndexScavenging(const MachineFunction &MF) const override {
95 bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override {
99 bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override {
103 void lowerDynamicAlloc(MachineBasicBlock::iterator II) const;
104 void lowerCRSpilling(MachineBasicBlock::iterator II,
105 unsigned FrameIndex) const;
106 void lowerCRRestore(MachineBasicBlock::iterator II,
107 unsigned FrameIndex) const;
108 void lowerCRBitSpilling(MachineBasicBlock::iterator II,
109 unsigned FrameIndex) const;
110 void lowerCRBitRestore(MachineBasicBlock::iterator II,
111 unsigned FrameIndex) const;
112 void lowerVRSAVESpilling(MachineBasicBlock::iterator II,
113 unsigned FrameIndex) const;
114 void lowerVRSAVERestore(MachineBasicBlock::iterator II,
115 unsigned FrameIndex) const;
117 bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
118 int &FrameIdx) const override;
119 void eliminateFrameIndex(MachineBasicBlock::iterator II,
120 int SPAdj, unsigned FIOperandNum,
121 RegScavenger *RS = nullptr) const override;
123 // Support for virtual base registers.
124 bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
125 void materializeFrameBaseRegister(MachineBasicBlock *MBB,
126 unsigned BaseReg, int FrameIdx,
127 int64_t Offset) const override;
128 void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
129 int64_t Offset) const override;
130 bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
131 int64_t Offset) const override;
133 // Debug information queries.
134 unsigned getFrameRegister(const MachineFunction &MF) const override;
136 // Base pointer (stack realignment) support.
137 unsigned getBaseRegister(const MachineFunction &MF) const;
138 bool hasBasePointer(const MachineFunction &MF) const;
139 bool canRealignStack(const MachineFunction &MF) const;
140 bool needsStackRealignment(const MachineFunction &MF) const override;
143 } // end namespace llvm