1 //===-- PPCRegisterInfo.h - PowerPC Register Information Impl ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetRegisterInfo
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_POWERPC_PPCREGISTERINFO_H
16 #define LLVM_LIB_TARGET_POWERPC_PPCREGISTERINFO_H
19 #include "llvm/ADT/DenseMap.h"
21 #define GET_REGINFO_HEADER
22 #include "PPCGenRegisterInfo.inc"
26 class TargetInstrInfo;
29 class PPCRegisterInfo : public PPCGenRegisterInfo {
30 DenseMap<unsigned, unsigned> ImmToIdxMap;
31 const PPCSubtarget &Subtarget;
33 PPCRegisterInfo(const PPCSubtarget &SubTarget);
35 /// getPointerRegClass - Return the register class to use to hold pointers.
36 /// This is used for addressing modes.
37 const TargetRegisterClass *
38 getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override;
40 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
41 MachineFunction &MF) const override;
43 const TargetRegisterClass *
44 getLargestLegalSuperClass(const TargetRegisterClass *RC,
45 const MachineFunction &MF) const override;
47 /// Code Generation virtual methods...
49 getCalleeSavedRegs(const MachineFunction* MF =nullptr) const override;
50 const uint32_t *getCallPreservedMask(CallingConv::ID CC) const override;
51 const uint32_t *getNoPreservedMask() const;
53 void adjustStackMapLiveOutMask(uint32_t *Mask) const override;
55 BitVector getReservedRegs(const MachineFunction &MF) const override;
57 /// We require the register scavenger.
58 bool requiresRegisterScavenging(const MachineFunction &MF) const override {
62 bool requiresFrameIndexScavenging(const MachineFunction &MF) const override {
66 bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override {
70 bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override {
74 void lowerDynamicAlloc(MachineBasicBlock::iterator II) const;
75 void lowerCRSpilling(MachineBasicBlock::iterator II,
76 unsigned FrameIndex) const;
77 void lowerCRRestore(MachineBasicBlock::iterator II,
78 unsigned FrameIndex) const;
79 void lowerCRBitSpilling(MachineBasicBlock::iterator II,
80 unsigned FrameIndex) const;
81 void lowerCRBitRestore(MachineBasicBlock::iterator II,
82 unsigned FrameIndex) const;
83 void lowerVRSAVESpilling(MachineBasicBlock::iterator II,
84 unsigned FrameIndex) const;
85 void lowerVRSAVERestore(MachineBasicBlock::iterator II,
86 unsigned FrameIndex) const;
88 bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
89 int &FrameIdx) const override;
90 void eliminateFrameIndex(MachineBasicBlock::iterator II,
91 int SPAdj, unsigned FIOperandNum,
92 RegScavenger *RS = nullptr) const override;
94 // Support for virtual base registers.
95 bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
96 void materializeFrameBaseRegister(MachineBasicBlock *MBB,
97 unsigned BaseReg, int FrameIdx,
98 int64_t Offset) const override;
99 void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
100 int64_t Offset) const override;
101 bool isFrameOffsetLegal(const MachineInstr *MI,
102 int64_t Offset) const override;
104 // Debug information queries.
105 unsigned getFrameRegister(const MachineFunction &MF) const override;
107 // Base pointer (stack realignment) support.
108 unsigned getBaseRegister(const MachineFunction &MF) const;
109 bool hasBasePointer(const MachineFunction &MF) const;
110 bool canRealignStack(const MachineFunction &MF) const;
111 bool needsStackRealignment(const MachineFunction &MF) const override;
114 } // end namespace llvm