1 //===- PowerPCRegisterInfo.td - The PowerPC Register File --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 class PPCReg<string n> : Register<n> {
14 let Namespace = "PPC";
17 // We identify all our registers with a 5-bit ID, for consistency's sake.
19 // GPR - One of the 32 32-bit general-purpose registers
20 class GPR<bits<5> num, string n> : PPCReg<n> {
21 field bits<5> Num = num;
24 // GP8 - One of the 32 64-bit general-purpose registers
25 class GP8<GPR Alias> : PPCReg<Alias.Name> {
26 field bits<5> Num = Alias.Num;
27 let Aliases = [Alias];
30 // SPR - One of the 32-bit special-purpose registers
31 class SPR<bits<10> num, string n> : PPCReg<n> {
32 field bits<10> Num = num;
35 // FPR - One of the 32 64-bit floating-point registers
36 class FPR<bits<5> num, string n> : PPCReg<n> {
37 field bits<5> Num = num;
40 // VR - One of the 32 128-bit vector registers
41 class VR<bits<5> num, string n> : PPCReg<n> {
42 field bits<5> Num = num;
45 // CR - One of the 8 4-bit condition registers
46 class CR<bits<5> num, string n> : PPCReg<n> {
47 field bits<5> Num = num;
50 // General-purpose registers
51 def R0 : GPR< 0, "r0">, DwarfRegNum<0>;
52 def R1 : GPR< 1, "r1">, DwarfRegNum<1>;
53 def R2 : GPR< 2, "r2">, DwarfRegNum<2>;
54 def R3 : GPR< 3, "r3">, DwarfRegNum<3>;
55 def R4 : GPR< 4, "r4">, DwarfRegNum<4>;
56 def R5 : GPR< 5, "r5">, DwarfRegNum<5>;
57 def R6 : GPR< 6, "r6">, DwarfRegNum<6>;
58 def R7 : GPR< 7, "r7">, DwarfRegNum<7>;
59 def R8 : GPR< 8, "r8">, DwarfRegNum<8>;
60 def R9 : GPR< 9, "r9">, DwarfRegNum<9>;
61 def R10 : GPR<10, "r10">, DwarfRegNum<10>;
62 def R11 : GPR<11, "r11">, DwarfRegNum<11>;
63 def R12 : GPR<12, "r12">, DwarfRegNum<12>;
64 def R13 : GPR<13, "r13">, DwarfRegNum<13>;
65 def R14 : GPR<14, "r14">, DwarfRegNum<14>;
66 def R15 : GPR<15, "r15">, DwarfRegNum<15>;
67 def R16 : GPR<16, "r16">, DwarfRegNum<16>;
68 def R17 : GPR<17, "r17">, DwarfRegNum<17>;
69 def R18 : GPR<18, "r18">, DwarfRegNum<18>;
70 def R19 : GPR<19, "r19">, DwarfRegNum<19>;
71 def R20 : GPR<20, "r20">, DwarfRegNum<20>;
72 def R21 : GPR<21, "r21">, DwarfRegNum<21>;
73 def R22 : GPR<22, "r22">, DwarfRegNum<22>;
74 def R23 : GPR<23, "r23">, DwarfRegNum<23>;
75 def R24 : GPR<24, "r24">, DwarfRegNum<24>;
76 def R25 : GPR<25, "r25">, DwarfRegNum<25>;
77 def R26 : GPR<26, "r26">, DwarfRegNum<26>;
78 def R27 : GPR<27, "r27">, DwarfRegNum<27>;
79 def R28 : GPR<28, "r28">, DwarfRegNum<28>;
80 def R29 : GPR<29, "r29">, DwarfRegNum<29>;
81 def R30 : GPR<30, "r30">, DwarfRegNum<30>;
82 def R31 : GPR<31, "r31">, DwarfRegNum<31>;
84 // 64-bit General-purpose registers
85 def X0 : GP8< R0>, DwarfRegNum<0>;
86 def X1 : GP8< R1>, DwarfRegNum<1>;
87 def X2 : GP8< R2>, DwarfRegNum<2>;
88 def X3 : GP8< R3>, DwarfRegNum<3>;
89 def X4 : GP8< R4>, DwarfRegNum<4>;
90 def X5 : GP8< R5>, DwarfRegNum<5>;
91 def X6 : GP8< R6>, DwarfRegNum<6>;
92 def X7 : GP8< R7>, DwarfRegNum<7>;
93 def X8 : GP8< R8>, DwarfRegNum<8>;
94 def X9 : GP8< R9>, DwarfRegNum<9>;
95 def X10 : GP8<R10>, DwarfRegNum<10>;
96 def X11 : GP8<R11>, DwarfRegNum<11>;
97 def X12 : GP8<R12>, DwarfRegNum<12>;
98 def X13 : GP8<R13>, DwarfRegNum<13>;
99 def X14 : GP8<R14>, DwarfRegNum<14>;
100 def X15 : GP8<R15>, DwarfRegNum<15>;
101 def X16 : GP8<R16>, DwarfRegNum<16>;
102 def X17 : GP8<R17>, DwarfRegNum<17>;
103 def X18 : GP8<R18>, DwarfRegNum<18>;
104 def X19 : GP8<R19>, DwarfRegNum<19>;
105 def X20 : GP8<R20>, DwarfRegNum<20>;
106 def X21 : GP8<R21>, DwarfRegNum<21>;
107 def X22 : GP8<R22>, DwarfRegNum<22>;
108 def X23 : GP8<R23>, DwarfRegNum<23>;
109 def X24 : GP8<R24>, DwarfRegNum<24>;
110 def X25 : GP8<R25>, DwarfRegNum<25>;
111 def X26 : GP8<R26>, DwarfRegNum<26>;
112 def X27 : GP8<R27>, DwarfRegNum<27>;
113 def X28 : GP8<R28>, DwarfRegNum<28>;
114 def X29 : GP8<R29>, DwarfRegNum<29>;
115 def X30 : GP8<R30>, DwarfRegNum<30>;
116 def X31 : GP8<R31>, DwarfRegNum<31>;
118 // Floating-point registers
119 def F0 : FPR< 0, "f0">, DwarfRegNum<32>;
120 def F1 : FPR< 1, "f1">, DwarfRegNum<33>;
121 def F2 : FPR< 2, "f2">, DwarfRegNum<34>;
122 def F3 : FPR< 3, "f3">, DwarfRegNum<35>;
123 def F4 : FPR< 4, "f4">, DwarfRegNum<36>;
124 def F5 : FPR< 5, "f5">, DwarfRegNum<37>;
125 def F6 : FPR< 6, "f6">, DwarfRegNum<38>;
126 def F7 : FPR< 7, "f7">, DwarfRegNum<39>;
127 def F8 : FPR< 8, "f8">, DwarfRegNum<40>;
128 def F9 : FPR< 9, "f9">, DwarfRegNum<41>;
129 def F10 : FPR<10, "f10">, DwarfRegNum<42>;
130 def F11 : FPR<11, "f11">, DwarfRegNum<43>;
131 def F12 : FPR<12, "f12">, DwarfRegNum<44>;
132 def F13 : FPR<13, "f13">, DwarfRegNum<45>;
133 def F14 : FPR<14, "f14">, DwarfRegNum<46>;
134 def F15 : FPR<15, "f15">, DwarfRegNum<47>;
135 def F16 : FPR<16, "f16">, DwarfRegNum<48>;
136 def F17 : FPR<17, "f17">, DwarfRegNum<49>;
137 def F18 : FPR<18, "f18">, DwarfRegNum<50>;
138 def F19 : FPR<19, "f19">, DwarfRegNum<51>;
139 def F20 : FPR<20, "f20">, DwarfRegNum<52>;
140 def F21 : FPR<21, "f21">, DwarfRegNum<53>;
141 def F22 : FPR<22, "f22">, DwarfRegNum<54>;
142 def F23 : FPR<23, "f23">, DwarfRegNum<55>;
143 def F24 : FPR<24, "f24">, DwarfRegNum<56>;
144 def F25 : FPR<25, "f25">, DwarfRegNum<57>;
145 def F26 : FPR<26, "f26">, DwarfRegNum<58>;
146 def F27 : FPR<27, "f27">, DwarfRegNum<59>;
147 def F28 : FPR<28, "f28">, DwarfRegNum<60>;
148 def F29 : FPR<29, "f29">, DwarfRegNum<61>;
149 def F30 : FPR<30, "f30">, DwarfRegNum<62>;
150 def F31 : FPR<31, "f31">, DwarfRegNum<63>;
153 def V0 : VR< 0, "v0">, DwarfRegNum<77>;
154 def V1 : VR< 1, "v1">, DwarfRegNum<78>;
155 def V2 : VR< 2, "v2">, DwarfRegNum<79>;
156 def V3 : VR< 3, "v3">, DwarfRegNum<80>;
157 def V4 : VR< 4, "v4">, DwarfRegNum<81>;
158 def V5 : VR< 5, "v5">, DwarfRegNum<82>;
159 def V6 : VR< 6, "v6">, DwarfRegNum<83>;
160 def V7 : VR< 7, "v7">, DwarfRegNum<84>;
161 def V8 : VR< 8, "v8">, DwarfRegNum<85>;
162 def V9 : VR< 9, "v9">, DwarfRegNum<86>;
163 def V10 : VR<10, "v10">, DwarfRegNum<87>;
164 def V11 : VR<11, "v11">, DwarfRegNum<88>;
165 def V12 : VR<12, "v12">, DwarfRegNum<89>;
166 def V13 : VR<13, "v13">, DwarfRegNum<90>;
167 def V14 : VR<14, "v14">, DwarfRegNum<91>;
168 def V15 : VR<15, "v15">, DwarfRegNum<92>;
169 def V16 : VR<16, "v16">, DwarfRegNum<93>;
170 def V17 : VR<17, "v17">, DwarfRegNum<94>;
171 def V18 : VR<18, "v18">, DwarfRegNum<95>;
172 def V19 : VR<19, "v19">, DwarfRegNum<96>;
173 def V20 : VR<20, "v20">, DwarfRegNum<97>;
174 def V21 : VR<21, "v21">, DwarfRegNum<98>;
175 def V22 : VR<22, "v22">, DwarfRegNum<99>;
176 def V23 : VR<23, "v23">, DwarfRegNum<100>;
177 def V24 : VR<24, "v24">, DwarfRegNum<101>;
178 def V25 : VR<25, "v25">, DwarfRegNum<102>;
179 def V26 : VR<26, "v26">, DwarfRegNum<103>;
180 def V27 : VR<27, "v27">, DwarfRegNum<104>;
181 def V28 : VR<28, "v28">, DwarfRegNum<105>;
182 def V29 : VR<29, "v29">, DwarfRegNum<106>;
183 def V30 : VR<30, "v30">, DwarfRegNum<107>;
184 def V31 : VR<31, "v31">, DwarfRegNum<108>;
186 // Condition registers
187 def CR0 : CR<0, "cr0">, DwarfRegNum<68>;
188 def CR1 : CR<1, "cr1">, DwarfRegNum<69>;
189 def CR2 : CR<2, "cr2">, DwarfRegNum<70>;
190 def CR3 : CR<3, "cr3">, DwarfRegNum<71>;
191 def CR4 : CR<4, "cr4">, DwarfRegNum<72>;
192 def CR5 : CR<5, "cr5">, DwarfRegNum<73>;
193 def CR6 : CR<6, "cr6">, DwarfRegNum<74>;
194 def CR7 : CR<7, "cr7">, DwarfRegNum<75>;
197 def LR : SPR<8, "lr">, DwarfRegNum<65>;
198 //let Aliases = [LR] in
199 def LR8 : SPR<8, "lr">, DwarfRegNum<65>;
202 def CTR : SPR<9, "ctr">, DwarfRegNum<66>;
203 def CTR8 : SPR<9, "ctr">, DwarfRegNum<66>;
206 def VRSAVE: SPR<256, "VRsave">, DwarfRegNum<107>;
209 // Allocate volatiles first
210 // then nonvolatiles in reverse order since stmw/lmw save from rN to r31
211 def GPRC : RegisterClass<"PPC", [i32], 32,
212 [R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12,
213 R30, R29, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17,
214 R16, R15, R14, R13, R31, R0, R1, LR]>
216 let MethodProtos = [{
217 iterator allocation_order_begin(const MachineFunction &MF) const;
218 iterator allocation_order_end(const MachineFunction &MF) const;
220 let MethodBodies = [{
222 GPRCClass::allocation_order_begin(const MachineFunction &MF) const {
226 GPRCClass::allocation_order_end(const MachineFunction &MF) const {
228 return end()-4; // don't allocate R31, R0, R1, LR
230 return end()-3; // don't allocate R0, R1, LR
234 def G8RC : RegisterClass<"PPC", [i64], 64,
235 [X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12,
236 X30, X29, X28, X27, X26, X25, X24, X23, X22, X21, X20, X19, X18, X17,
237 X16, X15, X14, X13, X31, X0, X1, LR8]>
239 let MethodProtos = [{
240 iterator allocation_order_begin(const MachineFunction &MF) const;
241 iterator allocation_order_end(const MachineFunction &MF) const;
243 let MethodBodies = [{
245 G8RCClass::allocation_order_begin(const MachineFunction &MF) const {
249 G8RCClass::allocation_order_end(const MachineFunction &MF) const {
260 def F8RC : RegisterClass<"PPC", [f64], 64, [F0, F1, F2, F3, F4, F5, F6, F7,
261 F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21,
262 F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
263 def F4RC : RegisterClass<"PPC", [f32], 32, [F0, F1, F2, F3, F4, F5, F6, F7,
264 F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21,
265 F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
267 def VRRC : RegisterClass<"PPC", [v16i8,v8i16,v4i32,v4f32], 128,
268 [V2, V3, V4, V5, V0, V1,
269 V6, V7, V8, V9, V10, V11, V12, V13, V14, V15, V16, V17, V18, V19, V20, V21,
270 V22, V23, V24, V25, V26, V27, V28, V29, V30, V31]>;
272 def CRRC : RegisterClass<"PPC", [i32], 32, [CR0, CR1, CR5, CR6, CR7, CR2,