1 //===-- PPCRegisterInfo.td - The PowerPC Register File -----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 let Namespace = "PPC" in {
14 def sub_lt : SubRegIndex<1>;
15 def sub_gt : SubRegIndex<1, 1>;
16 def sub_eq : SubRegIndex<1, 2>;
17 def sub_un : SubRegIndex<1, 3>;
18 def sub_32 : SubRegIndex<32>;
19 def sub_64 : SubRegIndex<64>;
20 def sub_128 : SubRegIndex<128>;
24 class PPCReg<string n> : Register<n> {
25 let Namespace = "PPC";
28 // We identify all our registers with a 5-bit ID, for consistency's sake.
30 // GPR - One of the 32 32-bit general-purpose registers
31 class GPR<bits<5> num, string n> : PPCReg<n> {
32 let HWEncoding{4-0} = num;
35 // GP8 - One of the 32 64-bit general-purpose registers
36 class GP8<GPR SubReg, string n> : PPCReg<n> {
37 let HWEncoding = SubReg.HWEncoding;
38 let SubRegs = [SubReg];
39 let SubRegIndices = [sub_32];
42 // SPR - One of the 32-bit special-purpose registers
43 class SPR<bits<10> num, string n> : PPCReg<n> {
44 let HWEncoding{9-0} = num;
47 // FPR - One of the 32 64-bit floating-point registers
48 class FPR<bits<5> num, string n> : PPCReg<n> {
49 let HWEncoding{4-0} = num;
52 // QFPR - One of the 32 256-bit floating-point vector registers (used for QPX)
53 class QFPR<FPR SubReg, string n> : PPCReg<n> {
54 let HWEncoding = SubReg.HWEncoding;
55 let SubRegs = [SubReg];
56 let SubRegIndices = [sub_64];
59 // VF - One of the 32 64-bit floating-point subregisters of the vector
60 // registers (used by VSX).
61 class VF<bits<5> num, string n> : PPCReg<n> {
62 let HWEncoding{4-0} = num;
63 let HWEncoding{5} = 1;
66 // VR - One of the 32 128-bit vector registers
67 class VR<VF SubReg, string n> : PPCReg<n> {
68 let HWEncoding{4-0} = SubReg.HWEncoding{4-0};
69 let HWEncoding{5} = 0;
70 let SubRegs = [SubReg];
71 let SubRegIndices = [sub_64];
74 // VSRL - One of the 32 128-bit VSX registers that overlap with the scalar
75 // floating-point registers.
76 class VSRL<FPR SubReg, string n> : PPCReg<n> {
77 let HWEncoding = SubReg.HWEncoding;
78 let SubRegs = [SubReg];
79 let SubRegIndices = [sub_64];
82 // VSRH - One of the 32 128-bit VSX registers that overlap with the vector
84 class VSRH<VR SubReg, string n> : PPCReg<n> {
85 let HWEncoding{4-0} = SubReg.HWEncoding{4-0};
86 let HWEncoding{5} = 1;
87 let SubRegs = [SubReg];
88 let SubRegIndices = [sub_128];
91 // CR - One of the 8 4-bit condition registers
92 class CR<bits<3> num, string n, list<Register> subregs> : PPCReg<n> {
93 let HWEncoding{2-0} = num;
94 let SubRegs = subregs;
97 // CRBIT - One of the 32 1-bit condition register fields
98 class CRBIT<bits<5> num, string n> : PPCReg<n> {
99 let HWEncoding{4-0} = num;
102 // General-purpose registers
103 foreach Index = 0-31 in {
104 def R#Index : GPR<Index, "r"#Index>, DwarfRegNum<[-2, Index]>;
107 // 64-bit General-purpose registers
108 foreach Index = 0-31 in {
109 def X#Index : GP8<!cast<GPR>("R"#Index), "r"#Index>,
110 DwarfRegNum<[Index, -2]>;
113 // Floating-point registers
114 foreach Index = 0-31 in {
115 def F#Index : FPR<Index, "f"#Index>,
116 DwarfRegNum<[!add(Index, 32), !add(Index, 32)]>;
119 // Floating-point vector subregisters (for VSX)
120 foreach Index = 0-31 in {
121 def VF#Index : VF<Index, "vs" # !add(Index, 32)>;
124 // QPX Floating-point registers
125 foreach Index = 0-31 in {
126 def QF#Index : QFPR<!cast<FPR>("F"#Index), "q"#Index>,
127 DwarfRegNum<[!add(Index, 32), !add(Index, 32)]>;
131 foreach Index = 0-31 in {
132 def V#Index : VR<!cast<VF>("VF"#Index), "v"#Index>,
133 DwarfRegNum<[!add(Index, 77), !add(Index, 77)]>;
137 foreach Index = 0-31 in {
138 def VSL#Index : VSRL<!cast<FPR>("F"#Index), "vs"#Index>,
139 DwarfRegAlias<!cast<FPR>("F"#Index)>;
141 foreach Index = 0-31 in {
142 def VSH#Index : VSRH<!cast<VR>("V"#Index), "vs" # !add(Index, 32)>,
143 DwarfRegAlias<!cast<VR>("V"#Index)>;
146 // The reprsentation of r0 when treated as the constant 0.
147 def ZERO : GPR<0, "0">, DwarfRegAlias<R0>;
148 def ZERO8 : GP8<ZERO, "0">, DwarfRegAlias<X0>;
150 // Representations of the frame pointer used by ISD::FRAMEADDR.
151 def FP : GPR<0 /* arbitrary */, "**FRAME POINTER**">;
152 def FP8 : GP8<FP, "**FRAME POINTER**">;
154 // Representations of the base pointer used by setjmp.
155 def BP : GPR<0 /* arbitrary */, "**BASE POINTER**">;
156 def BP8 : GP8<BP, "**BASE POINTER**">;
158 // Condition register bits
159 def CR0LT : CRBIT< 0, "0">;
160 def CR0GT : CRBIT< 1, "1">;
161 def CR0EQ : CRBIT< 2, "2">;
162 def CR0UN : CRBIT< 3, "3">;
163 def CR1LT : CRBIT< 4, "4">;
164 def CR1GT : CRBIT< 5, "5">;
165 def CR1EQ : CRBIT< 6, "6">;
166 def CR1UN : CRBIT< 7, "7">;
167 def CR2LT : CRBIT< 8, "8">;
168 def CR2GT : CRBIT< 9, "9">;
169 def CR2EQ : CRBIT<10, "10">;
170 def CR2UN : CRBIT<11, "11">;
171 def CR3LT : CRBIT<12, "12">;
172 def CR3GT : CRBIT<13, "13">;
173 def CR3EQ : CRBIT<14, "14">;
174 def CR3UN : CRBIT<15, "15">;
175 def CR4LT : CRBIT<16, "16">;
176 def CR4GT : CRBIT<17, "17">;
177 def CR4EQ : CRBIT<18, "18">;
178 def CR4UN : CRBIT<19, "19">;
179 def CR5LT : CRBIT<20, "20">;
180 def CR5GT : CRBIT<21, "21">;
181 def CR5EQ : CRBIT<22, "22">;
182 def CR5UN : CRBIT<23, "23">;
183 def CR6LT : CRBIT<24, "24">;
184 def CR6GT : CRBIT<25, "25">;
185 def CR6EQ : CRBIT<26, "26">;
186 def CR6UN : CRBIT<27, "27">;
187 def CR7LT : CRBIT<28, "28">;
188 def CR7GT : CRBIT<29, "29">;
189 def CR7EQ : CRBIT<30, "30">;
190 def CR7UN : CRBIT<31, "31">;
192 // Condition registers
193 let SubRegIndices = [sub_lt, sub_gt, sub_eq, sub_un] in {
194 def CR0 : CR<0, "cr0", [CR0LT, CR0GT, CR0EQ, CR0UN]>, DwarfRegNum<[68, 68]>;
195 def CR1 : CR<1, "cr1", [CR1LT, CR1GT, CR1EQ, CR1UN]>, DwarfRegNum<[69, 69]>;
196 def CR2 : CR<2, "cr2", [CR2LT, CR2GT, CR2EQ, CR2UN]>, DwarfRegNum<[70, 70]>;
197 def CR3 : CR<3, "cr3", [CR3LT, CR3GT, CR3EQ, CR3UN]>, DwarfRegNum<[71, 71]>;
198 def CR4 : CR<4, "cr4", [CR4LT, CR4GT, CR4EQ, CR4UN]>, DwarfRegNum<[72, 72]>;
199 def CR5 : CR<5, "cr5", [CR5LT, CR5GT, CR5EQ, CR5UN]>, DwarfRegNum<[73, 73]>;
200 def CR6 : CR<6, "cr6", [CR6LT, CR6GT, CR6EQ, CR6UN]>, DwarfRegNum<[74, 74]>;
201 def CR7 : CR<7, "cr7", [CR7LT, CR7GT, CR7EQ, CR7UN]>, DwarfRegNum<[75, 75]>;
205 def LR : SPR<8, "lr">, DwarfRegNum<[-2, 65]>;
206 //let Aliases = [LR] in
207 def LR8 : SPR<8, "lr">, DwarfRegNum<[65, -2]>;
210 def CTR : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>;
211 def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]>;
214 def VRSAVE: SPR<256, "vrsave">, DwarfRegNum<[109]>;
216 // Carry bit. In the architecture this is really bit 0 of the XER register
217 // (which really is SPR register 1); this is the only bit interesting to a
219 def CARRY: SPR<1, "ca">, DwarfRegNum<[76]>;
221 // FP rounding mode: bits 30 and 31 of the FP status and control register
222 // This is not allocated as a normal register; it appears only in
223 // Uses and Defs. The ABI says it needs to be preserved by a function,
224 // but this is not achieved by saving and restoring it as with
225 // most registers, it has to be done in code; to make this work all the
226 // return and call instructions are described as Uses of RM, so instructions
227 // that do nothing but change RM will not get deleted.
228 def RM: PPCReg<"**ROUNDING MODE**">;
231 // Allocate volatiles first
232 // then nonvolatiles in reverse order since stmw/lmw save from rN to r31
233 def GPRC : RegisterClass<"PPC", [i32], 32, (add (sequence "R%u", 2, 12),
234 (sequence "R%u", 30, 13),
235 R31, R0, R1, FP, BP)> {
236 // On non-Darwin PPC64 systems, R2 can be allocated, but must be restored, so
237 // put it at the end of the list.
238 let AltOrders = [(add (sub GPRC, R2), R2)];
239 let AltOrderSelect = [{
240 const PPCSubtarget &S = MF.getSubtarget<PPCSubtarget>();
241 return S.isPPC64() && S.isSVR4ABI();
245 def G8RC : RegisterClass<"PPC", [i64], 64, (add (sequence "X%u", 2, 12),
246 (sequence "X%u", 30, 14),
247 X31, X13, X0, X1, FP8, BP8)> {
248 // On non-Darwin PPC64 systems, R2 can be allocated, but must be restored, so
249 // put it at the end of the list.
250 let AltOrders = [(add (sub G8RC, X2), X2)];
251 let AltOrderSelect = [{
252 const PPCSubtarget &S = MF.getSubtarget<PPCSubtarget>();
253 return S.isPPC64() && S.isSVR4ABI();
257 // For some instructions r0 is special (representing the value 0 instead of
258 // the value in the r0 register), and we use these register subclasses to
259 // prevent r0 from being allocated for use by those instructions.
260 def GPRC_NOR0 : RegisterClass<"PPC", [i32], 32, (add (sub GPRC, R0), ZERO)> {
261 // On non-Darwin PPC64 systems, R2 can be allocated, but must be restored, so
262 // put it at the end of the list.
263 let AltOrders = [(add (sub GPRC_NOR0, R2), R2)];
264 let AltOrderSelect = [{
265 const PPCSubtarget &S = MF.getSubtarget<PPCSubtarget>();
266 return S.isPPC64() && S.isSVR4ABI();
270 def G8RC_NOX0 : RegisterClass<"PPC", [i64], 64, (add (sub G8RC, X0), ZERO8)> {
271 // On non-Darwin PPC64 systems, R2 can be allocated, but must be restored, so
272 // put it at the end of the list.
273 let AltOrders = [(add (sub G8RC_NOX0, X2), X2)];
274 let AltOrderSelect = [{
275 const PPCSubtarget &S = MF.getSubtarget<PPCSubtarget>();
276 return S.isPPC64() && S.isSVR4ABI();
280 // Allocate volatiles first, then non-volatiles in reverse order. With the SVR4
281 // ABI the size of the Floating-point register save area is determined by the
282 // allocated non-volatile register with the lowest register number, as FP
283 // register N is spilled to offset 8 * (32 - N) below the back chain word of the
284 // previous stack frame. By allocating non-volatiles in reverse order we make
285 // sure that the Floating-point register save area is always as small as
286 // possible because there aren't any unused spill slots.
287 def F8RC : RegisterClass<"PPC", [f64], 64, (add (sequence "F%u", 0, 13),
288 (sequence "F%u", 31, 14))>;
289 def F4RC : RegisterClass<"PPC", [f32], 32, (add F8RC)>;
291 def VRRC : RegisterClass<"PPC", [v16i8,v8i16,v4i32,v2i64,v4f32], 128,
292 (add V2, V3, V4, V5, V0, V1, V6, V7, V8, V9, V10, V11,
293 V12, V13, V14, V15, V16, V17, V18, V19, V31, V30,
294 V29, V28, V27, V26, V25, V24, V23, V22, V21, V20)>;
296 // VSX register classes (the allocation order mirrors that of the corresponding
297 // subregister classes).
298 def VSLRC : RegisterClass<"PPC", [v4i32,v4f32,v2f64,v2i64], 128,
299 (add (sequence "VSL%u", 0, 13),
300 (sequence "VSL%u", 31, 14))>;
301 def VSHRC : RegisterClass<"PPC", [v4i32,v4f32,v2f64,v2i64], 128,
302 (add VSH2, VSH3, VSH4, VSH5, VSH0, VSH1, VSH6, VSH7,
303 VSH8, VSH9, VSH10, VSH11, VSH12, VSH13, VSH14,
304 VSH15, VSH16, VSH17, VSH18, VSH19, VSH31, VSH30,
305 VSH29, VSH28, VSH27, VSH26, VSH25, VSH24, VSH23,
306 VSH22, VSH21, VSH20)>;
307 def VSRC : RegisterClass<"PPC", [v4i32,v4f32,v2f64,v2i64], 128,
310 // Register classes for the 64-bit "scalar" VSX subregisters.
311 def VFRC : RegisterClass<"PPC", [f64], 64,
312 (add VF2, VF3, VF4, VF5, VF0, VF1, VF6, VF7,
313 VF8, VF9, VF10, VF11, VF12, VF13, VF14,
314 VF15, VF16, VF17, VF18, VF19, VF31, VF30,
315 VF29, VF28, VF27, VF26, VF25, VF24, VF23,
317 def VSFRC : RegisterClass<"PPC", [f64], 64, (add F8RC, VFRC)>;
320 def QFRC : RegisterClass<"PPC", [v4f64], 256, (add (sequence "QF%u", 0, 13),
321 (sequence "QF%u", 31, 14))>;
322 def QSRC : RegisterClass<"PPC", [v4f32], 128, (add QFRC)>;
323 def QBRC : RegisterClass<"PPC", [v4i1], 256, (add QFRC)> {
324 // These are actually stored as floating-point values where a positive
325 // number is true and anything else (including NaN) is false.
329 def CRBITRC : RegisterClass<"PPC", [i1], 32,
330 (add CR2LT, CR2GT, CR2EQ, CR2UN,
331 CR3LT, CR3GT, CR3EQ, CR3UN,
332 CR4LT, CR4GT, CR4EQ, CR4UN,
333 CR5LT, CR5GT, CR5EQ, CR5UN,
334 CR6LT, CR6GT, CR6EQ, CR6UN,
335 CR7LT, CR7GT, CR7EQ, CR7UN,
336 CR1LT, CR1GT, CR1EQ, CR1UN,
337 CR0LT, CR0GT, CR0EQ, CR0UN)> {
341 def CRRC : RegisterClass<"PPC", [i32], 32, (add CR0, CR1, CR5, CR6,
342 CR7, CR2, CR3, CR4)>;
344 // The CTR registers are not allocatable because they're used by the
345 // decrement-and-branch instructions, and thus need to stay live across
346 // multiple basic blocks.
347 def CTRRC : RegisterClass<"PPC", [i32], 32, (add CTR)> {
348 let isAllocatable = 0;
350 def CTRRC8 : RegisterClass<"PPC", [i64], 64, (add CTR8)> {
351 let isAllocatable = 0;
354 def VRSAVERC : RegisterClass<"PPC", [i32], 32, (add VRSAVE)>;
355 def CARRYRC : RegisterClass<"PPC", [i32], 32, (add CARRY)> {