1 //===- PowerPCRegisterInfo.td - The PowerPC Register File --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 class PPCReg<string n> : Register<n> {
14 let Namespace = "PPC";
17 // We identify all our registers with a 5-bit ID, for consistency's sake.
19 // GPR - One of the 32 32-bit general-purpose registers
20 class GPR<bits<5> num, string n> : PPCReg<n> {
21 field bits<5> Num = num;
24 // SPR - One of the 32-bit special-purpose registers
25 class SPR<bits<5> num, string n> : PPCReg<n> {
26 field bits<5> Num = num;
29 // FPR - One of the 32 64-bit floating-point registers
30 class FPR<bits<5> num, string n> : PPCReg<n> {
31 field bits<5> Num = num;
34 // CR - One of the 8 4-bit condition registers
35 class CR<bits<5> num, string n> : PPCReg<n> {
36 field bits<5> Num = num;
39 // General-purpose registers
40 def R0 : GPR< 0, "R0">; def R1 : GPR< 1, "R1">;
41 def R2 : GPR< 2, "R2">; def R3 : GPR< 3, "R3">;
42 def R4 : GPR< 4, "R4">; def R5 : GPR< 5, "R5">;
43 def R6 : GPR< 6, "R6">; def R7 : GPR< 7, "R7">;
44 def R8 : GPR< 8, "R8">; def R9 : GPR< 9, "R9">;
45 def R10 : GPR<10, "R10">; def R11 : GPR<11, "R11">;
46 def R12 : GPR<12, "R12">; def R13 : GPR<13, "R13">;
47 def R14 : GPR<14, "R14">; def R15 : GPR<15, "R15">;
48 def R16 : GPR<16, "R16">; def R17 : GPR<17, "R17">;
49 def R18 : GPR<18, "R18">; def R19 : GPR<19, "R19">;
50 def R20 : GPR<20, "R20">; def R21 : GPR<21, "R21">;
51 def R22 : GPR<22, "R22">; def R23 : GPR<23, "R23">;
52 def R24 : GPR<24, "R24">; def R25 : GPR<25, "R25">;
53 def R26 : GPR<26, "R26">; def R27 : GPR<27, "R27">;
54 def R28 : GPR<28, "R28">; def R29 : GPR<29, "R29">;
55 def R30 : GPR<30, "R30">; def R31 : GPR<31, "R31">;
57 // Floating-point registers
58 def F0 : FPR< 0, "F0">; def F1 : FPR< 1, "F1">;
59 def F2 : FPR< 2, "F2">; def F3 : FPR< 3, "F3">;
60 def F4 : FPR< 4, "F4">; def F5 : FPR< 5, "F5">;
61 def F6 : FPR< 6, "F6">; def F7 : FPR< 7, "F7">;
62 def F8 : FPR< 8, "F8">; def F9 : FPR< 9, "F9">;
63 def F10 : FPR<10, "F10">; def F11 : FPR<11, "F11">;
64 def F12 : FPR<12, "F12">; def F13 : FPR<13, "F13">;
65 def F14 : FPR<14, "F14">; def F15 : FPR<15, "F15">;
66 def F16 : FPR<16, "F16">; def F17 : FPR<17, "F17">;
67 def F18 : FPR<18, "F18">; def F19 : FPR<19, "F19">;
68 def F20 : FPR<20, "F20">; def F21 : FPR<21, "F21">;
69 def F22 : FPR<22, "F22">; def F23 : FPR<23, "F23">;
70 def F24 : FPR<24, "F24">; def F25 : FPR<25, "F25">;
71 def F26 : FPR<26, "F26">; def F27 : FPR<27, "F27">;
72 def F28 : FPR<28, "F28">; def F29 : FPR<29, "F29">;
73 def F30 : FPR<30, "F30">; def F31 : FPR<31, "F31">;
76 // Condition registers
77 def CR0 : CR<0, "CR0">; def CR1 : CR<1, "CR1">;
78 def CR2 : CR<2, "CR2">; def CR3 : CR<3, "CR3">;
79 def CR4 : CR<4, "CR4">; def CR5 : CR<5, "CR5">;
80 def CR6 : CR<6, "CR6">; def CR7 : CR<7, "CR7">;
82 // Floating-point status and control register
83 def FPSCR : SPR<0, "FPSCR">;
84 // fiXed-point Exception Register? :-)
85 def XER : SPR<1, "XER">;
87 def LR : SPR<2, "LR">;
89 def CTR : SPR<3, "CTR">;
90 // These are the "time base" registers which are read-only in user mode.
91 def TBL : SPR<4, "TBL">;
92 def TBU : SPR<5, "TBU">;