1 //===- PowerPCRegisterInfo.td - The PowerPC Register File --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 class PPCReg<string n> : Register<n> {
14 let Namespace = "PPC";
17 // We identify all our registers with a 5-bit ID, for consistency's sake.
19 // GPR - One of the 32 32-bit general-purpose registers
20 class GPR<bits<5> num, string n> : PPCReg<n> {
21 field bits<5> Num = num;
24 // GP8 - One of the 32 64-bit general-purpose registers
25 class GP8<GPR Alias> : PPCReg<Alias.Name> {
26 field bits<5> Num = Alias.Num;
27 let Aliases = [Alias];
30 // SPR - One of the 32-bit special-purpose registers
31 class SPR<bits<10> num, string n> : PPCReg<n> {
32 field bits<10> Num = num;
35 // FPR - One of the 32 64-bit floating-point registers
36 class FPR<bits<5> num, string n> : PPCReg<n> {
37 field bits<5> Num = num;
40 // VR - One of the 32 128-bit vector registers
41 class VR<bits<5> num, string n> : PPCReg<n> {
42 field bits<5> Num = num;
45 // CR - One of the 8 4-bit condition registers
46 class CR<bits<3> num, string n> : PPCReg<n> {
47 field bits<3> Num = num;
50 // CRBIT - One of the 32 1-bit condition register fields
51 class CRBIT<bits<5> num, string n> : PPCReg<n> {
52 field bits<5> Num = num;
56 // General-purpose registers
57 def R0 : GPR< 0, "r0">, DwarfRegNum<0>;
58 def R1 : GPR< 1, "r1">, DwarfRegNum<1>;
59 def R2 : GPR< 2, "r2">, DwarfRegNum<2>;
60 def R3 : GPR< 3, "r3">, DwarfRegNum<3>;
61 def R4 : GPR< 4, "r4">, DwarfRegNum<4>;
62 def R5 : GPR< 5, "r5">, DwarfRegNum<5>;
63 def R6 : GPR< 6, "r6">, DwarfRegNum<6>;
64 def R7 : GPR< 7, "r7">, DwarfRegNum<7>;
65 def R8 : GPR< 8, "r8">, DwarfRegNum<8>;
66 def R9 : GPR< 9, "r9">, DwarfRegNum<9>;
67 def R10 : GPR<10, "r10">, DwarfRegNum<10>;
68 def R11 : GPR<11, "r11">, DwarfRegNum<11>;
69 def R12 : GPR<12, "r12">, DwarfRegNum<12>;
70 def R13 : GPR<13, "r13">, DwarfRegNum<13>;
71 def R14 : GPR<14, "r14">, DwarfRegNum<14>;
72 def R15 : GPR<15, "r15">, DwarfRegNum<15>;
73 def R16 : GPR<16, "r16">, DwarfRegNum<16>;
74 def R17 : GPR<17, "r17">, DwarfRegNum<17>;
75 def R18 : GPR<18, "r18">, DwarfRegNum<18>;
76 def R19 : GPR<19, "r19">, DwarfRegNum<19>;
77 def R20 : GPR<20, "r20">, DwarfRegNum<20>;
78 def R21 : GPR<21, "r21">, DwarfRegNum<21>;
79 def R22 : GPR<22, "r22">, DwarfRegNum<22>;
80 def R23 : GPR<23, "r23">, DwarfRegNum<23>;
81 def R24 : GPR<24, "r24">, DwarfRegNum<24>;
82 def R25 : GPR<25, "r25">, DwarfRegNum<25>;
83 def R26 : GPR<26, "r26">, DwarfRegNum<26>;
84 def R27 : GPR<27, "r27">, DwarfRegNum<27>;
85 def R28 : GPR<28, "r28">, DwarfRegNum<28>;
86 def R29 : GPR<29, "r29">, DwarfRegNum<29>;
87 def R30 : GPR<30, "r30">, DwarfRegNum<30>;
88 def R31 : GPR<31, "r31">, DwarfRegNum<31>;
90 // 64-bit General-purpose registers
91 def X0 : GP8< R0>, DwarfRegNum<0>;
92 def X1 : GP8< R1>, DwarfRegNum<1>;
93 def X2 : GP8< R2>, DwarfRegNum<2>;
94 def X3 : GP8< R3>, DwarfRegNum<3>;
95 def X4 : GP8< R4>, DwarfRegNum<4>;
96 def X5 : GP8< R5>, DwarfRegNum<5>;
97 def X6 : GP8< R6>, DwarfRegNum<6>;
98 def X7 : GP8< R7>, DwarfRegNum<7>;
99 def X8 : GP8< R8>, DwarfRegNum<8>;
100 def X9 : GP8< R9>, DwarfRegNum<9>;
101 def X10 : GP8<R10>, DwarfRegNum<10>;
102 def X11 : GP8<R11>, DwarfRegNum<11>;
103 def X12 : GP8<R12>, DwarfRegNum<12>;
104 def X13 : GP8<R13>, DwarfRegNum<13>;
105 def X14 : GP8<R14>, DwarfRegNum<14>;
106 def X15 : GP8<R15>, DwarfRegNum<15>;
107 def X16 : GP8<R16>, DwarfRegNum<16>;
108 def X17 : GP8<R17>, DwarfRegNum<17>;
109 def X18 : GP8<R18>, DwarfRegNum<18>;
110 def X19 : GP8<R19>, DwarfRegNum<19>;
111 def X20 : GP8<R20>, DwarfRegNum<20>;
112 def X21 : GP8<R21>, DwarfRegNum<21>;
113 def X22 : GP8<R22>, DwarfRegNum<22>;
114 def X23 : GP8<R23>, DwarfRegNum<23>;
115 def X24 : GP8<R24>, DwarfRegNum<24>;
116 def X25 : GP8<R25>, DwarfRegNum<25>;
117 def X26 : GP8<R26>, DwarfRegNum<26>;
118 def X27 : GP8<R27>, DwarfRegNum<27>;
119 def X28 : GP8<R28>, DwarfRegNum<28>;
120 def X29 : GP8<R29>, DwarfRegNum<29>;
121 def X30 : GP8<R30>, DwarfRegNum<30>;
122 def X31 : GP8<R31>, DwarfRegNum<31>;
124 // Floating-point registers
125 def F0 : FPR< 0, "f0">, DwarfRegNum<32>;
126 def F1 : FPR< 1, "f1">, DwarfRegNum<33>;
127 def F2 : FPR< 2, "f2">, DwarfRegNum<34>;
128 def F3 : FPR< 3, "f3">, DwarfRegNum<35>;
129 def F4 : FPR< 4, "f4">, DwarfRegNum<36>;
130 def F5 : FPR< 5, "f5">, DwarfRegNum<37>;
131 def F6 : FPR< 6, "f6">, DwarfRegNum<38>;
132 def F7 : FPR< 7, "f7">, DwarfRegNum<39>;
133 def F8 : FPR< 8, "f8">, DwarfRegNum<40>;
134 def F9 : FPR< 9, "f9">, DwarfRegNum<41>;
135 def F10 : FPR<10, "f10">, DwarfRegNum<42>;
136 def F11 : FPR<11, "f11">, DwarfRegNum<43>;
137 def F12 : FPR<12, "f12">, DwarfRegNum<44>;
138 def F13 : FPR<13, "f13">, DwarfRegNum<45>;
139 def F14 : FPR<14, "f14">, DwarfRegNum<46>;
140 def F15 : FPR<15, "f15">, DwarfRegNum<47>;
141 def F16 : FPR<16, "f16">, DwarfRegNum<48>;
142 def F17 : FPR<17, "f17">, DwarfRegNum<49>;
143 def F18 : FPR<18, "f18">, DwarfRegNum<50>;
144 def F19 : FPR<19, "f19">, DwarfRegNum<51>;
145 def F20 : FPR<20, "f20">, DwarfRegNum<52>;
146 def F21 : FPR<21, "f21">, DwarfRegNum<53>;
147 def F22 : FPR<22, "f22">, DwarfRegNum<54>;
148 def F23 : FPR<23, "f23">, DwarfRegNum<55>;
149 def F24 : FPR<24, "f24">, DwarfRegNum<56>;
150 def F25 : FPR<25, "f25">, DwarfRegNum<57>;
151 def F26 : FPR<26, "f26">, DwarfRegNum<58>;
152 def F27 : FPR<27, "f27">, DwarfRegNum<59>;
153 def F28 : FPR<28, "f28">, DwarfRegNum<60>;
154 def F29 : FPR<29, "f29">, DwarfRegNum<61>;
155 def F30 : FPR<30, "f30">, DwarfRegNum<62>;
156 def F31 : FPR<31, "f31">, DwarfRegNum<63>;
159 def V0 : VR< 0, "v0">, DwarfRegNum<77>;
160 def V1 : VR< 1, "v1">, DwarfRegNum<78>;
161 def V2 : VR< 2, "v2">, DwarfRegNum<79>;
162 def V3 : VR< 3, "v3">, DwarfRegNum<80>;
163 def V4 : VR< 4, "v4">, DwarfRegNum<81>;
164 def V5 : VR< 5, "v5">, DwarfRegNum<82>;
165 def V6 : VR< 6, "v6">, DwarfRegNum<83>;
166 def V7 : VR< 7, "v7">, DwarfRegNum<84>;
167 def V8 : VR< 8, "v8">, DwarfRegNum<85>;
168 def V9 : VR< 9, "v9">, DwarfRegNum<86>;
169 def V10 : VR<10, "v10">, DwarfRegNum<87>;
170 def V11 : VR<11, "v11">, DwarfRegNum<88>;
171 def V12 : VR<12, "v12">, DwarfRegNum<89>;
172 def V13 : VR<13, "v13">, DwarfRegNum<90>;
173 def V14 : VR<14, "v14">, DwarfRegNum<91>;
174 def V15 : VR<15, "v15">, DwarfRegNum<92>;
175 def V16 : VR<16, "v16">, DwarfRegNum<93>;
176 def V17 : VR<17, "v17">, DwarfRegNum<94>;
177 def V18 : VR<18, "v18">, DwarfRegNum<95>;
178 def V19 : VR<19, "v19">, DwarfRegNum<96>;
179 def V20 : VR<20, "v20">, DwarfRegNum<97>;
180 def V21 : VR<21, "v21">, DwarfRegNum<98>;
181 def V22 : VR<22, "v22">, DwarfRegNum<99>;
182 def V23 : VR<23, "v23">, DwarfRegNum<100>;
183 def V24 : VR<24, "v24">, DwarfRegNum<101>;
184 def V25 : VR<25, "v25">, DwarfRegNum<102>;
185 def V26 : VR<26, "v26">, DwarfRegNum<103>;
186 def V27 : VR<27, "v27">, DwarfRegNum<104>;
187 def V28 : VR<28, "v28">, DwarfRegNum<105>;
188 def V29 : VR<29, "v29">, DwarfRegNum<106>;
189 def V30 : VR<30, "v30">, DwarfRegNum<107>;
190 def V31 : VR<31, "v31">, DwarfRegNum<108>;
192 // Condition registers
193 def CR0 : CR<0, "cr0">, DwarfRegNum<68>;
194 def CR1 : CR<1, "cr1">, DwarfRegNum<69>;
195 def CR2 : CR<2, "cr2">, DwarfRegNum<70>;
196 def CR3 : CR<3, "cr3">, DwarfRegNum<71>;
197 def CR4 : CR<4, "cr4">, DwarfRegNum<72>;
198 def CR5 : CR<5, "cr5">, DwarfRegNum<73>;
199 def CR6 : CR<6, "cr6">, DwarfRegNum<74>;
200 def CR7 : CR<7, "cr7">, DwarfRegNum<75>;
202 // Condition register bits
203 def CR0LT : CRBIT< 0, "0">, DwarfRegNum<0>;
204 def CR0GT : CRBIT< 1, "1">, DwarfRegNum<0>;
205 def CR0EQ : CRBIT< 2, "2">, DwarfRegNum<0>;
206 def CR0UN : CRBIT< 3, "3">, DwarfRegNum<0>;
207 def CR1LT : CRBIT< 4, "4">, DwarfRegNum<0>;
208 def CR1GT : CRBIT< 5, "5">, DwarfRegNum<0>;
209 def CR1EQ : CRBIT< 6, "6">, DwarfRegNum<0>;
210 def CR1UN : CRBIT< 7, "7">, DwarfRegNum<0>;
211 def CR2LT : CRBIT< 8, "8">, DwarfRegNum<0>;
212 def CR2GT : CRBIT< 9, "9">, DwarfRegNum<0>;
213 def CR2EQ : CRBIT<10, "10">, DwarfRegNum<0>;
214 def CR2UN : CRBIT<11, "11">, DwarfRegNum<0>;
215 def CR3LT : CRBIT<12, "12">, DwarfRegNum<0>;
216 def CR3GT : CRBIT<13, "13">, DwarfRegNum<0>;
217 def CR3EQ : CRBIT<14, "14">, DwarfRegNum<0>;
218 def CR3UN : CRBIT<15, "15">, DwarfRegNum<0>;
219 def CR4LT : CRBIT<16, "16">, DwarfRegNum<0>;
220 def CR4GT : CRBIT<17, "17">, DwarfRegNum<0>;
221 def CR4EQ : CRBIT<18, "18">, DwarfRegNum<0>;
222 def CR4UN : CRBIT<19, "19">, DwarfRegNum<0>;
223 def CR5LT : CRBIT<20, "20">, DwarfRegNum<0>;
224 def CR5GT : CRBIT<21, "21">, DwarfRegNum<0>;
225 def CR5EQ : CRBIT<22, "22">, DwarfRegNum<0>;
226 def CR5UN : CRBIT<23, "23">, DwarfRegNum<0>;
227 def CR6LT : CRBIT<24, "24">, DwarfRegNum<0>;
228 def CR6GT : CRBIT<25, "25">, DwarfRegNum<0>;
229 def CR6EQ : CRBIT<26, "26">, DwarfRegNum<0>;
230 def CR6UN : CRBIT<27, "27">, DwarfRegNum<0>;
231 def CR7LT : CRBIT<28, "28">, DwarfRegNum<0>;
232 def CR7GT : CRBIT<29, "29">, DwarfRegNum<0>;
233 def CR7EQ : CRBIT<30, "30">, DwarfRegNum<0>;
234 def CR7UN : CRBIT<31, "31">, DwarfRegNum<0>;
236 def : SubRegSet<1, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7],
237 [CR0LT, CR1LT, CR2LT, CR3LT, CR4LT, CR5LT, CR6LT, CR7LT]>;
238 def : SubRegSet<2, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7],
239 [CR0GT, CR1GT, CR2GT, CR3GT, CR4GT, CR5GT, CR6GT, CR7GT]>;
240 def : SubRegSet<3, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7],
241 [CR0EQ, CR1EQ, CR2EQ, CR3EQ, CR4EQ, CR5EQ, CR6EQ, CR7EQ]>;
242 def : SubRegSet<4, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7],
243 [CR0UN, CR1UN, CR2UN, CR3UN, CR4UN, CR5UN, CR6UN, CR7UN]>;
246 def LR : SPR<8, "lr">, DwarfRegNum<65>;
247 //let Aliases = [LR] in
248 def LR8 : SPR<8, "lr">, DwarfRegNum<65>;
251 def CTR : SPR<9, "ctr">, DwarfRegNum<66>;
252 def CTR8 : SPR<9, "ctr">, DwarfRegNum<66>;
255 def VRSAVE: SPR<256, "VRsave">, DwarfRegNum<107>;
258 // Allocate volatiles first
259 // then nonvolatiles in reverse order since stmw/lmw save from rN to r31
260 def GPRC : RegisterClass<"PPC", [i32], 32,
261 [R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12,
262 R30, R29, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17,
263 R16, R15, R14, R13, R31, R0, R1, LR]>
265 let MethodProtos = [{
266 iterator allocation_order_begin(const MachineFunction &MF) const;
267 iterator allocation_order_end(const MachineFunction &MF) const;
269 let MethodBodies = [{
271 GPRCClass::allocation_order_begin(const MachineFunction &MF) const {
272 // In Linux, r2 is reserved for the OS.
273 if (!MF.getTarget().getSubtarget<PPCSubtarget>().isDarwin())
279 GPRCClass::allocation_order_end(const MachineFunction &MF) const {
280 // On PPC64, r13 is the thread pointer. Never allocate this register.
281 // Note that this is overconservative, as it also prevents allocation of
282 // R31 when the FP is not needed.
283 if (MF.getTarget().getSubtarget<PPCSubtarget>().isPPC64())
284 return end()-5; // don't allocate R13, R31, R0, R1, LR
287 return end()-4; // don't allocate R31, R0, R1, LR
289 return end()-3; // don't allocate R0, R1, LR
293 def G8RC : RegisterClass<"PPC", [i64], 64,
294 [X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12,
295 X30, X29, X28, X27, X26, X25, X24, X23, X22, X21, X20, X19, X18, X17,
296 X16, X15, X14, X31, X13, X0, X1, LR8]>
298 let MethodProtos = [{
299 iterator allocation_order_begin(const MachineFunction &MF) const;
300 iterator allocation_order_end(const MachineFunction &MF) const;
302 let MethodBodies = [{
304 G8RCClass::allocation_order_begin(const MachineFunction &MF) const {
308 G8RCClass::allocation_order_end(const MachineFunction &MF) const {
319 def F8RC : RegisterClass<"PPC", [f64], 64, [F0, F1, F2, F3, F4, F5, F6, F7,
320 F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21,
321 F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
322 def F4RC : RegisterClass<"PPC", [f32], 32, [F0, F1, F2, F3, F4, F5, F6, F7,
323 F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21,
324 F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
326 def VRRC : RegisterClass<"PPC", [v16i8,v8i16,v4i32,v4f32], 128,
327 [V2, V3, V4, V5, V0, V1,
328 V6, V7, V8, V9, V10, V11, V12, V13, V14, V15, V16, V17, V18, V19, V20, V21,
329 V22, V23, V24, V25, V26, V27, V28, V29, V30, V31]>;
331 def CRRC : RegisterClass<"PPC", [i32], 32, [CR0, CR1, CR5, CR6, CR7, CR2,