1 //===-- PPCSchedule.td - PowerPC Scheduling Definitions ----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Functional units across PowerPC chips sets
13 def BPU : FuncUnit; // Branch unit
14 def SLU : FuncUnit; // Store/load unit
15 def SRU : FuncUnit; // special register unit
16 def IU1 : FuncUnit; // integer unit 1 (simple)
17 def IU2 : FuncUnit; // integer unit 2 (complex)
18 def FPU1 : FuncUnit; // floating point unit 1
19 def FPU2 : FuncUnit; // floating point unit 2
20 def VPU : FuncUnit; // vector permutation unit
21 def VIU1 : FuncUnit; // vector integer unit 1 (simple)
22 def VIU2 : FuncUnit; // vector integer unit 2 (complex)
23 def VFPU : FuncUnit; // vector floating point unit
25 //===----------------------------------------------------------------------===//
26 // Instruction Itinerary classes used for PowerPC
28 def IntSimple : InstrItinClass;
29 def IntGeneral : InstrItinClass;
30 def IntCompare : InstrItinClass;
31 def IntDivD : InstrItinClass;
32 def IntDivW : InstrItinClass;
33 def IntMFFS : InstrItinClass;
34 def IntMFVSCR : InstrItinClass;
35 def IntMTFSB0 : InstrItinClass;
36 def IntMTSRD : InstrItinClass;
37 def IntMulHD : InstrItinClass;
38 def IntMulHW : InstrItinClass;
39 def IntMulHWU : InstrItinClass;
40 def IntMulLI : InstrItinClass;
41 def IntRFID : InstrItinClass;
42 def IntRotateD : InstrItinClass;
43 def IntRotate : InstrItinClass;
44 def IntShift : InstrItinClass;
45 def IntTrapD : InstrItinClass;
46 def IntTrapW : InstrItinClass;
47 def BrB : InstrItinClass;
48 def BrCR : InstrItinClass;
49 def BrMCR : InstrItinClass;
50 def BrMCRX : InstrItinClass;
51 def LdStDCBA : InstrItinClass;
52 def LdStDCBF : InstrItinClass;
53 def LdStDCBI : InstrItinClass;
54 def LdStLoad : InstrItinClass;
55 def LdStStore : InstrItinClass;
56 def LdStDSS : InstrItinClass;
57 def LdStICBI : InstrItinClass;
58 def LdStUX : InstrItinClass;
59 def LdStLD : InstrItinClass;
60 def LdStLDARX : InstrItinClass;
61 def LdStLFD : InstrItinClass;
62 def LdStLFDU : InstrItinClass;
63 def LdStLHA : InstrItinClass;
64 def LdStLMW : InstrItinClass;
65 def LdStLVecX : InstrItinClass;
66 def LdStLWA : InstrItinClass;
67 def LdStLWARX : InstrItinClass;
68 def LdStSLBIA : InstrItinClass;
69 def LdStSLBIE : InstrItinClass;
70 def LdStSTD : InstrItinClass;
71 def LdStSTDCX : InstrItinClass;
72 def LdStSTVEBX : InstrItinClass;
73 def LdStSTWCX : InstrItinClass;
74 def LdStSync : InstrItinClass;
75 def SprISYNC : InstrItinClass;
76 def SprMFSR : InstrItinClass;
77 def SprMTMSR : InstrItinClass;
78 def SprMTSR : InstrItinClass;
79 def SprTLBSYNC : InstrItinClass;
80 def SprMFCR : InstrItinClass;
81 def SprMFMSR : InstrItinClass;
82 def SprMFSPR : InstrItinClass;
83 def SprMFTB : InstrItinClass;
84 def SprMTSPR : InstrItinClass;
85 def SprMTSRIN : InstrItinClass;
86 def SprRFI : InstrItinClass;
87 def SprSC : InstrItinClass;
88 def FPGeneral : InstrItinClass;
89 def FPCompare : InstrItinClass;
90 def FPDivD : InstrItinClass;
91 def FPDivS : InstrItinClass;
92 def FPFused : InstrItinClass;
93 def FPRes : InstrItinClass;
94 def FPSqrt : InstrItinClass;
95 def VecGeneral : InstrItinClass;
96 def VecFP : InstrItinClass;
97 def VecFPCompare : InstrItinClass;
98 def VecComplex : InstrItinClass;
99 def VecPerm : InstrItinClass;
100 def VecFPRound : InstrItinClass;
101 def VecVSL : InstrItinClass;
102 def VecVSR : InstrItinClass;
104 //===----------------------------------------------------------------------===//
105 // Processor instruction itineraries.
107 include "PPCScheduleG3.td"
108 include "PPCSchedule440.td"
109 include "PPCScheduleG4.td"
110 include "PPCScheduleG4Plus.td"
111 include "PPCScheduleG5.td"
112 include "PPCScheduleA2.td"
114 //===----------------------------------------------------------------------===//
115 // Instruction to itinerary class map - When add new opcodes to the supported
116 // set, refer to the following table to determine which itinerary class the
119 // opcode itinerary class
120 // ====== ===============
361 // tlbsync SprTLBSYNC
364 // vaddcuw VecGeneral
366 // vaddsbs VecGeneral
367 // vaddshs VecGeneral
368 // vaddsws VecGeneral
369 // vaddubm VecGeneral
370 // vaddubs VecGeneral
371 // vadduhm VecGeneral
372 // vadduhs VecGeneral
373 // vadduwm VecGeneral
374 // vadduws VecGeneral
385 // vcmpbfp VecFPCompare
386 // vcmpeqfp VecFPCompare
387 // vcmpequb VecGeneral
388 // vcmpequh VecGeneral
389 // vcmpequw VecGeneral
390 // vcmpgefp VecFPCompare
391 // vcmpgtfp VecFPCompare
392 // vcmpgtsb VecGeneral
393 // vcmpgtsh VecGeneral
394 // vcmpgtsw VecGeneral
395 // vcmpgtub VecGeneral
396 // vcmpgtuh VecGeneral
397 // vcmpgtuw VecGeneral
403 // vmaxfp VecFPCompare
410 // vmhaddshs VecComplex
411 // vmhraddshs VecComplex
412 // vminfp VecFPCompare
419 // vmladduhm VecComplex
427 // vmsummbm VecComplex
428 // vmsumshm VecComplex
429 // vmsumshs VecComplex
430 // vmsumubm VecComplex
431 // vmsumuhm VecComplex
432 // vmsumuhs VecComplex
433 // vmulesb VecComplex
434 // vmulesh VecComplex
435 // vmuleub VecComplex
436 // vmuleuh VecComplex
437 // vmulosb VecComplex
438 // vmulosh VecComplex
439 // vmuloub VecComplex
440 // vmulouh VecComplex
483 // vsubcuw VecGeneral
485 // vsubsbs VecGeneral
486 // vsubshs VecGeneral
487 // vsubsws VecGeneral
488 // vsububm VecGeneral
489 // vsububs VecGeneral
490 // vsubuhm VecGeneral
491 // vsubuhs VecGeneral
492 // vsubuwm VecGeneral
493 // vsubuws VecGeneral
494 // vsum2sws VecComplex
495 // vsum4sbs VecComplex
496 // vsum4shs VecComplex
497 // vsum4ubs VecComplex
498 // vsumsws VecComplex