1 //===- PPCSchedule.td - PowerPC Scheduling Definitions -----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by James M. Laskey and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "../Target.td"
12 //===----------------------------------------------------------------------===//
13 // Functional units across PowerPC chips sets
15 def BPU : FuncUnit; // Branch unit
16 def SLU : FuncUnit; // Store/load unit
17 def SRU : FuncUnit; // special register unit
18 def IU1 : FuncUnit; // integer unit 1 (simple)
19 def IU2 : FuncUnit; // integer unit 2 (complex)
20 def IU3 : FuncUnit; // integer unit 3 (7450 simple)
21 def IU4 : FuncUnit; // integer unit 4 (7450 simple)
22 def FPU1 : FuncUnit; // floating point unit 1
23 def FPU2 : FuncUnit; // floating point unit 2
24 def VPU : FuncUnit; // vector permutation unit
25 def VIU1 : FuncUnit; // vector integer unit 1 (simple)
26 def VIU2 : FuncUnit; // vector integer unit 2 (complex)
27 def VFPU : FuncUnit; // vector floating point unit
30 //===----------------------------------------------------------------------===//
31 // Instruction Itinerary classes used for PowerPC
33 def IntGeneral : InstrItinClass;
34 def IntCompare : InstrItinClass;
35 def IntDivD : InstrItinClass;
36 def IntDivW : InstrItinClass;
37 def IntMFFS : InstrItinClass;
38 def IntMFVSCR : InstrItinClass;
39 def IntMTFSB0 : InstrItinClass;
40 def IntMTSRD : InstrItinClass;
41 def IntMulHD : InstrItinClass;
42 def IntMulHW : InstrItinClass;
43 def IntMulHWU : InstrItinClass;
44 def IntMulLI : InstrItinClass;
45 def IntRFID : InstrItinClass;
46 def IntRotateD : InstrItinClass;
47 def IntRotate : InstrItinClass;
48 def IntShift : InstrItinClass;
49 def IntTrapD : InstrItinClass;
50 def IntTrapW : InstrItinClass;
51 def BrB : InstrItinClass;
52 def BrCR : InstrItinClass;
53 def BrMCR : InstrItinClass;
54 def BrMCRX : InstrItinClass;
55 def LdStDCBA : InstrItinClass;
56 def LdStDCBF : InstrItinClass;
57 def LdStDCBI : InstrItinClass;
58 def LdStDCBT : InstrItinClass;
59 def LdStDSS : InstrItinClass;
60 def LdStICBI : InstrItinClass;
61 def LdStLBZUX : InstrItinClass;
62 def LdStLD : InstrItinClass;
63 def LdStLDARX : InstrItinClass;
64 def LdStLFD : InstrItinClass;
65 def LdStLFDU : InstrItinClass;
66 def LdStLHA : InstrItinClass;
67 def LdStLMW : InstrItinClass;
68 def LdStLVEBX : InstrItinClass;
69 def LdStLWA : InstrItinClass;
70 def LdStLWARX : InstrItinClass;
71 def LdStSLBIA : InstrItinClass;
72 def LdStSLBIE : InstrItinClass;
73 def LdStSTD : InstrItinClass;
74 def LdStSTDCX : InstrItinClass;
75 def LdStSTVEBX : InstrItinClass;
76 def LdStSTWCX : InstrItinClass;
77 def LdStSync : InstrItinClass;
78 def SprISYNC : InstrItinClass;
79 def SprMFSR : InstrItinClass;
80 def SprMTMSR : InstrItinClass;
81 def SprMTSR : InstrItinClass;
82 def SprTLBSYNC : InstrItinClass;
83 def SprMFCR : InstrItinClass;
84 def SprMFMSR : InstrItinClass;
85 def SprMFSPR : InstrItinClass;
86 def SprMFTB : InstrItinClass;
87 def SprMTSPR : InstrItinClass;
88 def SprMTSRIN : InstrItinClass;
89 def SprRFI : InstrItinClass;
90 def SprSC : InstrItinClass;
91 def FPGeneral : InstrItinClass;
92 def FPCompare : InstrItinClass;
93 def FPDivD : InstrItinClass;
94 def FPDivS : InstrItinClass;
95 def FPFused : InstrItinClass;
96 def FPRes : InstrItinClass;
97 def FPSqrt : InstrItinClass;
98 def VecGeneral : InstrItinClass;
99 def VecFP : InstrItinClass;
100 def VecFPCompare : InstrItinClass;
101 def VecComplex : InstrItinClass;
102 def VecPerm : InstrItinClass;
103 def VecFPRound : InstrItinClass;
104 def VecVSL : InstrItinClass;
105 def VecVSR : InstrItinClass;
107 //===----------------------------------------------------------------------===//
108 // Processor instruction itineraries.
110 #include "PPCScheduleG3.td"
111 #include "PPCScheduleG4.td"
112 #include "PPCScheduleG4Plus.td"
113 #include "PPCScheduleG5.td"
115 //===----------------------------------------------------------------------===//
116 // Instruction to itinerary class map - When add new opcodes to the supported
117 // set, refer to the following table to determine which itinerary class the
120 // opcode itinerary class
121 // ====== ===============
362 // tlbsync SprTLBSYNC
365 // vaddcuw VecGeneral
367 // vaddsbs VecGeneral
368 // vaddshs VecGeneral
369 // vaddsws VecGeneral
370 // vaddubm VecGeneral
371 // vaddubs VecGeneral
372 // vadduhm VecGeneral
373 // vadduhs VecGeneral
374 // vadduwm VecGeneral
375 // vadduws VecGeneral
386 // vcmpbfp VecFPCompare
387 // vcmpeqfp VecFPCompare
388 // vcmpequb VecGeneral
389 // vcmpequh VecGeneral
390 // vcmpequw VecGeneral
391 // vcmpgefp VecFPCompare
392 // vcmpgtfp VecFPCompare
393 // vcmpgtsb VecGeneral
394 // vcmpgtsh VecGeneral
395 // vcmpgtsw VecGeneral
396 // vcmpgtub VecGeneral
397 // vcmpgtuh VecGeneral
398 // vcmpgtuw VecGeneral
404 // vmaxfp VecFPCompare
411 // vmhaddshs VecComplex
412 // vmhraddshs VecComplex
413 // vminfp VecFPCompare
420 // vmladduhm VecComplex
428 // vmsummbm VecComplex
429 // vmsumshm VecComplex
430 // vmsumshs VecComplex
431 // vmsumubm VecComplex
432 // vmsumuhm VecComplex
433 // vmsumuhs VecComplex
434 // vmulesb VecComplex
435 // vmulesh VecComplex
436 // vmuleub VecComplex
437 // vmuleuh VecComplex
438 // vmulosb VecComplex
439 // vmulosh VecComplex
440 // vmuloub VecComplex
441 // vmulouh VecComplex
484 // vsubcuw VecGeneral
486 // vsubsbs VecGeneral
487 // vsubshs VecGeneral
488 // vsubsws VecGeneral
489 // vsububm VecGeneral
490 // vsububs VecGeneral
491 // vsubuhm VecGeneral
492 // vsubuhs VecGeneral
493 // vsubuwm VecGeneral
494 // vsubuws VecGeneral
495 // vsum2sws VecComplex
496 // vsum4sbs VecComplex
497 // vsum4shs VecComplex
498 // vsum4ubs VecComplex
499 // vsumsws VecComplex
513 //===----------------------------------------------------------------------===//
514 // PowerPC Subtarget features.
517 def F64Bit : SubtargetFeature<"64bit",
518 "Should 64 bit instructions be used">;
519 def F64BitRegs : SubtargetFeature<"64bitregs",
520 "Should 64 bit registers be used">;
521 def FAltivec : SubtargetFeature<"altivec",
522 "Should Altivec instructions be used">;
523 def FGPUL : SubtargetFeature<"gpul",
524 "Should GPUL instructions be used">;
525 def FFSQRT : SubtargetFeature<"fsqrt",
526 "Should the fsqrt instruction be used">;
528 //===----------------------------------------------------------------------===//
529 // PowerPC chips sets supported
532 def : Processor<"601", G3Itineraries, []>;
533 def : Processor<"602", G3Itineraries, []>;
534 def : Processor<"603", G3Itineraries, []>;
535 def : Processor<"604", G3Itineraries, []>;
536 def : Processor<"750", G3Itineraries, []>;
537 def : Processor<"7400", G4Itineraries, [FAltivec]>;
538 def : Processor<"g4", G4Itineraries, [FAltivec]>;
539 def : Processor<"7450", G4PlusItineraries, [FAltivec]>;
540 def : Processor<"g4+", G4PlusItineraries, [FAltivec]>;
541 def : Processor<"970", G5Itineraries,
542 [FAltivec, FGPUL, FFSQRT, F64Bit, F64BitRegs]>;
543 def : Processor<"g5", G5Itineraries,
544 [FAltivec, FGPUL, FFSQRT, F64Bit, F64BitRegs]>;