1 //===-- PPCSchedule440.td - PPC 440 Scheduling Definitions -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 // PowerPC 440x6 Embedded Processor Core User's Manual.
12 // IBM (as updated in) 2010.
14 // The basic PPC 440 does not include a floating-point unit; the pipeline
15 // timings here are constructed to match the FP2 unit shipped with the
16 // PPC-440- and PPC-450-based Blue Gene (L and P) supercomputers.
18 // S. Chatterjee, et al. Design and exploitation of a high-performance
19 // SIMD floating-point unit for Blue Gene/L.
20 // IBM J. Res. & Dev. 49 (2/3) March/May 2005.
22 // Carlos Sosa and Brant Knudson. IBM System Blue Gene Solution:
23 // Blue Gene/P Application Development.
24 // IBM (as updated in) 2009.
26 //===----------------------------------------------------------------------===//
27 // Functional units on the PowerPC 440/450 chip sets
29 def IFTH1 : FuncUnit; // Fetch unit 1
30 def IFTH2 : FuncUnit; // Fetch unit 2
31 def PDCD1 : FuncUnit; // Decode unit 1
32 def PDCD2 : FuncUnit; // Decode unit 2
33 def DISS1 : FuncUnit; // Issue unit 1
34 def DISS2 : FuncUnit; // Issue unit 2
35 def LRACC : FuncUnit; // Register access and dispatch for
36 // the simple integer (J-pipe) and
37 // load/store (L-pipe) pipelines
38 def IRACC : FuncUnit; // Register access and dispatch for
39 // the complex integer (I-pipe) pipeline
40 def FRACC : FuncUnit; // Register access and dispatch for
41 // the floating-point execution (F-pipe) pipeline
42 def IEXE1 : FuncUnit; // Execution stage 1 for the I pipeline
43 def IEXE2 : FuncUnit; // Execution stage 2 for the I pipeline
44 def IWB : FuncUnit; // Write-back unit for the I pipeline
45 def JEXE1 : FuncUnit; // Execution stage 1 for the J pipeline
46 def JEXE2 : FuncUnit; // Execution stage 2 for the J pipeline
47 def JWB : FuncUnit; // Write-back unit for the J pipeline
48 def AGEN : FuncUnit; // Address generation for the L pipeline
49 def CRD : FuncUnit; // D-cache access for the L pipeline
50 def LWB : FuncUnit; // Write-back unit for the L pipeline
51 def FEXE1 : FuncUnit; // Execution stage 1 for the F pipeline
52 def FEXE2 : FuncUnit; // Execution stage 2 for the F pipeline
53 def FEXE3 : FuncUnit; // Execution stage 3 for the F pipeline
54 def FEXE4 : FuncUnit; // Execution stage 4 for the F pipeline
55 def FEXE5 : FuncUnit; // Execution stage 5 for the F pipeline
56 def FEXE6 : FuncUnit; // Execution stage 6 for the F pipeline
57 def FWB : FuncUnit; // Write-back unit for the F pipeline
59 def LWARX_Hold : FuncUnit; // This is a pseudo-unit which is used
60 // to make sure that no lwarx/stwcx.
61 // instructions are issued while another
62 // lwarx/stwcx. is in the L pipe.
64 def GPR_Bypass : Bypass; // The bypass for general-purpose regs.
65 def FPR_Bypass : Bypass; // The bypass for floating-point regs.
68 // Instructions are held in the FRACC, LRACC and IRACC pipeline
69 // stages until their source operands become ready. Exceptions:
70 // - Store instructions will hold in the AGEN stage
71 // - The integer multiply-accumulate instruction will hold in
74 // For most I-pipe operations, the result is available at the end of
75 // the IEXE1 stage. Operations such as multiply and divide must
76 // continue to execute in IEXE2 and IWB. Divide resides in IWB for
77 // 33 cycles (multiply also calculates its result in IWB). For all
78 // J-pipe instructions, the result is available
79 // at the end of the JEXE1 stage. Loads have a 3-cycle latency
80 // (data is not available until after the LWB stage).
82 // The L1 cache hit latency is four cycles for floating point loads
83 // and three cycles for integer loads.
85 // The stwcx. instruction requires both the LRACC and the IRACC
86 // dispatch stages. It must be issued from DISS0.
88 // All lwarx/stwcx. instructions hold in LRACC if another
89 // uncommitted lwarx/stwcx. is in AGEN, CRD, or LWB.
91 // msync (a.k.a. sync) and mbar will hold in LWB until all load/store
92 // resources are empty. AGEN and CRD are held empty until the msync/mbar
95 // Most floating-point instructions, computational and move,
96 // have a 5-cycle latency. Divide takes longer (30 cycles). Instructions that
97 // update the CR take 2 cycles. Stores take 3 cycles and, as mentioned above,
98 // loads take 4 cycles (for L1 hit).
101 // This file defines the itinerary class data for the PPC 440 processor.
103 //===----------------------------------------------------------------------===//
106 def PPC440Itineraries : ProcessorItineraries<
107 [IFTH1, IFTH2, PDCD1, PDCD2, DISS1, DISS2, FRACC,
108 IRACC, IEXE1, IEXE2, IWB, LRACC, JEXE1, JEXE2, JWB, AGEN, CRD, LWB,
109 FEXE1, FEXE2, FEXE3, FEXE4, FEXE5, FEXE6, FWB, LWARX_Hold],
110 [GPR_Bypass, FPR_Bypass], [
111 InstrItinData<IntGeneral , [InstrStage<1, [IFTH1, IFTH2]>,
112 InstrStage<1, [PDCD1, PDCD2]>,
113 InstrStage<1, [DISS1, DISS2]>,
114 InstrStage<1, [IRACC, LRACC]>,
115 InstrStage<1, [IEXE1, JEXE1]>,
116 InstrStage<1, [IEXE2, JEXE2]>,
117 InstrStage<1, [IWB, JWB]>],
119 [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
120 InstrItinData<IntCompare , [InstrStage<1, [IFTH1, IFTH2]>,
121 InstrStage<1, [PDCD1, PDCD2]>,
122 InstrStage<1, [DISS1, DISS2]>,
123 InstrStage<1, [IRACC, LRACC]>,
124 InstrStage<1, [IEXE1, JEXE1]>,
125 InstrStage<1, [IEXE2, JEXE2]>,
126 InstrStage<1, [IWB, JWB]>],
128 [NoBypass, GPR_Bypass, GPR_Bypass]>,
129 InstrItinData<IntDivW , [InstrStage<1, [IFTH1, IFTH2]>,
130 InstrStage<1, [PDCD1, PDCD2]>,
131 InstrStage<1, [DISS1, DISS2]>,
132 InstrStage<1, [IRACC]>,
133 InstrStage<1, [IEXE1]>,
134 InstrStage<1, [IEXE2]>,
135 InstrStage<33, [IWB]>],
137 [NoBypass, GPR_Bypass, GPR_Bypass]>,
138 InstrItinData<IntMFFS , [InstrStage<1, [IFTH1, IFTH2]>,
139 InstrStage<1, [PDCD1, PDCD2]>,
140 InstrStage<1, [DISS1, DISS2]>,
141 InstrStage<1, [IRACC]>,
142 InstrStage<1, [IEXE1]>,
143 InstrStage<1, [IEXE2]>,
144 InstrStage<1, [IWB]>],
146 [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
147 InstrItinData<IntMTFSB0 , [InstrStage<1, [IFTH1, IFTH2]>,
148 InstrStage<1, [PDCD1, PDCD2]>,
149 InstrStage<1, [DISS1, DISS2]>,
150 InstrStage<1, [IRACC]>,
151 InstrStage<1, [IEXE1]>,
152 InstrStage<1, [IEXE2]>,
153 InstrStage<1, [IWB]>],
155 [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
156 InstrItinData<IntMulHW , [InstrStage<1, [IFTH1, IFTH2]>,
157 InstrStage<1, [PDCD1, PDCD2]>,
158 InstrStage<1, [DISS1, DISS2]>,
159 InstrStage<1, [IRACC]>,
160 InstrStage<1, [IEXE1]>,
161 InstrStage<1, [IEXE2]>,
162 InstrStage<1, [IWB]>],
164 [NoBypass, GPR_Bypass, GPR_Bypass]>,
165 InstrItinData<IntMulHWU , [InstrStage<1, [IFTH1, IFTH2]>,
166 InstrStage<1, [PDCD1, PDCD2]>,
167 InstrStage<1, [DISS1, DISS2]>,
168 InstrStage<1, [IRACC]>,
169 InstrStage<1, [IEXE1]>,
170 InstrStage<1, [IEXE2]>,
171 InstrStage<1, [IWB]>],
173 [NoBypass, GPR_Bypass, GPR_Bypass]>,
174 InstrItinData<IntMulLI , [InstrStage<1, [IFTH1, IFTH2]>,
175 InstrStage<1, [PDCD1, PDCD2]>,
176 InstrStage<1, [DISS1, DISS2]>,
177 InstrStage<1, [IRACC]>,
178 InstrStage<1, [IEXE1]>,
179 InstrStage<1, [IEXE2]>,
180 InstrStage<1, [IWB]>],
182 [NoBypass, GPR_Bypass, GPR_Bypass]>,
183 InstrItinData<IntRotate , [InstrStage<1, [IFTH1, IFTH2]>,
184 InstrStage<1, [PDCD1, PDCD2]>,
185 InstrStage<1, [DISS1, DISS2]>,
186 InstrStage<1, [IRACC, LRACC]>,
187 InstrStage<1, [IEXE1, JEXE1]>,
188 InstrStage<1, [IEXE2, JEXE2]>,
189 InstrStage<1, [IWB, JWB]>],
191 [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
192 InstrItinData<IntShift , [InstrStage<1, [IFTH1, IFTH2]>,
193 InstrStage<1, [PDCD1, PDCD2]>,
194 InstrStage<1, [DISS1, DISS2]>,
195 InstrStage<1, [IRACC, LRACC]>,
196 InstrStage<1, [IEXE1, JEXE1]>,
197 InstrStage<1, [IEXE2, JEXE2]>,
198 InstrStage<1, [IWB, JWB]>],
200 [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
201 InstrItinData<IntTrapW , [InstrStage<1, [IFTH1, IFTH2]>,
202 InstrStage<1, [PDCD1, PDCD2]>,
203 InstrStage<1, [DISS1, DISS2]>,
204 InstrStage<1, [IRACC]>,
205 InstrStage<1, [IEXE1]>,
206 InstrStage<1, [IEXE2]>,
207 InstrStage<1, [IWB]>],
209 [GPR_Bypass, GPR_Bypass]>,
210 InstrItinData<BrB , [InstrStage<1, [IFTH1, IFTH2]>,
211 InstrStage<1, [PDCD1, PDCD2]>,
212 InstrStage<1, [DISS1, DISS2]>,
213 InstrStage<1, [IRACC]>,
214 InstrStage<1, [IEXE1]>,
215 InstrStage<1, [IEXE2]>,
216 InstrStage<1, [IWB]>],
218 [NoBypass, GPR_Bypass]>,
219 InstrItinData<BrCR , [InstrStage<1, [IFTH1, IFTH2]>,
220 InstrStage<1, [PDCD1, PDCD2]>,
221 InstrStage<1, [DISS1, DISS2]>,
222 InstrStage<1, [IRACC]>,
223 InstrStage<1, [IEXE1]>,
224 InstrStage<1, [IEXE2]>,
225 InstrStage<1, [IWB]>],
227 [NoBypass, GPR_Bypass, GPR_Bypass]>,
228 InstrItinData<BrMCR , [InstrStage<1, [IFTH1, IFTH2]>,
229 InstrStage<1, [PDCD1, PDCD2]>,
230 InstrStage<1, [DISS1, DISS2]>,
231 InstrStage<1, [IRACC]>,
232 InstrStage<1, [IEXE1]>,
233 InstrStage<1, [IEXE2]>,
234 InstrStage<1, [IWB]>],
236 [NoBypass, GPR_Bypass, GPR_Bypass]>,
237 InstrItinData<BrMCRX , [InstrStage<1, [IFTH1, IFTH2]>,
238 InstrStage<1, [PDCD1, PDCD2]>,
239 InstrStage<1, [DISS1, DISS2]>,
240 InstrStage<1, [IRACC]>,
241 InstrStage<1, [IEXE1]>,
242 InstrStage<1, [IEXE2]>,
243 InstrStage<1, [IWB]>],
245 [NoBypass, GPR_Bypass, GPR_Bypass]>,
246 InstrItinData<LdStDCBA , [InstrStage<1, [IFTH1, IFTH2]>,
247 InstrStage<1, [PDCD1, PDCD2]>,
248 InstrStage<1, [DISS1, DISS2]>,
249 InstrStage<1, [LRACC]>,
250 InstrStage<1, [AGEN]>,
251 InstrStage<1, [CRD]>,
252 InstrStage<1, [LWB]>],
254 [NoBypass, GPR_Bypass]>,
255 InstrItinData<LdStDCBF , [InstrStage<1, [IFTH1, IFTH2]>,
256 InstrStage<1, [PDCD1, PDCD2]>,
257 InstrStage<1, [DISS1, DISS2]>,
258 InstrStage<1, [LRACC]>,
259 InstrStage<1, [AGEN]>,
260 InstrStage<1, [CRD]>,
261 InstrStage<1, [LWB]>],
263 [NoBypass, GPR_Bypass]>,
264 InstrItinData<LdStDCBI , [InstrStage<1, [IFTH1, IFTH2]>,
265 InstrStage<1, [PDCD1, PDCD2]>,
266 InstrStage<1, [DISS1, DISS2]>,
267 InstrStage<1, [LRACC]>,
268 InstrStage<1, [AGEN]>,
269 InstrStage<1, [CRD]>,
270 InstrStage<1, [LWB]>],
272 [NoBypass, GPR_Bypass]>,
273 InstrItinData<LdStLoad , [InstrStage<1, [IFTH1, IFTH2]>,
274 InstrStage<1, [PDCD1, PDCD2]>,
275 InstrStage<1, [DISS1, DISS2]>,
276 InstrStage<1, [LRACC]>,
277 InstrStage<1, [AGEN]>,
278 InstrStage<1, [CRD]>,
279 InstrStage<2, [LWB]>],
281 [GPR_Bypass, GPR_Bypass]>,
282 InstrItinData<LdStStore , [InstrStage<1, [IFTH1, IFTH2]>,
283 InstrStage<1, [PDCD1, PDCD2]>,
284 InstrStage<1, [DISS1, DISS2]>,
285 InstrStage<1, [LRACC]>,
286 InstrStage<1, [AGEN]>,
287 InstrStage<1, [CRD]>,
288 InstrStage<2, [LWB]>],
290 [NoBypass, GPR_Bypass]>,
291 InstrItinData<LdStICBI , [InstrStage<1, [IFTH1, IFTH2]>,
292 InstrStage<1, [PDCD1, PDCD2]>,
293 InstrStage<1, [DISS1, DISS2]>,
294 InstrStage<1, [LRACC]>,
295 InstrStage<1, [AGEN]>,
296 InstrStage<1, [CRD]>,
297 InstrStage<1, [LWB]>],
299 [NoBypass, GPR_Bypass]>,
300 InstrItinData<LdStUX , [InstrStage<1, [IFTH1, IFTH2]>,
301 InstrStage<1, [PDCD1, PDCD2]>,
302 InstrStage<1, [DISS1, DISS2]>,
303 InstrStage<1, [LRACC]>,
304 InstrStage<1, [AGEN]>,
305 InstrStage<1, [CRD]>,
306 InstrStage<1, [LWB]>],
308 [NoBypass, GPR_Bypass, GPR_Bypass]>,
309 InstrItinData<LdStLFD , [InstrStage<1, [IFTH1, IFTH2]>,
310 InstrStage<1, [PDCD1, PDCD2]>,
311 InstrStage<1, [DISS1, DISS2]>,
312 InstrStage<1, [LRACC]>,
313 InstrStage<1, [AGEN]>,
314 InstrStage<1, [CRD]>,
315 InstrStage<2, [LWB]>],
317 [NoBypass, GPR_Bypass, GPR_Bypass]>,
318 InstrItinData<LdStLFDU , [InstrStage<1, [IFTH1, IFTH2]>,
319 InstrStage<1, [PDCD1, PDCD2]>,
320 InstrStage<1, [DISS1, DISS2]>,
321 InstrStage<1, [LRACC]>,
322 InstrStage<1, [AGEN]>,
323 InstrStage<1, [CRD]>,
324 InstrStage<1, [LWB]>],
326 [NoBypass, GPR_Bypass, GPR_Bypass]>,
327 InstrItinData<LdStLHA , [InstrStage<1, [IFTH1, IFTH2]>,
328 InstrStage<1, [PDCD1, PDCD2]>,
329 InstrStage<1, [DISS1, DISS2]>,
330 InstrStage<1, [LRACC]>,
331 InstrStage<1, [AGEN]>,
332 InstrStage<1, [CRD]>,
333 InstrStage<1, [LWB]>],
335 [NoBypass, GPR_Bypass]>,
336 InstrItinData<LdStLMW , [InstrStage<1, [IFTH1, IFTH2]>,
337 InstrStage<1, [PDCD1, PDCD2]>,
338 InstrStage<1, [DISS1, DISS2]>,
339 InstrStage<1, [LRACC]>,
340 InstrStage<1, [AGEN]>,
341 InstrStage<1, [CRD]>,
342 InstrStage<1, [LWB]>],
344 [NoBypass, GPR_Bypass]>,
345 InstrItinData<LdStLWARX , [InstrStage<1, [IFTH1, IFTH2]>,
346 InstrStage<1, [PDCD1, PDCD2]>,
347 InstrStage<1, [DISS1]>,
348 InstrStage<1, [IRACC], 0>,
349 InstrStage<4, [LWARX_Hold], 0>,
350 InstrStage<1, [LRACC]>,
351 InstrStage<1, [AGEN]>,
352 InstrStage<1, [CRD]>,
353 InstrStage<1, [LWB]>],
355 [NoBypass, GPR_Bypass]>,
356 InstrItinData<LdStSTD , [InstrStage<1, [IFTH1, IFTH2]>,
357 InstrStage<1, [PDCD1, PDCD2]>,
358 InstrStage<1, [DISS1, DISS2]>,
359 InstrStage<1, [LRACC]>,
360 InstrStage<1, [AGEN]>,
361 InstrStage<1, [CRD]>,
362 InstrStage<2, [LWB]>],
364 [NoBypass, GPR_Bypass]>,
365 InstrItinData<LdStSTDCX , [InstrStage<1, [IFTH1, IFTH2]>,
366 InstrStage<1, [PDCD1, PDCD2]>,
367 InstrStage<1, [DISS1]>,
368 InstrStage<1, [IRACC], 0>,
369 InstrStage<4, [LWARX_Hold], 0>,
370 InstrStage<1, [LRACC]>,
371 InstrStage<1, [AGEN]>,
372 InstrStage<1, [CRD]>,
373 InstrStage<1, [LWB]>],
375 [NoBypass, GPR_Bypass]>,
376 InstrItinData<LdStSTWCX , [InstrStage<1, [IFTH1, IFTH2]>,
377 InstrStage<1, [PDCD1, PDCD2]>,
378 InstrStage<1, [DISS1]>,
379 InstrStage<1, [IRACC], 0>,
380 InstrStage<4, [LWARX_Hold], 0>,
381 InstrStage<1, [LRACC]>,
382 InstrStage<1, [AGEN]>,
383 InstrStage<1, [CRD]>,
384 InstrStage<1, [LWB]>],
386 [NoBypass, GPR_Bypass]>,
387 InstrItinData<LdStSync , [InstrStage<1, [IFTH1, IFTH2]>,
388 InstrStage<1, [PDCD1, PDCD2]>,
389 InstrStage<1, [DISS1, DISS2]>,
390 InstrStage<1, [LRACC]>,
391 InstrStage<3, [AGEN], 1>,
392 InstrStage<2, [CRD], 1>,
393 InstrStage<1, [LWB]>]>,
394 InstrItinData<SprISYNC , [InstrStage<1, [IFTH1, IFTH2]>,
395 InstrStage<1, [PDCD1, PDCD2]>,
396 InstrStage<1, [DISS1, DISS2]>,
397 InstrStage<1, [FRACC], 0>,
398 InstrStage<1, [LRACC], 0>,
399 InstrStage<1, [IRACC]>,
400 InstrStage<1, [FEXE1], 0>,
401 InstrStage<1, [AGEN], 0>,
402 InstrStage<1, [JEXE1], 0>,
403 InstrStage<1, [IEXE1]>,
404 InstrStage<1, [FEXE2], 0>,
405 InstrStage<1, [CRD], 0>,
406 InstrStage<1, [JEXE2], 0>,
407 InstrStage<1, [IEXE2]>,
408 InstrStage<6, [FEXE3], 0>,
409 InstrStage<6, [LWB], 0>,
410 InstrStage<6, [JWB], 0>,
411 InstrStage<6, [IWB]>]>,
412 InstrItinData<SprMFSR , [InstrStage<1, [IFTH1, IFTH2]>,
413 InstrStage<1, [PDCD1, PDCD2]>,
414 InstrStage<1, [DISS1, DISS2]>,
415 InstrStage<1, [IRACC]>,
416 InstrStage<1, [IEXE1]>,
417 InstrStage<1, [IEXE2]>,
418 InstrStage<1, [IWB]>],
420 [GPR_Bypass, GPR_Bypass]>,
421 InstrItinData<SprMTMSR , [InstrStage<1, [IFTH1, IFTH2]>,
422 InstrStage<1, [PDCD1, PDCD2]>,
423 InstrStage<1, [DISS1, DISS2]>,
424 InstrStage<1, [IRACC]>,
425 InstrStage<1, [IEXE1]>,
426 InstrStage<1, [IEXE2]>,
427 InstrStage<1, [IWB]>],
429 [GPR_Bypass, GPR_Bypass]>,
430 InstrItinData<SprMTSR , [InstrStage<1, [IFTH1, IFTH2]>,
431 InstrStage<1, [PDCD1, PDCD2]>,
432 InstrStage<1, [DISS1, DISS2]>,
433 InstrStage<1, [IRACC]>,
434 InstrStage<1, [IEXE1]>,
435 InstrStage<1, [IEXE2]>,
436 InstrStage<3, [IWB]>],
438 [NoBypass, GPR_Bypass]>,
439 InstrItinData<SprTLBSYNC , [InstrStage<1, [IFTH1, IFTH2]>,
440 InstrStage<1, [PDCD1, PDCD2]>,
441 InstrStage<1, [DISS1, DISS2]>,
442 InstrStage<1, [IRACC]>,
443 InstrStage<1, [IEXE1]>,
444 InstrStage<1, [IEXE2]>,
445 InstrStage<1, [IWB]>]>,
446 InstrItinData<SprMFCR , [InstrStage<1, [IFTH1, IFTH2]>,
447 InstrStage<1, [PDCD1, PDCD2]>,
448 InstrStage<1, [DISS1, DISS2]>,
449 InstrStage<1, [IRACC]>,
450 InstrStage<1, [IEXE1]>,
451 InstrStage<1, [IEXE2]>,
452 InstrStage<1, [IWB]>],
454 [NoBypass, GPR_Bypass]>,
455 InstrItinData<SprMFMSR , [InstrStage<1, [IFTH1, IFTH2]>,
456 InstrStage<1, [PDCD1, PDCD2]>,
457 InstrStage<1, [DISS1, DISS2]>,
458 InstrStage<1, [IRACC]>,
459 InstrStage<1, [IEXE1]>,
460 InstrStage<1, [IEXE2]>,
461 InstrStage<1, [IWB]>],
463 [GPR_Bypass, GPR_Bypass]>,
464 InstrItinData<SprMFSPR , [InstrStage<1, [IFTH1, IFTH2]>,
465 InstrStage<1, [PDCD1, PDCD2]>,
466 InstrStage<1, [DISS1, DISS2]>,
467 InstrStage<1, [IRACC]>,
468 InstrStage<1, [IEXE1]>,
469 InstrStage<1, [IEXE2]>,
470 InstrStage<3, [IWB]>],
472 [NoBypass, GPR_Bypass]>,
473 InstrItinData<SprMFTB , [InstrStage<1, [IFTH1, IFTH2]>,
474 InstrStage<1, [PDCD1, PDCD2]>,
475 InstrStage<1, [DISS1, DISS2]>,
476 InstrStage<1, [IRACC]>,
477 InstrStage<1, [IEXE1]>,
478 InstrStage<1, [IEXE2]>,
479 InstrStage<3, [IWB]>],
481 [NoBypass, GPR_Bypass]>,
482 InstrItinData<SprMTSPR , [InstrStage<1, [IFTH1, IFTH2]>,
483 InstrStage<1, [PDCD1, PDCD2]>,
484 InstrStage<1, [DISS1, DISS2]>,
485 InstrStage<1, [IRACC]>,
486 InstrStage<1, [IEXE1]>,
487 InstrStage<1, [IEXE2]>,
488 InstrStage<3, [IWB]>],
490 [NoBypass, GPR_Bypass]>,
491 InstrItinData<SprMTSRIN , [InstrStage<1, [IFTH1, IFTH2]>,
492 InstrStage<1, [PDCD1, PDCD2]>,
493 InstrStage<1, [DISS1, DISS2]>,
494 InstrStage<1, [IRACC]>,
495 InstrStage<1, [IEXE1]>,
496 InstrStage<1, [IEXE2]>,
497 InstrStage<3, [IWB]>],
499 [NoBypass, GPR_Bypass]>,
500 InstrItinData<SprRFI , [InstrStage<1, [IFTH1, IFTH2]>,
501 InstrStage<1, [PDCD1, PDCD2]>,
502 InstrStage<1, [DISS1, DISS2]>,
503 InstrStage<1, [IRACC]>,
504 InstrStage<1, [IEXE1]>,
505 InstrStage<1, [IEXE2]>,
506 InstrStage<1, [IWB]>],
508 [NoBypass, GPR_Bypass]>,
509 InstrItinData<SprSC , [InstrStage<1, [IFTH1, IFTH2]>,
510 InstrStage<1, [PDCD1, PDCD2]>,
511 InstrStage<1, [DISS1, DISS2]>,
512 InstrStage<1, [IRACC]>,
513 InstrStage<1, [IEXE1]>,
514 InstrStage<1, [IEXE2]>,
515 InstrStage<1, [IWB]>],
517 [NoBypass, GPR_Bypass]>,
518 InstrItinData<FPGeneral , [InstrStage<1, [IFTH1, IFTH2]>,
519 InstrStage<1, [PDCD1, PDCD2]>,
520 InstrStage<1, [DISS1, DISS2]>,
521 InstrStage<1, [FRACC]>,
522 InstrStage<1, [FEXE1]>,
523 InstrStage<1, [FEXE2]>,
524 InstrStage<1, [FEXE3]>,
525 InstrStage<1, [FEXE4]>,
526 InstrStage<1, [FEXE5]>,
527 InstrStage<1, [FEXE6]>,
528 InstrStage<1, [FWB]>],
530 [FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
531 InstrItinData<FPCompare , [InstrStage<1, [IFTH1, IFTH2]>,
532 InstrStage<1, [PDCD1, PDCD2]>,
533 InstrStage<1, [DISS1, DISS2]>,
534 InstrStage<1, [FRACC]>,
535 InstrStage<1, [FEXE1]>,
536 InstrStage<1, [FEXE2]>,
537 InstrStage<1, [FEXE3]>,
538 InstrStage<1, [FEXE4]>,
539 InstrStage<1, [FEXE5]>,
540 InstrStage<1, [FEXE6]>,
541 InstrStage<1, [FWB]>],
543 [FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
544 InstrItinData<FPDivD , [InstrStage<1, [IFTH1, IFTH2]>,
545 InstrStage<1, [PDCD1, PDCD2]>,
546 InstrStage<1, [DISS1, DISS2]>,
547 InstrStage<1, [FRACC]>,
548 InstrStage<1, [FEXE1]>,
549 InstrStage<1, [FEXE2]>,
550 InstrStage<1, [FEXE3]>,
551 InstrStage<1, [FEXE4]>,
552 InstrStage<1, [FEXE5]>,
553 InstrStage<1, [FEXE6]>,
554 InstrStage<25, [FWB]>],
556 [NoBypass, FPR_Bypass, FPR_Bypass]>,
557 InstrItinData<FPDivS , [InstrStage<1, [IFTH1, IFTH2]>,
558 InstrStage<1, [PDCD1, PDCD2]>,
559 InstrStage<1, [DISS1, DISS2]>,
560 InstrStage<1, [FRACC]>,
561 InstrStage<1, [FEXE1]>,
562 InstrStage<1, [FEXE2]>,
563 InstrStage<1, [FEXE3]>,
564 InstrStage<1, [FEXE4]>,
565 InstrStage<1, [FEXE5]>,
566 InstrStage<1, [FEXE6]>,
567 InstrStage<13, [FWB]>],
569 [NoBypass, FPR_Bypass, FPR_Bypass]>,
570 InstrItinData<FPFused , [InstrStage<1, [IFTH1, IFTH2]>,
571 InstrStage<1, [PDCD1, PDCD2]>,
572 InstrStage<1, [DISS1, DISS2]>,
573 InstrStage<1, [FRACC]>,
574 InstrStage<1, [FEXE1]>,
575 InstrStage<1, [FEXE2]>,
576 InstrStage<1, [FEXE3]>,
577 InstrStage<1, [FEXE4]>,
578 InstrStage<1, [FEXE5]>,
579 InstrStage<1, [FEXE6]>,
580 InstrStage<1, [FWB]>],
582 [FPR_Bypass, FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
583 InstrItinData<FPRes , [InstrStage<1, [IFTH1, IFTH2]>,
584 InstrStage<1, [PDCD1, PDCD2]>,
585 InstrStage<1, [DISS1, DISS2]>,
586 InstrStage<1, [FRACC]>,
587 InstrStage<1, [FEXE1]>,
588 InstrStage<1, [FEXE2]>,
589 InstrStage<1, [FEXE3]>,
590 InstrStage<1, [FEXE4]>,
591 InstrStage<1, [FEXE5]>,
592 InstrStage<1, [FEXE6]>,
593 InstrStage<1, [FWB]>],
595 [FPR_Bypass, FPR_Bypass]>