1 //===- PPCScheduleA2.td - PPC A2 Scheduling Definitions --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 // A2 Processor User's Manual.
12 // IBM (as updated in) 2010.
14 //===----------------------------------------------------------------------===//
15 // Functional units on the PowerPC A2 chip sets
17 def XU : FuncUnit; // XU pipeline
18 def FU : FuncUnit; // FI pipeline
21 // This file defines the itinerary class data for the PPC A2 processor.
23 //===----------------------------------------------------------------------===//
26 def PPCA2Itineraries : ProcessorItineraries<
28 InstrItinData<IntSimple , [InstrStage<1, [XU]>],
30 InstrItinData<IntGeneral , [InstrStage<1, [XU]>],
32 InstrItinData<IntCompare , [InstrStage<1, [XU]>],
34 InstrItinData<IntDivW , [InstrStage<1, [XU]>],
36 InstrItinData<IntDivD , [InstrStage<1, [XU]>],
38 InstrItinData<IntMulHW , [InstrStage<1, [XU]>],
40 InstrItinData<IntMulHWU , [InstrStage<1, [XU]>],
42 InstrItinData<IntMulLI , [InstrStage<1, [XU]>],
44 InstrItinData<IntRotate , [InstrStage<1, [XU]>],
46 InstrItinData<IntRotateD , [InstrStage<1, [XU]>],
48 InstrItinData<IntRotateDI , [InstrStage<1, [XU]>],
50 InstrItinData<IntShift , [InstrStage<1, [XU]>],
52 InstrItinData<IntTrapW , [InstrStage<1, [XU]>],
54 InstrItinData<IntTrapD , [InstrStage<1, [XU]>],
56 InstrItinData<BrB , [InstrStage<1, [XU]>],
58 InstrItinData<BrCR , [InstrStage<1, [XU]>],
60 InstrItinData<BrMCR , [InstrStage<1, [XU]>],
62 InstrItinData<BrMCRX , [InstrStage<1, [XU]>],
64 InstrItinData<LdStDCBA , [InstrStage<1, [XU]>],
66 InstrItinData<LdStDCBF , [InstrStage<1, [XU]>],
68 InstrItinData<LdStDCBI , [InstrStage<1, [XU]>],
70 InstrItinData<LdStLoad , [InstrStage<1, [XU]>],
72 InstrItinData<LdStLoadUpd , [InstrStage<1, [XU]>],
74 InstrItinData<LdStLDU , [InstrStage<1, [XU]>],
76 InstrItinData<LdStStore , [InstrStage<1, [XU]>],
78 InstrItinData<LdStStoreUpd, [InstrStage<1, [XU]>],
80 InstrItinData<LdStICBI, [InstrStage<1, [XU]>],
82 InstrItinData<LdStSTFD , [InstrStage<1, [XU]>],
84 InstrItinData<LdStSTFDU , [InstrStage<1, [XU]>],
86 InstrItinData<LdStLFD , [InstrStage<1, [XU]>],
88 InstrItinData<LdStLFDU , [InstrStage<1, [XU]>],
90 InstrItinData<LdStLHA , [InstrStage<1, [XU]>],
92 InstrItinData<LdStLHAU , [InstrStage<1, [XU]>],
94 InstrItinData<LdStLWARX , [InstrStage<1, [XU]>],
95 [82, 1, 1]>, // L2 latency
96 InstrItinData<LdStSTD , [InstrStage<1, [XU]>],
98 InstrItinData<LdStSTDU , [InstrStage<1, [XU]>],
100 InstrItinData<LdStSTDCX , [InstrStage<1, [XU]>],
101 [82, 1, 1]>, // L2 latency
102 InstrItinData<LdStSTWCX , [InstrStage<1, [XU]>],
103 [82, 1, 1]>, // L2 latency
104 InstrItinData<LdStSync , [InstrStage<1, [XU]>],
106 InstrItinData<SprISYNC , [InstrStage<1, [XU]>],
108 InstrItinData<SprMTMSR , [InstrStage<1, [XU]>],
110 InstrItinData<SprMFCR , [InstrStage<1, [XU]>],
112 InstrItinData<SprMFMSR , [InstrStage<1, [XU]>],
114 InstrItinData<SprMFSPR , [InstrStage<1, [XU]>],
116 InstrItinData<SprMFTB , [InstrStage<1, [XU]>],
118 InstrItinData<SprMTSPR , [InstrStage<1, [XU]>],
120 InstrItinData<SprRFI , [InstrStage<1, [XU]>],
122 InstrItinData<SprSC , [InstrStage<1, [XU]>],
124 InstrItinData<FPGeneral , [InstrStage<1, [FU]>],
126 InstrItinData<FPAddSub , [InstrStage<1, [FU]>],
128 InstrItinData<FPCompare , [InstrStage<1, [FU]>],
130 InstrItinData<FPDivD , [InstrStage<1, [FU]>],
132 InstrItinData<FPDivS , [InstrStage<1, [FU]>],
134 InstrItinData<FPSqrt , [InstrStage<1, [FU]>],
136 InstrItinData<FPFused , [InstrStage<1, [FU]>],
138 InstrItinData<FPRes , [InstrStage<1, [FU]>],
142 // ===---------------------------------------------------------------------===//
143 // A2 machine model for scheduling and other instruction cost heuristics.
145 def PPCA2Model : SchedMachineModel {
146 let IssueWidth = 1; // 2 micro-ops are dispatched per cycle.
147 let MinLatency = -1; // OperandCycles are interpreted as MinLatency.
148 let LoadLatency = 6; // Optimistic load latency assuming bypass.
149 // This is overriden by OperandCycles if the
150 // Itineraries are queried instead.
151 let MispredictPenalty = 13;
153 let Itineraries = PPCA2Itineraries;